azt3328.h 15 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef __SOUND_AZT3328_H
  3. #define __SOUND_AZT3328_H
  4. /* "PU" == "power-up value", as tested on PCI168 PCI rev. 10
  5. * "WRITE_ONLY" == register does not indicate actual bit values */
  6. /*** main I/O area port indices ***/
  7. /* (only 0x70 of 0x80 bytes saved/restored by Windows driver) */
  8. #define AZF_IO_SIZE_CTRL 0x80
  9. #define AZF_IO_SIZE_CTRL_PM 0x70
  10. /* the driver initialisation suggests a layout of 4 areas
  11. * within the main card control I/O:
  12. * from 0x00 (playback codec), from 0x20 (recording codec)
  13. * and from 0x40 (most certainly I2S out codec).
  14. * And another area from 0x60 to 0x6f (DirectX timer, IRQ management,
  15. * power management etc.???). */
  16. #define AZF_IO_OFFS_CODEC_PLAYBACK 0x00
  17. #define AZF_IO_OFFS_CODEC_CAPTURE 0x20
  18. #define AZF_IO_OFFS_CODEC_I2S_OUT 0x40
  19. #define IDX_IO_CODEC_DMA_FLAGS 0x00 /* PU:0x0000 */
  20. /* able to reactivate output after output muting due to 8/16bit
  21. * output change, just like 0x0002.
  22. * 0x0001 is the only bit that's able to start the DMA counter */
  23. #define DMA_RESUME 0x0001 /* paused if cleared? */
  24. /* 0x0002 *temporarily* set during DMA stopping. hmm
  25. * both 0x0002 and 0x0004 set in playback setup. */
  26. /* able to reactivate output after output muting due to 8/16bit
  27. * output change, just like 0x0001. */
  28. #define DMA_RUN_SOMETHING1 0x0002 /* \ alternated (toggled) */
  29. /* 0x0004: NOT able to reactivate output */
  30. #define DMA_RUN_SOMETHING2 0x0004 /* / bits */
  31. #define SOMETHING_ALMOST_ALWAYS_SET 0x0008 /* ???; can be modified */
  32. #define DMA_EPILOGUE_SOMETHING 0x0010
  33. #define DMA_SOMETHING_ELSE 0x0020 /* ??? */
  34. #define SOMETHING_UNMODIFIABLE 0xffc0 /* unused? not modifiable */
  35. #define IDX_IO_CODEC_IRQTYPE 0x02 /* PU:0x0001 */
  36. /* write back to flags in case flags are set, in order to ACK IRQ in handler
  37. * (bit 1 of port 0x64 indicates interrupt for one of these three types)
  38. * sometimes in this case it just writes 0xffff to globally ACK all IRQs
  39. * settings written are not reflected when reading back, though.
  40. * seems to be IRQ, too (frequently used: port |= 0x07 !), but who knows? */
  41. #define IRQ_SOMETHING 0x0001 /* something & ACK */
  42. #define IRQ_FINISHED_DMABUF_1 0x0002 /* 1st dmabuf finished & ACK */
  43. #define IRQ_FINISHED_DMABUF_2 0x0004 /* 2nd dmabuf finished & ACK */
  44. #define IRQMASK_SOME_STATUS_1 0x0008 /* \ related bits */
  45. #define IRQMASK_SOME_STATUS_2 0x0010 /* / (checked together in loop) */
  46. #define IRQMASK_UNMODIFIABLE 0xffe0 /* unused? not modifiable */
  47. /* start address of 1st DMA transfer area, PU:0x00000000 */
  48. #define IDX_IO_CODEC_DMA_START_1 0x04
  49. /* start address of 2nd DMA transfer area, PU:0x00000000 */
  50. #define IDX_IO_CODEC_DMA_START_2 0x08
  51. /* both lengths of DMA transfer areas, PU:0x00000000
  52. length1: offset 0x0c, length2: offset 0x0e */
  53. #define IDX_IO_CODEC_DMA_LENGTHS 0x0c
  54. #define IDX_IO_CODEC_DMA_CURRPOS 0x10 /* current DMA position, PU:0x00000000 */
  55. /* offset within current DMA transfer area, PU:0x0000 */
  56. #define IDX_IO_CODEC_DMA_CURROFS 0x14
  57. #define IDX_IO_CODEC_SOUNDFORMAT 0x16 /* PU:0x0010 */
  58. /* all unspecified bits can't be modified */
  59. #define SOUNDFORMAT_FREQUENCY_MASK 0x000f
  60. #define SOUNDFORMAT_XTAL1 0x00
  61. #define SOUNDFORMAT_XTAL2 0x01
  62. /* all _SUSPECTED_ values are not used by Windows drivers, so we don't
  63. * have any hard facts, only rough measurements.
  64. * All we know is that the crystal used on the board has 24.576MHz,
  65. * like many soundcards (which results in the frequencies below when
  66. * using certain divider values selected by the values below) */
  67. #define SOUNDFORMAT_FREQ_SUSPECTED_4000 0x0c | SOUNDFORMAT_XTAL1
  68. #define SOUNDFORMAT_FREQ_SUSPECTED_4800 0x0a | SOUNDFORMAT_XTAL1
  69. #define SOUNDFORMAT_FREQ_5510 0x0c | SOUNDFORMAT_XTAL2
  70. #define SOUNDFORMAT_FREQ_6620 0x0a | SOUNDFORMAT_XTAL2
  71. #define SOUNDFORMAT_FREQ_8000 0x00 | SOUNDFORMAT_XTAL1 /* also 0x0e | SOUNDFORMAT_XTAL1? */
  72. #define SOUNDFORMAT_FREQ_9600 0x08 | SOUNDFORMAT_XTAL1
  73. #define SOUNDFORMAT_FREQ_11025 0x00 | SOUNDFORMAT_XTAL2 /* also 0x0e | SOUNDFORMAT_XTAL2? */
  74. #define SOUNDFORMAT_FREQ_SUSPECTED_13240 0x08 | SOUNDFORMAT_XTAL2 /* seems to be 6620 *2 */
  75. #define SOUNDFORMAT_FREQ_16000 0x02 | SOUNDFORMAT_XTAL1
  76. #define SOUNDFORMAT_FREQ_22050 0x02 | SOUNDFORMAT_XTAL2
  77. #define SOUNDFORMAT_FREQ_32000 0x04 | SOUNDFORMAT_XTAL1
  78. #define SOUNDFORMAT_FREQ_44100 0x04 | SOUNDFORMAT_XTAL2
  79. #define SOUNDFORMAT_FREQ_48000 0x06 | SOUNDFORMAT_XTAL1
  80. #define SOUNDFORMAT_FREQ_SUSPECTED_66200 0x06 | SOUNDFORMAT_XTAL2 /* 66200 (13240 * 5); 64000 may have been nicer :-\ */
  81. #define SOUNDFORMAT_FLAG_16BIT 0x0010
  82. #define SOUNDFORMAT_FLAG_2CHANNELS 0x0020
  83. /* define frequency helpers, for maximum value safety */
  84. enum azf_freq_t {
  85. #define AZF_FREQ(rate) AZF_FREQ_##rate = rate
  86. AZF_FREQ(4000),
  87. AZF_FREQ(4800),
  88. AZF_FREQ(5512),
  89. AZF_FREQ(6620),
  90. AZF_FREQ(8000),
  91. AZF_FREQ(9600),
  92. AZF_FREQ(11025),
  93. AZF_FREQ(13240),
  94. AZF_FREQ(16000),
  95. AZF_FREQ(22050),
  96. AZF_FREQ(32000),
  97. AZF_FREQ(44100),
  98. AZF_FREQ(48000),
  99. AZF_FREQ(66200),
  100. #undef AZF_FREQ
  101. };
  102. /** DirectX timer, main interrupt area (FIXME: and something else?) **/
  103. #define IDX_IO_TIMER_VALUE 0x60 /* found this timer area by pure luck :-) */
  104. /* timer countdown value; triggers IRQ when timer is finished */
  105. #define TIMER_VALUE_MASK 0x000fffffUL
  106. /* activate timer countdown */
  107. #define TIMER_COUNTDOWN_ENABLE 0x01000000UL
  108. /* trigger timer IRQ on zero transition */
  109. #define TIMER_IRQ_ENABLE 0x02000000UL
  110. /* being set in IRQ handler in case port 0x00 (hmm, not port 0x64!?!?)
  111. * had 0x0020 set upon IRQ handler */
  112. #define TIMER_IRQ_ACK 0x04000000UL
  113. #define IDX_IO_IRQSTATUS 0x64
  114. /* some IRQ bit in here might also be used to signal a power-management timer
  115. * timeout, to request shutdown of the chip (e.g. AD1815JS has such a thing).
  116. * OPL3 hardware contains several timers which confusingly in most cases
  117. * are NOT routed to an IRQ, but some designs (e.g. LM4560) DO support that,
  118. * so I wouldn't be surprised at all to discover that AZF3328
  119. * supports that thing as well... */
  120. #define IRQ_PLAYBACK 0x0001
  121. #define IRQ_RECORDING 0x0002
  122. #define IRQ_I2S_OUT 0x0004 /* this IS I2S, right!? (untested) */
  123. #define IRQ_GAMEPORT 0x0008 /* Interrupt of Digital(ly) Enhanced Game Port */
  124. #define IRQ_MPU401 0x0010
  125. #define IRQ_TIMER 0x0020 /* DirectX timer */
  126. #define IRQ_UNKNOWN2 0x0040 /* probably unused, or possibly OPL3 timer? */
  127. #define IRQ_UNKNOWN3 0x0080 /* probably unused, or possibly OPL3 timer? */
  128. #define IDX_IO_66H 0x66 /* writing 0xffff returns 0x0000 */
  129. /* this is set to e.g. 0x3ff or 0x300, and writable;
  130. * maybe some buffer limit, but I couldn't find out more, PU:0x00ff: */
  131. #define IDX_IO_SOME_VALUE 0x68
  132. #define IO_68_RANDOM_TOGGLE1 0x0100 /* toggles randomly */
  133. #define IO_68_RANDOM_TOGGLE2 0x0200 /* toggles randomly */
  134. /* umm, nope, behaviour of these bits changes depending on what we wrote
  135. * to 0x6b!!
  136. * And they change upon playback/stop, too:
  137. * Writing a value to 0x68 will display this exact value during playback,
  138. * too but when stopped it can fall back to a rather different
  139. * seemingly random value). Hmm, possibly this is a register which
  140. * has a remote shadow which needs proper device supply which only exists
  141. * in case playback is active? Or is this driver-induced?
  142. */
  143. /* this WORD can be set to have bits 0x0028 activated (FIXME: correct??);
  144. * actually inhibits PCM playback!!! maybe power management??: */
  145. #define IDX_IO_6AH 0x6A /* WRITE_ONLY! */
  146. /* bit 5: enabling this will activate permanent counting of bytes 2/3
  147. * at gameport I/O (0xb402/3) (equal values each) and cause
  148. * gameport legacy I/O at 0x0200 to be _DISABLED_!
  149. * Is this Digital Enhanced Game Port Enable??? Or maybe it's Testmode
  150. * for Enhanced Digital Gameport (see 4D Wave DX card): */
  151. #define IO_6A_SOMETHING1_GAMEPORT 0x0020
  152. /* bit 8; sure, this _pauses_ playback (later resumes at same spot!),
  153. * but what the heck is this really about??: */
  154. #define IO_6A_PAUSE_PLAYBACK_BIT8 0x0100
  155. /* bit 9; sure, this _pauses_ playback (later resumes at same spot!),
  156. * but what the heck is this really about??: */
  157. #define IO_6A_PAUSE_PLAYBACK_BIT9 0x0200
  158. /* BIT8 and BIT9 are _NOT_ able to affect OPL3 MIDI playback,
  159. * thus it suggests influence on PCM only!!
  160. * However OTOH there seems to be no bit anywhere around here
  161. * which is able to disable OPL3... */
  162. /* bit 10: enabling this actually changes values at legacy gameport
  163. * I/O address (0x200); is this enabling of the Digital Enhanced Game Port???
  164. * Or maybe this simply switches off the NE558 circuit, since enabling this
  165. * still lets us evaluate button states, but not axis states */
  166. #define IO_6A_SOMETHING2_GAMEPORT 0x0400
  167. /* writing 0x0300: causes quite some crackling during
  168. * PC activity such as switching windows (PCI traffic??
  169. * --> FIFO/timing settings???) */
  170. /* writing 0x0100 plus/or 0x0200 inhibits playback */
  171. /* since the Windows .INF file has Flag_Enable_JoyStick and
  172. * Flag_Enable_SB_DOS_Emulation directly together, it stands to reason
  173. * that some other bit in this same register might be responsible
  174. * for SB DOS Emulation activation (note that the file did NOT define
  175. * a switch for OPL3!) */
  176. #define IDX_IO_6CH 0x6C /* unknown; fully read-writable */
  177. #define IDX_IO_6EH 0x6E
  178. /* writing 0xffff returns 0x83fe (or 0x03fe only).
  179. * writing 0x83 (and only 0x83!!) to 0x6f will cause 0x6c to switch
  180. * from 0000 to ffff. */
  181. /* further I/O indices not saved/restored and not readable after writing,
  182. * so probably not used */
  183. /*** Gameport area port indices ***/
  184. /* (only 0x06 of 0x08 bytes saved/restored by Windows driver) */
  185. #define AZF_IO_SIZE_GAME 0x08
  186. #define AZF_IO_SIZE_GAME_PM 0x06
  187. enum {
  188. AZF_GAME_LEGACY_IO_PORT = 0x200
  189. };
  190. #define IDX_GAME_LEGACY_COMPATIBLE 0x00
  191. /* in some operation mode, writing anything to this port
  192. * triggers an interrupt:
  193. * yup, that's in case IDX_GAME_01H has one of the
  194. * axis measurement bits enabled
  195. * (and of course one needs to have GAME_HWCFG_IRQ_ENABLE, too) */
  196. #define IDX_GAME_AXES_CONFIG 0x01
  197. /* NOTE: layout of this register awfully similar (read: "identical??")
  198. * to AD1815JS.pdf (p.29) */
  199. /* enables axis 1 (X axis) measurement: */
  200. #define GAME_AXES_ENABLE_1 0x01
  201. /* enables axis 2 (Y axis) measurement: */
  202. #define GAME_AXES_ENABLE_2 0x02
  203. /* enables axis 3 (X axis) measurement: */
  204. #define GAME_AXES_ENABLE_3 0x04
  205. /* enables axis 4 (Y axis) measurement: */
  206. #define GAME_AXES_ENABLE_4 0x08
  207. /* selects the current axis to read the measured value of
  208. * (at IDX_GAME_AXIS_VALUE):
  209. * 00 = axis 1, 01 = axis 2, 10 = axis 3, 11 = axis 4: */
  210. #define GAME_AXES_READ_MASK 0x30
  211. /* enable to have the latch continuously accept ADC values
  212. * (and continuously cause interrupts in case interrupts are enabled);
  213. * AD1815JS.pdf says it's ~16ms interval there: */
  214. #define GAME_AXES_LATCH_ENABLE 0x40
  215. /* joystick data (measured axes) ready for reading: */
  216. #define GAME_AXES_SAMPLING_READY 0x80
  217. /* NOTE: other card specs (SiS960 and others!) state that the
  218. * game position latches should be frozen when reading and be freed
  219. * (== reset?) after reading!!!
  220. * Freezing most likely means disabling 0x40 (GAME_AXES_LATCH_ENABLE),
  221. * but how to free the value? */
  222. /* An internet search for "gameport latch ADC" should provide some insight
  223. * into how to program such a gameport system. */
  224. /* writing 0xf0 to 01H once reset both counters to 0, in some special mode!?
  225. * yup, in case 6AH 0x20 is not enabled
  226. * (and 0x40 is sufficient, 0xf0 is not needed) */
  227. #define IDX_GAME_AXIS_VALUE 0x02
  228. /* R: value of currently configured axis (word value!);
  229. * W: trigger axis measurement */
  230. #define IDX_GAME_HWCONFIG 0x04
  231. /* note: bits 4 to 7 are never set (== 0) when reading!
  232. * --> reserved bits? */
  233. /* enables IRQ notification upon axes measurement ready: */
  234. #define GAME_HWCFG_IRQ_ENABLE 0x01
  235. /* these bits choose a different frequency for the
  236. * internal ADC counter increment.
  237. * hmm, seems to be a combo of bits:
  238. * 00 --> standard frequency
  239. * 10 --> 1/2
  240. * 01 --> 1/20
  241. * 11 --> 1/200: */
  242. #define GAME_HWCFG_ADC_COUNTER_FREQ_MASK 0x06
  243. /* FIXME: these values might be reversed... */
  244. #define GAME_HWCFG_ADC_COUNTER_FREQ_STD 0
  245. #define GAME_HWCFG_ADC_COUNTER_FREQ_1_2 1
  246. #define GAME_HWCFG_ADC_COUNTER_FREQ_1_20 2
  247. #define GAME_HWCFG_ADC_COUNTER_FREQ_1_200 3
  248. /* enable gameport legacy I/O address (0x200)
  249. * I was unable to locate any configurability for a different address: */
  250. #define GAME_HWCFG_LEGACY_ADDRESS_ENABLE 0x08
  251. /*** MPU401 ***/
  252. #define AZF_IO_SIZE_MPU 0x04
  253. #define AZF_IO_SIZE_MPU_PM 0x04
  254. /*** OPL3 synth ***/
  255. /* (only 0x06 of 0x08 bytes saved/restored by Windows driver) */
  256. #define AZF_IO_SIZE_OPL3 0x08
  257. #define AZF_IO_SIZE_OPL3_PM 0x06
  258. /* hmm, given that a standard OPL3 has 4 registers only,
  259. * there might be some enhanced functionality lurking at the end
  260. * (especially since register 0x04 has a "non-empty" value 0xfe) */
  261. /*** mixer I/O area port indices ***/
  262. /* (only 0x22 of 0x40 bytes saved/restored by Windows driver)
  263. * UNFORTUNATELY azf3328 is NOT truly AC97 compliant: see main file intro */
  264. #define AZF_IO_SIZE_MIXER 0x40
  265. #define AZF_IO_SIZE_MIXER_PM 0x22
  266. #define MIXER_VOLUME_RIGHT_MASK 0x001f
  267. #define MIXER_VOLUME_LEFT_MASK 0x1f00
  268. #define MIXER_MUTE_MASK 0x8000
  269. #define IDX_MIXER_RESET 0x00 /* does NOT seem to have AC97 ID bits */
  270. #define IDX_MIXER_PLAY_MASTER 0x02
  271. #define IDX_MIXER_MODEMOUT 0x04
  272. #define IDX_MIXER_BASSTREBLE 0x06
  273. #define MIXER_BASSTREBLE_TREBLE_VOLUME_MASK 0x000e
  274. #define MIXER_BASSTREBLE_BASS_VOLUME_MASK 0x0e00
  275. #define IDX_MIXER_PCBEEP 0x08
  276. #define IDX_MIXER_MODEMIN 0x0a
  277. #define IDX_MIXER_MIC 0x0c
  278. #define MIXER_MIC_MICGAIN_20DB_ENHANCEMENT_MASK 0x0040
  279. #define IDX_MIXER_LINEIN 0x0e
  280. #define IDX_MIXER_CDAUDIO 0x10
  281. #define IDX_MIXER_VIDEO 0x12
  282. #define IDX_MIXER_AUX 0x14
  283. #define IDX_MIXER_WAVEOUT 0x16
  284. #define IDX_MIXER_FMSYNTH 0x18
  285. #define IDX_MIXER_REC_SELECT 0x1a
  286. #define MIXER_REC_SELECT_MIC 0x00
  287. #define MIXER_REC_SELECT_CD 0x01
  288. #define MIXER_REC_SELECT_VIDEO 0x02
  289. #define MIXER_REC_SELECT_AUX 0x03
  290. #define MIXER_REC_SELECT_LINEIN 0x04
  291. #define MIXER_REC_SELECT_MIXSTEREO 0x05
  292. #define MIXER_REC_SELECT_MIXMONO 0x06
  293. #define MIXER_REC_SELECT_MONOIN 0x07
  294. #define IDX_MIXER_REC_VOLUME 0x1c
  295. #define IDX_MIXER_ADVCTL1 0x1e
  296. /* unlisted bits are unmodifiable */
  297. #define MIXER_ADVCTL1_3DWIDTH_MASK 0x000e
  298. #define MIXER_ADVCTL1_HIFI3D_MASK 0x0300 /* yup, this is missing the high bit that official AC97 contains, plus it doesn't have linear bit value range behaviour but instead acts weirdly (possibly we're dealing with two *different* 3D settings here??) */
  299. #define IDX_MIXER_ADVCTL2 0x20 /* subset of AC97_GENERAL_PURPOSE reg! */
  300. /* unlisted bits are unmodifiable */
  301. #define MIXER_ADVCTL2_LPBK 0x0080 /* Loopback mode -- Win driver: "WaveOut3DBypass"? mutes WaveOut at LineOut */
  302. #define MIXER_ADVCTL2_MS 0x0100 /* Mic Select 0=Mic1, 1=Mic2 -- Win driver: "ModemOutSelect"?? */
  303. #define MIXER_ADVCTL2_MIX 0x0200 /* Mono output select 0=Mix, 1=Mic; Win driver: "MonoSelectSource"?? */
  304. #define MIXER_ADVCTL2_3D 0x2000 /* 3D Enhancement 1=on */
  305. #define MIXER_ADVCTL2_POP 0x8000 /* Pcm Out Path, 0=pre 3D, 1=post 3D */
  306. #define IDX_MIXER_SOMETHING30H 0x30 /* used, but unknown??? */
  307. /* driver internal flags */
  308. #define SET_CHAN_LEFT 1
  309. #define SET_CHAN_RIGHT 2
  310. /* helper macro to align I/O port ranges to 32bit I/O width */
  311. #define AZF_ALIGN(x) (((x) + 3) & (~3))
  312. #endif /* __SOUND_AZT3328_H */