azt3328.c 81 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /* azt3328.c - driver for Aztech AZF3328 based soundcards (e.g. PCI168).
  3. * Copyright (C) 2002, 2005 - 2011 by Andreas Mohr <andi AT lisas.de>
  4. *
  5. * Framework borrowed from Bart Hartgers's als4000.c.
  6. * Driver developed on PCI168 AP(W) version (PCI rev. 10, subsystem ID 1801),
  7. * found in a Fujitsu-Siemens PC ("Cordant", aluminum case).
  8. * Other versions are:
  9. * PCI168 A(W), sub ID 1800
  10. * PCI168 A/AP, sub ID 8000
  11. * Please give me feedback in case you try my driver with one of these!!
  12. *
  13. * Keywords: Windows XP Vista 168nt4-125.zip 168win95-125.zip PCI 168 download
  14. * (XP/Vista do not support this card at all but every Linux distribution
  15. * has very good support out of the box;
  16. * just to make sure that the right people hit this and get to know that,
  17. * despite the high level of Internet ignorance - as usual :-P -
  18. * about very good support for this card - on Linux!)
  19. *
  20. * NOTES
  21. * Since Aztech does not provide any chipset documentation,
  22. * even on repeated request to various addresses,
  23. * and the answer that was finally given was negative
  24. * (and I was stupid enough to manage to get hold of a PCI168 soundcard
  25. * in the first place >:-P}),
  26. * I was forced to base this driver on reverse engineering
  27. * (3 weeks' worth of evenings filled with driver work).
  28. * (and no, I did NOT go the easy way: to pick up a SB PCI128 for 9 Euros)
  29. *
  30. * It is quite likely that the AZF3328 chip is the PCI cousin of the
  31. * AZF3318 ("azt1020 pnp", "MM Pro 16") ISA chip, given very similar specs.
  32. *
  33. * The AZF3328 chip (note: AZF3328, *not* AZT3328, that's just the driver name
  34. * for compatibility reasons) from Azfin (joint-venture of Aztech and Fincitec,
  35. * Fincitec acquired by National Semiconductor in 2002, together with the
  36. * Fincitec-related company ARSmikro) has the following features:
  37. *
  38. * - compatibility & compliance:
  39. * - Microsoft PC 97 ("PC 97 Hardware Design Guide",
  40. * http://www.microsoft.com/whdc/archive/pcguides.mspx)
  41. * - Microsoft PC 98 Baseline Audio
  42. * - MPU401 UART
  43. * - Sound Blaster Emulation (DOS Box)
  44. * - builtin AC97 conformant codec (SNR over 80dB)
  45. * Note that "conformant" != "compliant"!! this chip's mixer register layout
  46. * *differs* from the standard AC97 layout:
  47. * they chose to not implement the headphone register (which is not a
  48. * problem since it's merely optional), yet when doing this, they committed
  49. * the grave sin of letting other registers follow immediately instead of
  50. * keeping a headphone dummy register, thereby shifting the mixer register
  51. * addresses illegally. So far unfortunately it looks like the very flexible
  52. * ALSA AC97 support is still not enough to easily compensate for such a
  53. * grave layout violation despite all tweaks and quirks mechanisms it offers.
  54. * Well, not quite: now ac97 layer is much improved (bus-specific ops!),
  55. * thus I was able to implement support - it's actually working quite well.
  56. * An interesting item might be Aztech AMR 2800-W, since it's an AC97
  57. * modem card which might reveal the Aztech-specific codec ID which
  58. * we might want to pretend, too. Dito PCI168's brother, PCI368,
  59. * where the advertising datasheet says it's AC97-based and has a
  60. * Digital Enhanced Game Port.
  61. * - builtin genuine OPL3 - verified to work fine, 20080506
  62. * - full duplex 16bit playback/record at independent sampling rate
  63. * - MPU401 (+ legacy address support, claimed by one official spec sheet)
  64. * FIXME: how to enable legacy addr??
  65. * - game port (legacy address support)
  66. * - builtin DirectInput support, helps reduce CPU overhead (interrupt-driven
  67. * features supported). - See common term "Digital Enhanced Game Port"...
  68. * (probably DirectInput 3.0 spec - confirm)
  69. * - builtin 3D enhancement (said to be YAMAHA Ymersion)
  70. * - built-in General DirectX timer having a 20 bits counter
  71. * with 1us resolution (see below!)
  72. * - I2S serial output port for external DAC
  73. * [FIXME: 3.3V or 5V level? maximum rate is 66.2kHz right?]
  74. * - supports 33MHz PCI spec 2.1, PCI power management 1.0, compliant with ACPI
  75. * - supports hardware volume control
  76. * - single chip low cost solution (128 pin QFP)
  77. * - supports programmable Sub-vendor and Sub-system ID [24C02 SEEPROM chip]
  78. * required for Microsoft's logo compliance (FIXME: where?)
  79. * At least the Trident 4D Wave DX has one bit somewhere
  80. * to enable writes to PCI subsystem VID registers, that should be it.
  81. * This might easily be in extended PCI reg space, since PCI168 also has
  82. * some custom data starting at 0x80. What kind of config settings
  83. * are located in our extended PCI space anyway??
  84. * - PCI168 AP(W) card: power amplifier with 4 Watts/channel at 4 Ohms
  85. * [TDA1517P chip]
  86. *
  87. * Note that this driver now is actually *better* than the Windows driver,
  88. * since it additionally supports the card's 1MHz DirectX timer - just try
  89. * the following snd-seq module parameters etc.:
  90. * - options snd-seq seq_default_timer_class=2 seq_default_timer_sclass=0
  91. * seq_default_timer_card=0 seq_client_load=1 seq_default_timer_device=0
  92. * seq_default_timer_subdevice=0 seq_default_timer_resolution=1000000
  93. * - "timidity -iAv -B2,8 -Os -EFreverb=0"
  94. * - "pmidi -p 128:0 jazz.mid"
  95. *
  96. * OPL3 hardware playback testing, try something like:
  97. * cat /proc/asound/hwdep
  98. * and
  99. * aconnect -o
  100. * Then use
  101. * sbiload -Dhw:x,y --opl3 /usr/share/sounds/opl3/std.o3 ......./drums.o3
  102. * where x,y is the xx-yy number as given in hwdep.
  103. * Then try
  104. * pmidi -p a:b jazz.mid
  105. * where a:b is the client number plus 0 usually, as given by aconnect above.
  106. * Oh, and make sure to unmute the FM mixer control (doh!)
  107. * NOTE: power use during OPL3 playback is _VERY_ high (70W --> 90W!)
  108. * despite no CPU activity, possibly due to hindering ACPI idling somehow.
  109. * Shouldn't be a problem of the AZF3328 chip itself, I'd hope.
  110. * Higher PCM / FM mixer levels seem to conflict (causes crackling),
  111. * at least sometimes. Maybe even use with hardware sequencer timer above :)
  112. * adplay/adplug-utils might soon offer hardware-based OPL3 playback, too.
  113. *
  114. * Certain PCI versions of this card are susceptible to DMA traffic underruns
  115. * in some systems (resulting in sound crackling/clicking/popping),
  116. * probably because they don't have a DMA FIFO buffer or so.
  117. * Overview (PCI ID/PCI subID/PCI rev.):
  118. * - no DMA crackling on SiS735: 0x50DC/0x1801/16
  119. * - unknown performance: 0x50DC/0x1801/10
  120. * (well, it's not bad on an Athlon 1800 with now very optimized IRQ handler)
  121. *
  122. * Crackling happens with VIA chipsets or, in my case, an SiS735, which is
  123. * supposed to be very fast and supposed to get rid of crackling much
  124. * better than a VIA, yet ironically I still get crackling, like many other
  125. * people with the same chipset.
  126. * Possible remedies:
  127. * - use speaker (amplifier) output instead of headphone output
  128. * (in case crackling is due to overloaded output clipping)
  129. * - plug card into a different PCI slot, preferably one that isn't shared
  130. * too much (this helps a lot, but not completely!)
  131. * - get rid of PCI VGA card, use AGP instead
  132. * - upgrade or downgrade BIOS
  133. * - fiddle with PCI latency settings (setpci -v -s BUSID latency_timer=XX)
  134. * Not too helpful.
  135. * - Disable ACPI/power management/"Auto Detect RAM/PCI Clk" in BIOS
  136. *
  137. * BUGS
  138. * - full-duplex might *still* be problematic, however a recent test was fine
  139. * - (non-bug) "Bass/Treble or 3D settings don't work" - they do get evaluated
  140. * if you set PCM output switch to "pre 3D" instead of "post 3D".
  141. * If this can't be set, then get a mixer application that Isn't Stupid (tm)
  142. * (e.g. kmix, gamix) - unfortunately several are!!
  143. * - locking is not entirely clean, especially the audio stream activity
  144. * ints --> may be racy
  145. * - an _unconnected_ secondary joystick at the gameport will be reported
  146. * to be "active" (floating values, not precisely -1) due to the way we need
  147. * to read the Digital Enhanced Game Port. Not sure whether it is fixable.
  148. *
  149. * TODO
  150. * - use PCI_VDEVICE
  151. * - verify driver status on x86_64
  152. * - test multi-card driver operation
  153. * - (ab)use 1MHz DirectX timer as kernel clocksource
  154. * - test MPU401 MIDI playback etc.
  155. * - add more power micro-management (disable various units of the card
  156. * as long as they're unused, to improve audio quality and save power).
  157. * However this requires more I/O ports which I haven't figured out yet
  158. * and which thus might not even exist...
  159. * The standard suspend/resume functionality could probably make use of
  160. * some improvement, too...
  161. * - figure out what all unknown port bits are responsible for
  162. * - figure out some cleverly evil scheme to possibly make ALSA AC97 code
  163. * fully accept our quite incompatible ""AC97"" mixer and thus save some
  164. * code (but I'm not too optimistic that doing this is possible at all)
  165. * - use MMIO (memory-mapped I/O)? Slightly faster access, e.g. for gameport.
  166. */
  167. #include <linux/io.h>
  168. #include <linux/init.h>
  169. #include <linux/bug.h> /* WARN_ONCE */
  170. #include <linux/pci.h>
  171. #include <linux/delay.h>
  172. #include <linux/slab.h>
  173. #include <linux/gameport.h>
  174. #include <linux/module.h>
  175. #include <linux/dma-mapping.h>
  176. #include <sound/core.h>
  177. #include <sound/control.h>
  178. #include <sound/pcm.h>
  179. #include <sound/rawmidi.h>
  180. #include <sound/mpu401.h>
  181. #include <sound/opl3.h>
  182. #include <sound/initval.h>
  183. /*
  184. * Config switch, to use ALSA's AC97 layer instead of old custom mixer crap.
  185. * If the AC97 compatibility parts we needed to implement locally turn out
  186. * to work nicely, then remove the old implementation eventually.
  187. */
  188. #define AZF_USE_AC97_LAYER 1
  189. #ifdef AZF_USE_AC97_LAYER
  190. #include <sound/ac97_codec.h>
  191. #endif
  192. #include "azt3328.h"
  193. MODULE_AUTHOR("Andreas Mohr <andi AT lisas.de>");
  194. MODULE_DESCRIPTION("Aztech AZF3328 (PCI168)");
  195. MODULE_LICENSE("GPL");
  196. MODULE_SUPPORTED_DEVICE("{{Aztech,AZF3328}}");
  197. #if IS_REACHABLE(CONFIG_GAMEPORT)
  198. #define SUPPORT_GAMEPORT 1
  199. #endif
  200. /* === Debug settings ===
  201. Further diagnostic functionality than the settings below
  202. does not need to be provided, since one can easily write a POSIX shell script
  203. to dump the card's I/O ports (those listed in lspci -v -v):
  204. dump()
  205. {
  206. local descr=$1; local addr=$2; local count=$3
  207. echo "${descr}: ${count} @ ${addr}:"
  208. dd if=/dev/port skip=`printf %d ${addr}` count=${count} bs=1 \
  209. 2>/dev/null| hexdump -C
  210. }
  211. and then use something like
  212. "dump joy200 0x200 8", "dump mpu388 0x388 4", "dump joy 0xb400 8",
  213. "dump codec00 0xa800 32", "dump mixer 0xb800 64", "dump synth 0xbc00 8",
  214. possibly within a "while true; do ... sleep 1; done" loop.
  215. Tweaking ports could be done using
  216. VALSTRING="`printf "%02x" $value`"
  217. printf "\x""$VALSTRING"|dd of=/dev/port seek=`printf %d ${addr}` bs=1 \
  218. 2>/dev/null
  219. */
  220. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  221. module_param_array(index, int, NULL, 0444);
  222. MODULE_PARM_DESC(index, "Index value for AZF3328 soundcard.");
  223. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  224. module_param_array(id, charp, NULL, 0444);
  225. MODULE_PARM_DESC(id, "ID string for AZF3328 soundcard.");
  226. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  227. module_param_array(enable, bool, NULL, 0444);
  228. MODULE_PARM_DESC(enable, "Enable AZF3328 soundcard.");
  229. static int seqtimer_scaling = 128;
  230. module_param(seqtimer_scaling, int, 0444);
  231. MODULE_PARM_DESC(seqtimer_scaling, "Set 1024000Hz sequencer timer scale factor (lockup danger!). Default 128.");
  232. enum snd_azf3328_codec_type {
  233. /* warning: fixed indices (also used for bitmask checks!) */
  234. AZF_CODEC_PLAYBACK = 0,
  235. AZF_CODEC_CAPTURE = 1,
  236. AZF_CODEC_I2S_OUT = 2,
  237. };
  238. struct snd_azf3328_codec_data {
  239. unsigned long io_base; /* keep first! (avoid offset calc) */
  240. unsigned int dma_base; /* helper to avoid an indirection in hotpath */
  241. spinlock_t *lock; /* TODO: convert to our own per-codec lock member */
  242. struct snd_pcm_substream *substream;
  243. bool running;
  244. enum snd_azf3328_codec_type type;
  245. const char *name;
  246. };
  247. struct snd_azf3328 {
  248. /* often-used fields towards beginning, then grouped */
  249. unsigned long ctrl_io; /* usually 0xb000, size 128 */
  250. unsigned long game_io; /* usually 0xb400, size 8 */
  251. unsigned long mpu_io; /* usually 0xb800, size 4 */
  252. unsigned long opl3_io; /* usually 0xbc00, size 8 */
  253. unsigned long mixer_io; /* usually 0xc000, size 64 */
  254. spinlock_t reg_lock;
  255. struct snd_timer *timer;
  256. struct snd_pcm *pcm[3];
  257. /* playback, recording and I2S out codecs */
  258. struct snd_azf3328_codec_data codecs[3];
  259. #ifdef AZF_USE_AC97_LAYER
  260. struct snd_ac97 *ac97;
  261. #endif
  262. struct snd_card *card;
  263. struct snd_rawmidi *rmidi;
  264. #ifdef SUPPORT_GAMEPORT
  265. struct gameport *gameport;
  266. u16 axes[4];
  267. #endif
  268. struct pci_dev *pci;
  269. int irq;
  270. /* register 0x6a is write-only, thus need to remember setting.
  271. * If we need to add more registers here, then we might try to fold this
  272. * into some transparent combined shadow register handling with
  273. * CONFIG_PM register storage below, but that's slightly difficult. */
  274. u16 shadow_reg_ctrl_6AH;
  275. #ifdef CONFIG_PM_SLEEP
  276. /* register value containers for power management
  277. * Note: not always full I/O range preserved (similar to Win driver!) */
  278. u32 saved_regs_ctrl[AZF_ALIGN(AZF_IO_SIZE_CTRL_PM) / 4];
  279. u32 saved_regs_game[AZF_ALIGN(AZF_IO_SIZE_GAME_PM) / 4];
  280. u32 saved_regs_mpu[AZF_ALIGN(AZF_IO_SIZE_MPU_PM) / 4];
  281. u32 saved_regs_opl3[AZF_ALIGN(AZF_IO_SIZE_OPL3_PM) / 4];
  282. u32 saved_regs_mixer[AZF_ALIGN(AZF_IO_SIZE_MIXER_PM) / 4];
  283. #endif
  284. };
  285. static const struct pci_device_id snd_azf3328_ids[] = {
  286. { 0x122D, 0x50DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* PCI168/3328 */
  287. { 0x122D, 0x80DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 3328 */
  288. { 0, }
  289. };
  290. MODULE_DEVICE_TABLE(pci, snd_azf3328_ids);
  291. static int
  292. snd_azf3328_io_reg_setb(unsigned reg, u8 mask, bool do_set)
  293. {
  294. /* Well, strictly spoken, the inb/outb sequence isn't atomic
  295. and would need locking. However we currently don't care
  296. since it potentially complicates matters. */
  297. u8 prev = inb(reg), new;
  298. new = (do_set) ? (prev|mask) : (prev & ~mask);
  299. /* we need to always write the new value no matter whether it differs
  300. * or not, since some register bits don't indicate their setting */
  301. outb(new, reg);
  302. if (new != prev)
  303. return 1;
  304. return 0;
  305. }
  306. static inline void
  307. snd_azf3328_codec_outb(const struct snd_azf3328_codec_data *codec,
  308. unsigned reg,
  309. u8 value
  310. )
  311. {
  312. outb(value, codec->io_base + reg);
  313. }
  314. static inline u8
  315. snd_azf3328_codec_inb(const struct snd_azf3328_codec_data *codec, unsigned reg)
  316. {
  317. return inb(codec->io_base + reg);
  318. }
  319. static inline void
  320. snd_azf3328_codec_outw(const struct snd_azf3328_codec_data *codec,
  321. unsigned reg,
  322. u16 value
  323. )
  324. {
  325. outw(value, codec->io_base + reg);
  326. }
  327. static inline u16
  328. snd_azf3328_codec_inw(const struct snd_azf3328_codec_data *codec, unsigned reg)
  329. {
  330. return inw(codec->io_base + reg);
  331. }
  332. static inline void
  333. snd_azf3328_codec_outl(const struct snd_azf3328_codec_data *codec,
  334. unsigned reg,
  335. u32 value
  336. )
  337. {
  338. outl(value, codec->io_base + reg);
  339. }
  340. static inline void
  341. snd_azf3328_codec_outl_multi(const struct snd_azf3328_codec_data *codec,
  342. unsigned reg, const void *buffer, int count
  343. )
  344. {
  345. unsigned long addr = codec->io_base + reg;
  346. if (count) {
  347. const u32 *buf = buffer;
  348. do {
  349. outl(*buf++, addr);
  350. addr += 4;
  351. } while (--count);
  352. }
  353. }
  354. static inline u32
  355. snd_azf3328_codec_inl(const struct snd_azf3328_codec_data *codec, unsigned reg)
  356. {
  357. return inl(codec->io_base + reg);
  358. }
  359. static inline void
  360. snd_azf3328_ctrl_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value)
  361. {
  362. outb(value, chip->ctrl_io + reg);
  363. }
  364. static inline u8
  365. snd_azf3328_ctrl_inb(const struct snd_azf3328 *chip, unsigned reg)
  366. {
  367. return inb(chip->ctrl_io + reg);
  368. }
  369. static inline u16
  370. snd_azf3328_ctrl_inw(const struct snd_azf3328 *chip, unsigned reg)
  371. {
  372. return inw(chip->ctrl_io + reg);
  373. }
  374. static inline void
  375. snd_azf3328_ctrl_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
  376. {
  377. outw(value, chip->ctrl_io + reg);
  378. }
  379. static inline void
  380. snd_azf3328_ctrl_outl(const struct snd_azf3328 *chip, unsigned reg, u32 value)
  381. {
  382. outl(value, chip->ctrl_io + reg);
  383. }
  384. static inline void
  385. snd_azf3328_game_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value)
  386. {
  387. outb(value, chip->game_io + reg);
  388. }
  389. static inline void
  390. snd_azf3328_game_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
  391. {
  392. outw(value, chip->game_io + reg);
  393. }
  394. static inline u8
  395. snd_azf3328_game_inb(const struct snd_azf3328 *chip, unsigned reg)
  396. {
  397. return inb(chip->game_io + reg);
  398. }
  399. static inline u16
  400. snd_azf3328_game_inw(const struct snd_azf3328 *chip, unsigned reg)
  401. {
  402. return inw(chip->game_io + reg);
  403. }
  404. static inline void
  405. snd_azf3328_mixer_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
  406. {
  407. outw(value, chip->mixer_io + reg);
  408. }
  409. static inline u16
  410. snd_azf3328_mixer_inw(const struct snd_azf3328 *chip, unsigned reg)
  411. {
  412. return inw(chip->mixer_io + reg);
  413. }
  414. #define AZF_MUTE_BIT 0x80
  415. static bool
  416. snd_azf3328_mixer_mute_control(const struct snd_azf3328 *chip,
  417. unsigned reg, bool do_mute
  418. )
  419. {
  420. unsigned long portbase = chip->mixer_io + reg + 1;
  421. bool updated;
  422. /* the mute bit is on the *second* (i.e. right) register of a
  423. * left/right channel setting */
  424. updated = snd_azf3328_io_reg_setb(portbase, AZF_MUTE_BIT, do_mute);
  425. /* indicate whether it was muted before */
  426. return (do_mute) ? !updated : updated;
  427. }
  428. static inline bool
  429. snd_azf3328_mixer_mute_control_master(const struct snd_azf3328 *chip,
  430. bool do_mute
  431. )
  432. {
  433. return snd_azf3328_mixer_mute_control(
  434. chip,
  435. IDX_MIXER_PLAY_MASTER,
  436. do_mute
  437. );
  438. }
  439. static inline bool
  440. snd_azf3328_mixer_mute_control_pcm(const struct snd_azf3328 *chip,
  441. bool do_mute
  442. )
  443. {
  444. return snd_azf3328_mixer_mute_control(
  445. chip,
  446. IDX_MIXER_WAVEOUT,
  447. do_mute
  448. );
  449. }
  450. static inline void
  451. snd_azf3328_mixer_reset(const struct snd_azf3328 *chip)
  452. {
  453. /* reset (close) mixer:
  454. * first mute master volume, then reset
  455. */
  456. snd_azf3328_mixer_mute_control_master(chip, 1);
  457. snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
  458. }
  459. #ifdef AZF_USE_AC97_LAYER
  460. static inline void
  461. snd_azf3328_mixer_ac97_map_unsupported(const struct snd_azf3328 *chip,
  462. unsigned short reg, const char *mode)
  463. {
  464. /* need to add some more or less clever emulation? */
  465. dev_warn(chip->card->dev,
  466. "missing %s emulation for AC97 register 0x%02x!\n",
  467. mode, reg);
  468. }
  469. /*
  470. * Need to have _special_ AC97 mixer hardware register index mapper,
  471. * to compensate for the issue of a rather AC97-incompatible hardware layout.
  472. */
  473. #define AZF_REG_MASK 0x3f
  474. #define AZF_AC97_REG_UNSUPPORTED 0x8000
  475. #define AZF_AC97_REG_REAL_IO_READ 0x4000
  476. #define AZF_AC97_REG_REAL_IO_WRITE 0x2000
  477. #define AZF_AC97_REG_REAL_IO_RW \
  478. (AZF_AC97_REG_REAL_IO_READ | AZF_AC97_REG_REAL_IO_WRITE)
  479. #define AZF_AC97_REG_EMU_IO_READ 0x0400
  480. #define AZF_AC97_REG_EMU_IO_WRITE 0x0200
  481. #define AZF_AC97_REG_EMU_IO_RW \
  482. (AZF_AC97_REG_EMU_IO_READ | AZF_AC97_REG_EMU_IO_WRITE)
  483. static unsigned short
  484. snd_azf3328_mixer_ac97_map_reg_idx(unsigned short reg)
  485. {
  486. static const struct {
  487. unsigned short azf_reg;
  488. } azf_reg_mapper[] = {
  489. /* Especially when taking into consideration
  490. * mono/stereo-based sequence of azf vs. AC97 control series,
  491. * it's quite obvious that azf simply got rid
  492. * of the AC97_HEADPHONE control at its intended offset,
  493. * thus shifted _all_ controls by one,
  494. * and _then_ simply added it as an FMSYNTH control at the end,
  495. * to make up for the offset.
  496. * This means we'll have to translate indices here as
  497. * needed and then do some tiny AC97 patch action
  498. * (snd_ac97_rename_vol_ctl() etc.) - that's it.
  499. */
  500. { /* AC97_RESET */ IDX_MIXER_RESET
  501. | AZF_AC97_REG_REAL_IO_WRITE
  502. | AZF_AC97_REG_EMU_IO_READ },
  503. { /* AC97_MASTER */ IDX_MIXER_PLAY_MASTER },
  504. /* note large shift: AC97_HEADPHONE to IDX_MIXER_FMSYNTH! */
  505. { /* AC97_HEADPHONE */ IDX_MIXER_FMSYNTH },
  506. { /* AC97_MASTER_MONO */ IDX_MIXER_MODEMOUT },
  507. { /* AC97_MASTER_TONE */ IDX_MIXER_BASSTREBLE },
  508. { /* AC97_PC_BEEP */ IDX_MIXER_PCBEEP },
  509. { /* AC97_PHONE */ IDX_MIXER_MODEMIN },
  510. { /* AC97_MIC */ IDX_MIXER_MIC },
  511. { /* AC97_LINE */ IDX_MIXER_LINEIN },
  512. { /* AC97_CD */ IDX_MIXER_CDAUDIO },
  513. { /* AC97_VIDEO */ IDX_MIXER_VIDEO },
  514. { /* AC97_AUX */ IDX_MIXER_AUX },
  515. { /* AC97_PCM */ IDX_MIXER_WAVEOUT },
  516. { /* AC97_REC_SEL */ IDX_MIXER_REC_SELECT },
  517. { /* AC97_REC_GAIN */ IDX_MIXER_REC_VOLUME },
  518. { /* AC97_REC_GAIN_MIC */ AZF_AC97_REG_EMU_IO_RW },
  519. { /* AC97_GENERAL_PURPOSE */ IDX_MIXER_ADVCTL2 },
  520. { /* AC97_3D_CONTROL */ IDX_MIXER_ADVCTL1 },
  521. };
  522. unsigned short reg_azf = AZF_AC97_REG_UNSUPPORTED;
  523. /* azf3328 supports the low-numbered and low-spec:ed range
  524. of AC97 regs only */
  525. if (reg <= AC97_3D_CONTROL) {
  526. unsigned short reg_idx = reg / 2;
  527. reg_azf = azf_reg_mapper[reg_idx].azf_reg;
  528. /* a translation-only entry means it's real read/write: */
  529. if (!(reg_azf & ~AZF_REG_MASK))
  530. reg_azf |= AZF_AC97_REG_REAL_IO_RW;
  531. } else {
  532. switch (reg) {
  533. case AC97_POWERDOWN:
  534. reg_azf = AZF_AC97_REG_EMU_IO_RW;
  535. break;
  536. case AC97_EXTENDED_ID:
  537. reg_azf = AZF_AC97_REG_EMU_IO_READ;
  538. break;
  539. case AC97_EXTENDED_STATUS:
  540. /* I don't know what the h*ll AC97 layer
  541. * would consult this _extended_ register for
  542. * given a base-AC97-advertised card,
  543. * but let's just emulate it anyway :-P
  544. */
  545. reg_azf = AZF_AC97_REG_EMU_IO_RW;
  546. break;
  547. case AC97_VENDOR_ID1:
  548. case AC97_VENDOR_ID2:
  549. reg_azf = AZF_AC97_REG_EMU_IO_READ;
  550. break;
  551. }
  552. }
  553. return reg_azf;
  554. }
  555. static const unsigned short
  556. azf_emulated_ac97_caps =
  557. AC97_BC_DEDICATED_MIC |
  558. AC97_BC_BASS_TREBLE |
  559. /* Headphone is an FM Synth control here */
  560. AC97_BC_HEADPHONE |
  561. /* no AC97_BC_LOUDNESS! */
  562. /* mask 0x7c00 is
  563. vendor-specific 3D enhancement
  564. vendor indicator.
  565. Since there actually _is_ an
  566. entry for Aztech Labs
  567. (13), make damn sure
  568. to indicate it. */
  569. (13 << 10);
  570. static const unsigned short
  571. azf_emulated_ac97_powerdown =
  572. /* pretend everything to be active */
  573. AC97_PD_ADC_STATUS |
  574. AC97_PD_DAC_STATUS |
  575. AC97_PD_MIXER_STATUS |
  576. AC97_PD_VREF_STATUS;
  577. /*
  578. * Emulated, _inofficial_ vendor ID
  579. * (there might be some devices such as the MR 2800-W
  580. * which could reveal the real Aztech AC97 ID).
  581. * We choose to use "AZT" prefix, and then use 1 to indicate PCI168
  582. * (better don't use 0x68 since there's a PCI368 as well).
  583. */
  584. static const unsigned int
  585. azf_emulated_ac97_vendor_id = 0x415a5401;
  586. static unsigned short
  587. snd_azf3328_mixer_ac97_read(struct snd_ac97 *ac97, unsigned short reg_ac97)
  588. {
  589. const struct snd_azf3328 *chip = ac97->private_data;
  590. unsigned short reg_azf = snd_azf3328_mixer_ac97_map_reg_idx(reg_ac97);
  591. unsigned short reg_val = 0;
  592. bool unsupported = false;
  593. dev_dbg(chip->card->dev, "snd_azf3328_mixer_ac97_read reg_ac97 %u\n",
  594. reg_ac97);
  595. if (reg_azf & AZF_AC97_REG_UNSUPPORTED)
  596. unsupported = true;
  597. else {
  598. if (reg_azf & AZF_AC97_REG_REAL_IO_READ)
  599. reg_val = snd_azf3328_mixer_inw(chip,
  600. reg_azf & AZF_REG_MASK);
  601. else {
  602. /*
  603. * Proceed with dummy I/O read,
  604. * to ensure compatible timing where this may matter.
  605. * (ALSA AC97 layer usually doesn't call I/O functions
  606. * due to intelligent I/O caching anyway)
  607. * Choose a mixer register that's thoroughly unrelated
  608. * to common audio (try to minimize distortion).
  609. */
  610. snd_azf3328_mixer_inw(chip, IDX_MIXER_SOMETHING30H);
  611. }
  612. if (reg_azf & AZF_AC97_REG_EMU_IO_READ) {
  613. switch (reg_ac97) {
  614. case AC97_RESET:
  615. reg_val |= azf_emulated_ac97_caps;
  616. break;
  617. case AC97_POWERDOWN:
  618. reg_val |= azf_emulated_ac97_powerdown;
  619. break;
  620. case AC97_EXTENDED_ID:
  621. case AC97_EXTENDED_STATUS:
  622. /* AFAICS we simply can't support anything: */
  623. reg_val |= 0;
  624. break;
  625. case AC97_VENDOR_ID1:
  626. reg_val = azf_emulated_ac97_vendor_id >> 16;
  627. break;
  628. case AC97_VENDOR_ID2:
  629. reg_val = azf_emulated_ac97_vendor_id & 0xffff;
  630. break;
  631. default:
  632. unsupported = true;
  633. break;
  634. }
  635. }
  636. }
  637. if (unsupported)
  638. snd_azf3328_mixer_ac97_map_unsupported(chip, reg_ac97, "read");
  639. return reg_val;
  640. }
  641. static void
  642. snd_azf3328_mixer_ac97_write(struct snd_ac97 *ac97,
  643. unsigned short reg_ac97, unsigned short val)
  644. {
  645. const struct snd_azf3328 *chip = ac97->private_data;
  646. unsigned short reg_azf = snd_azf3328_mixer_ac97_map_reg_idx(reg_ac97);
  647. bool unsupported = false;
  648. dev_dbg(chip->card->dev,
  649. "snd_azf3328_mixer_ac97_write reg_ac97 %u val %u\n",
  650. reg_ac97, val);
  651. if (reg_azf & AZF_AC97_REG_UNSUPPORTED)
  652. unsupported = true;
  653. else {
  654. if (reg_azf & AZF_AC97_REG_REAL_IO_WRITE)
  655. snd_azf3328_mixer_outw(
  656. chip,
  657. reg_azf & AZF_REG_MASK,
  658. val
  659. );
  660. else
  661. if (reg_azf & AZF_AC97_REG_EMU_IO_WRITE) {
  662. switch (reg_ac97) {
  663. case AC97_REC_GAIN_MIC:
  664. case AC97_POWERDOWN:
  665. case AC97_EXTENDED_STATUS:
  666. /*
  667. * Silently swallow these writes.
  668. * Since for most registers our card doesn't
  669. * actually support a comparable feature,
  670. * this is exactly what we should do here.
  671. * The AC97 layer's I/O caching probably
  672. * automatically takes care of all the rest...
  673. * (remembers written values etc.)
  674. */
  675. break;
  676. default:
  677. unsupported = true;
  678. break;
  679. }
  680. }
  681. }
  682. if (unsupported)
  683. snd_azf3328_mixer_ac97_map_unsupported(chip, reg_ac97, "write");
  684. }
  685. static int
  686. snd_azf3328_mixer_new(struct snd_azf3328 *chip)
  687. {
  688. struct snd_ac97_bus *bus;
  689. struct snd_ac97_template ac97;
  690. static const struct snd_ac97_bus_ops ops = {
  691. .write = snd_azf3328_mixer_ac97_write,
  692. .read = snd_azf3328_mixer_ac97_read,
  693. };
  694. int rc;
  695. memset(&ac97, 0, sizeof(ac97));
  696. ac97.scaps = AC97_SCAP_SKIP_MODEM
  697. | AC97_SCAP_AUDIO /* we support audio! */
  698. | AC97_SCAP_NO_SPDIF;
  699. ac97.private_data = chip;
  700. ac97.pci = chip->pci;
  701. /*
  702. * ALSA's AC97 layer has terrible init crackling issues,
  703. * unfortunately, and since it makes use of AC97_RESET,
  704. * there's no use trying to mute Master Playback proactively.
  705. */
  706. rc = snd_ac97_bus(chip->card, 0, &ops, NULL, &bus);
  707. if (!rc)
  708. rc = snd_ac97_mixer(bus, &ac97, &chip->ac97);
  709. /*
  710. * Make sure to complain loudly in case of AC97 init failure,
  711. * since failure may happen quite often,
  712. * due to this card being a very quirky AC97 "lookalike".
  713. */
  714. if (rc)
  715. dev_err(chip->card->dev, "AC97 init failed, err %d!\n", rc);
  716. /* If we return an error here, then snd_card_free() should
  717. * free up any ac97 codecs that got created, as well as the bus.
  718. */
  719. return rc;
  720. }
  721. #else /* AZF_USE_AC97_LAYER */
  722. static void
  723. snd_azf3328_mixer_write_volume_gradually(const struct snd_azf3328 *chip,
  724. unsigned reg,
  725. unsigned char dst_vol_left,
  726. unsigned char dst_vol_right,
  727. int chan_sel, int delay
  728. )
  729. {
  730. unsigned long portbase = chip->mixer_io + reg;
  731. unsigned char curr_vol_left = 0, curr_vol_right = 0;
  732. int left_change = 0, right_change = 0;
  733. if (chan_sel & SET_CHAN_LEFT) {
  734. curr_vol_left = inb(portbase + 1);
  735. /* take care of muting flag contained in left channel */
  736. if (curr_vol_left & AZF_MUTE_BIT)
  737. dst_vol_left |= AZF_MUTE_BIT;
  738. else
  739. dst_vol_left &= ~AZF_MUTE_BIT;
  740. left_change = (curr_vol_left > dst_vol_left) ? -1 : 1;
  741. }
  742. if (chan_sel & SET_CHAN_RIGHT) {
  743. curr_vol_right = inb(portbase + 0);
  744. right_change = (curr_vol_right > dst_vol_right) ? -1 : 1;
  745. }
  746. do {
  747. if (left_change) {
  748. if (curr_vol_left != dst_vol_left) {
  749. curr_vol_left += left_change;
  750. outb(curr_vol_left, portbase + 1);
  751. } else
  752. left_change = 0;
  753. }
  754. if (right_change) {
  755. if (curr_vol_right != dst_vol_right) {
  756. curr_vol_right += right_change;
  757. /* during volume change, the right channel is crackling
  758. * somewhat more than the left channel, unfortunately.
  759. * This seems to be a hardware issue. */
  760. outb(curr_vol_right, portbase + 0);
  761. } else
  762. right_change = 0;
  763. }
  764. if (delay)
  765. mdelay(delay);
  766. } while ((left_change) || (right_change));
  767. }
  768. /*
  769. * general mixer element
  770. */
  771. struct azf3328_mixer_reg {
  772. unsigned reg;
  773. unsigned int lchan_shift, rchan_shift;
  774. unsigned int mask;
  775. unsigned int invert: 1;
  776. unsigned int stereo: 1;
  777. unsigned int enum_c: 4;
  778. };
  779. #define COMPOSE_MIXER_REG(reg,lchan_shift,rchan_shift,mask,invert,stereo,enum_c) \
  780. ((reg) | (lchan_shift << 8) | (rchan_shift << 12) | \
  781. (mask << 16) | \
  782. (invert << 24) | \
  783. (stereo << 25) | \
  784. (enum_c << 26))
  785. static void snd_azf3328_mixer_reg_decode(struct azf3328_mixer_reg *r, unsigned long val)
  786. {
  787. r->reg = val & 0xff;
  788. r->lchan_shift = (val >> 8) & 0x0f;
  789. r->rchan_shift = (val >> 12) & 0x0f;
  790. r->mask = (val >> 16) & 0xff;
  791. r->invert = (val >> 24) & 1;
  792. r->stereo = (val >> 25) & 1;
  793. r->enum_c = (val >> 26) & 0x0f;
  794. }
  795. /*
  796. * mixer switches/volumes
  797. */
  798. #define AZF3328_MIXER_SWITCH(xname, reg, shift, invert) \
  799. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  800. .info = snd_azf3328_info_mixer, \
  801. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  802. .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0x1, invert, 0, 0), \
  803. }
  804. #define AZF3328_MIXER_VOL_STEREO(xname, reg, mask, invert) \
  805. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  806. .info = snd_azf3328_info_mixer, \
  807. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  808. .private_value = COMPOSE_MIXER_REG(reg, 8, 0, mask, invert, 1, 0), \
  809. }
  810. #define AZF3328_MIXER_VOL_MONO(xname, reg, mask, is_right_chan) \
  811. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  812. .info = snd_azf3328_info_mixer, \
  813. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  814. .private_value = COMPOSE_MIXER_REG(reg, is_right_chan ? 0 : 8, 0, mask, 1, 0, 0), \
  815. }
  816. #define AZF3328_MIXER_VOL_SPECIAL(xname, reg, mask, shift, invert) \
  817. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  818. .info = snd_azf3328_info_mixer, \
  819. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  820. .private_value = COMPOSE_MIXER_REG(reg, shift, 0, mask, invert, 0, 0), \
  821. }
  822. #define AZF3328_MIXER_ENUM(xname, reg, enum_c, shift) \
  823. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  824. .info = snd_azf3328_info_mixer_enum, \
  825. .get = snd_azf3328_get_mixer_enum, .put = snd_azf3328_put_mixer_enum, \
  826. .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0, 0, 0, enum_c), \
  827. }
  828. static int
  829. snd_azf3328_info_mixer(struct snd_kcontrol *kcontrol,
  830. struct snd_ctl_elem_info *uinfo)
  831. {
  832. struct azf3328_mixer_reg reg;
  833. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  834. uinfo->type = reg.mask == 1 ?
  835. SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  836. uinfo->count = reg.stereo + 1;
  837. uinfo->value.integer.min = 0;
  838. uinfo->value.integer.max = reg.mask;
  839. return 0;
  840. }
  841. static int
  842. snd_azf3328_get_mixer(struct snd_kcontrol *kcontrol,
  843. struct snd_ctl_elem_value *ucontrol)
  844. {
  845. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  846. struct azf3328_mixer_reg reg;
  847. u16 oreg, val;
  848. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  849. oreg = snd_azf3328_mixer_inw(chip, reg.reg);
  850. val = (oreg >> reg.lchan_shift) & reg.mask;
  851. if (reg.invert)
  852. val = reg.mask - val;
  853. ucontrol->value.integer.value[0] = val;
  854. if (reg.stereo) {
  855. val = (oreg >> reg.rchan_shift) & reg.mask;
  856. if (reg.invert)
  857. val = reg.mask - val;
  858. ucontrol->value.integer.value[1] = val;
  859. }
  860. dev_dbg(chip->card->dev,
  861. "get: %02x is %04x -> vol %02lx|%02lx (shift %02d|%02d, mask %02x, inv. %d, stereo %d)\n",
  862. reg.reg, oreg,
  863. ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
  864. reg.lchan_shift, reg.rchan_shift, reg.mask, reg.invert, reg.stereo);
  865. return 0;
  866. }
  867. static int
  868. snd_azf3328_put_mixer(struct snd_kcontrol *kcontrol,
  869. struct snd_ctl_elem_value *ucontrol)
  870. {
  871. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  872. struct azf3328_mixer_reg reg;
  873. u16 oreg, nreg, val;
  874. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  875. oreg = snd_azf3328_mixer_inw(chip, reg.reg);
  876. val = ucontrol->value.integer.value[0] & reg.mask;
  877. if (reg.invert)
  878. val = reg.mask - val;
  879. nreg = oreg & ~(reg.mask << reg.lchan_shift);
  880. nreg |= (val << reg.lchan_shift);
  881. if (reg.stereo) {
  882. val = ucontrol->value.integer.value[1] & reg.mask;
  883. if (reg.invert)
  884. val = reg.mask - val;
  885. nreg &= ~(reg.mask << reg.rchan_shift);
  886. nreg |= (val << reg.rchan_shift);
  887. }
  888. if (reg.mask >= 0x07) /* it's a volume control, so better take care */
  889. snd_azf3328_mixer_write_volume_gradually(
  890. chip, reg.reg, nreg >> 8, nreg & 0xff,
  891. /* just set both channels, doesn't matter */
  892. SET_CHAN_LEFT|SET_CHAN_RIGHT,
  893. 0);
  894. else
  895. snd_azf3328_mixer_outw(chip, reg.reg, nreg);
  896. dev_dbg(chip->card->dev,
  897. "put: %02x to %02lx|%02lx, oreg %04x; shift %02d|%02d -> nreg %04x; after: %04x\n",
  898. reg.reg, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
  899. oreg, reg.lchan_shift, reg.rchan_shift,
  900. nreg, snd_azf3328_mixer_inw(chip, reg.reg));
  901. return (nreg != oreg);
  902. }
  903. static int
  904. snd_azf3328_info_mixer_enum(struct snd_kcontrol *kcontrol,
  905. struct snd_ctl_elem_info *uinfo)
  906. {
  907. static const char * const texts1[] = {
  908. "Mic1", "Mic2"
  909. };
  910. static const char * const texts2[] = {
  911. "Mix", "Mic"
  912. };
  913. static const char * const texts3[] = {
  914. "Mic", "CD", "Video", "Aux",
  915. "Line", "Mix", "Mix Mono", "Phone"
  916. };
  917. static const char * const texts4[] = {
  918. "pre 3D", "post 3D"
  919. };
  920. struct azf3328_mixer_reg reg;
  921. const char * const *p = NULL;
  922. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  923. if (reg.reg == IDX_MIXER_ADVCTL2) {
  924. switch(reg.lchan_shift) {
  925. case 8: /* modem out sel */
  926. p = texts1;
  927. break;
  928. case 9: /* mono sel source */
  929. p = texts2;
  930. break;
  931. case 15: /* PCM Out Path */
  932. p = texts4;
  933. break;
  934. }
  935. } else if (reg.reg == IDX_MIXER_REC_SELECT)
  936. p = texts3;
  937. return snd_ctl_enum_info(uinfo,
  938. (reg.reg == IDX_MIXER_REC_SELECT) ? 2 : 1,
  939. reg.enum_c, p);
  940. }
  941. static int
  942. snd_azf3328_get_mixer_enum(struct snd_kcontrol *kcontrol,
  943. struct snd_ctl_elem_value *ucontrol)
  944. {
  945. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  946. struct azf3328_mixer_reg reg;
  947. unsigned short val;
  948. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  949. val = snd_azf3328_mixer_inw(chip, reg.reg);
  950. if (reg.reg == IDX_MIXER_REC_SELECT) {
  951. ucontrol->value.enumerated.item[0] = (val >> 8) & (reg.enum_c - 1);
  952. ucontrol->value.enumerated.item[1] = (val >> 0) & (reg.enum_c - 1);
  953. } else
  954. ucontrol->value.enumerated.item[0] = (val >> reg.lchan_shift) & (reg.enum_c - 1);
  955. dev_dbg(chip->card->dev,
  956. "get_enum: %02x is %04x -> %d|%d (shift %02d, enum_c %d)\n",
  957. reg.reg, val, ucontrol->value.enumerated.item[0], ucontrol->value.enumerated.item[1],
  958. reg.lchan_shift, reg.enum_c);
  959. return 0;
  960. }
  961. static int
  962. snd_azf3328_put_mixer_enum(struct snd_kcontrol *kcontrol,
  963. struct snd_ctl_elem_value *ucontrol)
  964. {
  965. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  966. struct azf3328_mixer_reg reg;
  967. u16 oreg, nreg, val;
  968. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  969. oreg = snd_azf3328_mixer_inw(chip, reg.reg);
  970. val = oreg;
  971. if (reg.reg == IDX_MIXER_REC_SELECT) {
  972. if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U ||
  973. ucontrol->value.enumerated.item[1] > reg.enum_c - 1U)
  974. return -EINVAL;
  975. val = (ucontrol->value.enumerated.item[0] << 8) |
  976. (ucontrol->value.enumerated.item[1] << 0);
  977. } else {
  978. if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U)
  979. return -EINVAL;
  980. val &= ~((reg.enum_c - 1) << reg.lchan_shift);
  981. val |= (ucontrol->value.enumerated.item[0] << reg.lchan_shift);
  982. }
  983. snd_azf3328_mixer_outw(chip, reg.reg, val);
  984. nreg = val;
  985. dev_dbg(chip->card->dev,
  986. "put_enum: %02x to %04x, oreg %04x\n", reg.reg, val, oreg);
  987. return (nreg != oreg);
  988. }
  989. static const struct snd_kcontrol_new snd_azf3328_mixer_controls[] = {
  990. AZF3328_MIXER_SWITCH("Master Playback Switch", IDX_MIXER_PLAY_MASTER, 15, 1),
  991. AZF3328_MIXER_VOL_STEREO("Master Playback Volume", IDX_MIXER_PLAY_MASTER, 0x1f, 1),
  992. AZF3328_MIXER_SWITCH("PCM Playback Switch", IDX_MIXER_WAVEOUT, 15, 1),
  993. AZF3328_MIXER_VOL_STEREO("PCM Playback Volume",
  994. IDX_MIXER_WAVEOUT, 0x1f, 1),
  995. AZF3328_MIXER_SWITCH("PCM 3D Bypass Playback Switch",
  996. IDX_MIXER_ADVCTL2, 7, 1),
  997. AZF3328_MIXER_SWITCH("FM Playback Switch", IDX_MIXER_FMSYNTH, 15, 1),
  998. AZF3328_MIXER_VOL_STEREO("FM Playback Volume", IDX_MIXER_FMSYNTH, 0x1f, 1),
  999. AZF3328_MIXER_SWITCH("CD Playback Switch", IDX_MIXER_CDAUDIO, 15, 1),
  1000. AZF3328_MIXER_VOL_STEREO("CD Playback Volume", IDX_MIXER_CDAUDIO, 0x1f, 1),
  1001. AZF3328_MIXER_SWITCH("Capture Switch", IDX_MIXER_REC_VOLUME, 15, 1),
  1002. AZF3328_MIXER_VOL_STEREO("Capture Volume", IDX_MIXER_REC_VOLUME, 0x0f, 0),
  1003. AZF3328_MIXER_ENUM("Capture Source", IDX_MIXER_REC_SELECT, 8, 0),
  1004. AZF3328_MIXER_SWITCH("Mic Playback Switch", IDX_MIXER_MIC, 15, 1),
  1005. AZF3328_MIXER_VOL_MONO("Mic Playback Volume", IDX_MIXER_MIC, 0x1f, 1),
  1006. AZF3328_MIXER_SWITCH("Mic Boost (+20dB)", IDX_MIXER_MIC, 6, 0),
  1007. AZF3328_MIXER_SWITCH("Line Playback Switch", IDX_MIXER_LINEIN, 15, 1),
  1008. AZF3328_MIXER_VOL_STEREO("Line Playback Volume", IDX_MIXER_LINEIN, 0x1f, 1),
  1009. AZF3328_MIXER_SWITCH("Beep Playback Switch", IDX_MIXER_PCBEEP, 15, 1),
  1010. AZF3328_MIXER_VOL_SPECIAL("Beep Playback Volume", IDX_MIXER_PCBEEP, 0x0f, 1, 1),
  1011. AZF3328_MIXER_SWITCH("Video Playback Switch", IDX_MIXER_VIDEO, 15, 1),
  1012. AZF3328_MIXER_VOL_STEREO("Video Playback Volume", IDX_MIXER_VIDEO, 0x1f, 1),
  1013. AZF3328_MIXER_SWITCH("Aux Playback Switch", IDX_MIXER_AUX, 15, 1),
  1014. AZF3328_MIXER_VOL_STEREO("Aux Playback Volume", IDX_MIXER_AUX, 0x1f, 1),
  1015. AZF3328_MIXER_SWITCH("Modem Playback Switch", IDX_MIXER_MODEMOUT, 15, 1),
  1016. AZF3328_MIXER_VOL_MONO("Modem Playback Volume", IDX_MIXER_MODEMOUT, 0x1f, 1),
  1017. AZF3328_MIXER_SWITCH("Modem Capture Switch", IDX_MIXER_MODEMIN, 15, 1),
  1018. AZF3328_MIXER_VOL_MONO("Modem Capture Volume", IDX_MIXER_MODEMIN, 0x1f, 1),
  1019. AZF3328_MIXER_ENUM("Mic Select", IDX_MIXER_ADVCTL2, 2, 8),
  1020. AZF3328_MIXER_ENUM("Mono Output Select", IDX_MIXER_ADVCTL2, 2, 9),
  1021. AZF3328_MIXER_ENUM("PCM Output Route", IDX_MIXER_ADVCTL2, 2, 15), /* PCM Out Path, place in front since it controls *both* 3D and Bass/Treble! */
  1022. AZF3328_MIXER_VOL_SPECIAL("Tone Control - Treble", IDX_MIXER_BASSTREBLE, 0x07, 1, 0),
  1023. AZF3328_MIXER_VOL_SPECIAL("Tone Control - Bass", IDX_MIXER_BASSTREBLE, 0x07, 9, 0),
  1024. AZF3328_MIXER_SWITCH("3D Control - Switch", IDX_MIXER_ADVCTL2, 13, 0),
  1025. AZF3328_MIXER_VOL_SPECIAL("3D Control - Width", IDX_MIXER_ADVCTL1, 0x07, 1, 0), /* "3D Width" */
  1026. AZF3328_MIXER_VOL_SPECIAL("3D Control - Depth", IDX_MIXER_ADVCTL1, 0x03, 8, 0), /* "Hifi 3D" */
  1027. #if MIXER_TESTING
  1028. AZF3328_MIXER_SWITCH("0", IDX_MIXER_ADVCTL2, 0, 0),
  1029. AZF3328_MIXER_SWITCH("1", IDX_MIXER_ADVCTL2, 1, 0),
  1030. AZF3328_MIXER_SWITCH("2", IDX_MIXER_ADVCTL2, 2, 0),
  1031. AZF3328_MIXER_SWITCH("3", IDX_MIXER_ADVCTL2, 3, 0),
  1032. AZF3328_MIXER_SWITCH("4", IDX_MIXER_ADVCTL2, 4, 0),
  1033. AZF3328_MIXER_SWITCH("5", IDX_MIXER_ADVCTL2, 5, 0),
  1034. AZF3328_MIXER_SWITCH("6", IDX_MIXER_ADVCTL2, 6, 0),
  1035. AZF3328_MIXER_SWITCH("7", IDX_MIXER_ADVCTL2, 7, 0),
  1036. AZF3328_MIXER_SWITCH("8", IDX_MIXER_ADVCTL2, 8, 0),
  1037. AZF3328_MIXER_SWITCH("9", IDX_MIXER_ADVCTL2, 9, 0),
  1038. AZF3328_MIXER_SWITCH("10", IDX_MIXER_ADVCTL2, 10, 0),
  1039. AZF3328_MIXER_SWITCH("11", IDX_MIXER_ADVCTL2, 11, 0),
  1040. AZF3328_MIXER_SWITCH("12", IDX_MIXER_ADVCTL2, 12, 0),
  1041. AZF3328_MIXER_SWITCH("13", IDX_MIXER_ADVCTL2, 13, 0),
  1042. AZF3328_MIXER_SWITCH("14", IDX_MIXER_ADVCTL2, 14, 0),
  1043. AZF3328_MIXER_SWITCH("15", IDX_MIXER_ADVCTL2, 15, 0),
  1044. #endif
  1045. };
  1046. static const u16 snd_azf3328_init_values[][2] = {
  1047. { IDX_MIXER_PLAY_MASTER, MIXER_MUTE_MASK|0x1f1f },
  1048. { IDX_MIXER_MODEMOUT, MIXER_MUTE_MASK|0x1f1f },
  1049. { IDX_MIXER_BASSTREBLE, 0x0000 },
  1050. { IDX_MIXER_PCBEEP, MIXER_MUTE_MASK|0x1f1f },
  1051. { IDX_MIXER_MODEMIN, MIXER_MUTE_MASK|0x1f1f },
  1052. { IDX_MIXER_MIC, MIXER_MUTE_MASK|0x001f },
  1053. { IDX_MIXER_LINEIN, MIXER_MUTE_MASK|0x1f1f },
  1054. { IDX_MIXER_CDAUDIO, MIXER_MUTE_MASK|0x1f1f },
  1055. { IDX_MIXER_VIDEO, MIXER_MUTE_MASK|0x1f1f },
  1056. { IDX_MIXER_AUX, MIXER_MUTE_MASK|0x1f1f },
  1057. { IDX_MIXER_WAVEOUT, MIXER_MUTE_MASK|0x1f1f },
  1058. { IDX_MIXER_FMSYNTH, MIXER_MUTE_MASK|0x1f1f },
  1059. { IDX_MIXER_REC_VOLUME, MIXER_MUTE_MASK|0x0707 },
  1060. };
  1061. static int
  1062. snd_azf3328_mixer_new(struct snd_azf3328 *chip)
  1063. {
  1064. struct snd_card *card;
  1065. const struct snd_kcontrol_new *sw;
  1066. unsigned int idx;
  1067. int err;
  1068. if (snd_BUG_ON(!chip || !chip->card))
  1069. return -EINVAL;
  1070. card = chip->card;
  1071. /* mixer reset */
  1072. snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
  1073. /* mute and zero volume channels */
  1074. for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_init_values); ++idx) {
  1075. snd_azf3328_mixer_outw(chip,
  1076. snd_azf3328_init_values[idx][0],
  1077. snd_azf3328_init_values[idx][1]);
  1078. }
  1079. /* add mixer controls */
  1080. sw = snd_azf3328_mixer_controls;
  1081. for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_mixer_controls);
  1082. ++idx, ++sw) {
  1083. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(sw, chip))) < 0)
  1084. return err;
  1085. }
  1086. snd_component_add(card, "AZF3328 mixer");
  1087. strcpy(card->mixername, "AZF3328 mixer");
  1088. return 0;
  1089. }
  1090. #endif /* AZF_USE_AC97_LAYER */
  1091. static void
  1092. snd_azf3328_codec_setfmt(struct snd_azf3328_codec_data *codec,
  1093. enum azf_freq_t bitrate,
  1094. unsigned int format_width,
  1095. unsigned int channels
  1096. )
  1097. {
  1098. unsigned long flags;
  1099. u16 val = 0xff00;
  1100. u8 freq = 0;
  1101. switch (bitrate) {
  1102. case AZF_FREQ_4000: freq = SOUNDFORMAT_FREQ_SUSPECTED_4000; break;
  1103. case AZF_FREQ_4800: freq = SOUNDFORMAT_FREQ_SUSPECTED_4800; break;
  1104. case AZF_FREQ_5512:
  1105. /* the AZF3328 names it "5510" for some strange reason */
  1106. freq = SOUNDFORMAT_FREQ_5510; break;
  1107. case AZF_FREQ_6620: freq = SOUNDFORMAT_FREQ_6620; break;
  1108. case AZF_FREQ_8000: freq = SOUNDFORMAT_FREQ_8000; break;
  1109. case AZF_FREQ_9600: freq = SOUNDFORMAT_FREQ_9600; break;
  1110. case AZF_FREQ_11025: freq = SOUNDFORMAT_FREQ_11025; break;
  1111. case AZF_FREQ_13240: freq = SOUNDFORMAT_FREQ_SUSPECTED_13240; break;
  1112. case AZF_FREQ_16000: freq = SOUNDFORMAT_FREQ_16000; break;
  1113. case AZF_FREQ_22050: freq = SOUNDFORMAT_FREQ_22050; break;
  1114. case AZF_FREQ_32000: freq = SOUNDFORMAT_FREQ_32000; break;
  1115. default:
  1116. snd_printk(KERN_WARNING "unknown bitrate %d, assuming 44.1kHz!\n", bitrate);
  1117. fallthrough;
  1118. case AZF_FREQ_44100: freq = SOUNDFORMAT_FREQ_44100; break;
  1119. case AZF_FREQ_48000: freq = SOUNDFORMAT_FREQ_48000; break;
  1120. case AZF_FREQ_66200: freq = SOUNDFORMAT_FREQ_SUSPECTED_66200; break;
  1121. }
  1122. /* val = 0xff07; 3m27.993s (65301Hz; -> 64000Hz???) hmm, 66120, 65967, 66123 */
  1123. /* val = 0xff09; 17m15.098s (13123,478Hz; -> 12000Hz???) hmm, 13237.2Hz? */
  1124. /* val = 0xff0a; 47m30.599s (4764,891Hz; -> 4800Hz???) yup, 4803Hz */
  1125. /* val = 0xff0c; 57m0.510s (4010,263Hz; -> 4000Hz???) yup, 4003Hz */
  1126. /* val = 0xff05; 5m11.556s (... -> 44100Hz) */
  1127. /* val = 0xff03; 10m21.529s (21872,463Hz; -> 22050Hz???) */
  1128. /* val = 0xff0f; 20m41.883s (10937,993Hz; -> 11025Hz???) */
  1129. /* val = 0xff0d; 41m23.135s (5523,600Hz; -> 5512Hz???) */
  1130. /* val = 0xff0e; 28m30.777s (8017Hz; -> 8000Hz???) */
  1131. val |= freq;
  1132. if (channels == 2)
  1133. val |= SOUNDFORMAT_FLAG_2CHANNELS;
  1134. if (format_width == 16)
  1135. val |= SOUNDFORMAT_FLAG_16BIT;
  1136. spin_lock_irqsave(codec->lock, flags);
  1137. /* set bitrate/format */
  1138. snd_azf3328_codec_outw(codec, IDX_IO_CODEC_SOUNDFORMAT, val);
  1139. /* changing the bitrate/format settings switches off the
  1140. * audio output with an annoying click in case of 8/16bit format change
  1141. * (maybe shutting down DAC/ADC?), thus immediately
  1142. * do some tweaking to reenable it and get rid of the clicking
  1143. * (FIXME: yes, it works, but what exactly am I doing here?? :)
  1144. * FIXME: does this have some side effects for full-duplex
  1145. * or other dramatic side effects? */
  1146. /* do it for non-capture codecs only */
  1147. if (codec->type != AZF_CODEC_CAPTURE)
  1148. snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
  1149. snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS) |
  1150. DMA_RUN_SOMETHING1 |
  1151. DMA_RUN_SOMETHING2 |
  1152. SOMETHING_ALMOST_ALWAYS_SET |
  1153. DMA_EPILOGUE_SOMETHING |
  1154. DMA_SOMETHING_ELSE
  1155. );
  1156. spin_unlock_irqrestore(codec->lock, flags);
  1157. }
  1158. static inline void
  1159. snd_azf3328_codec_setfmt_lowpower(struct snd_azf3328_codec_data *codec
  1160. )
  1161. {
  1162. /* choose lowest frequency for low power consumption.
  1163. * While this will cause louder noise due to rather coarse frequency,
  1164. * it should never matter since output should always
  1165. * get disabled properly when idle anyway. */
  1166. snd_azf3328_codec_setfmt(codec, AZF_FREQ_4000, 8, 1);
  1167. }
  1168. static void
  1169. snd_azf3328_ctrl_reg_6AH_update(struct snd_azf3328 *chip,
  1170. unsigned bitmask,
  1171. bool enable
  1172. )
  1173. {
  1174. bool do_mask = !enable;
  1175. if (do_mask)
  1176. chip->shadow_reg_ctrl_6AH |= bitmask;
  1177. else
  1178. chip->shadow_reg_ctrl_6AH &= ~bitmask;
  1179. dev_dbg(chip->card->dev,
  1180. "6AH_update mask 0x%04x do_mask %d: val 0x%04x\n",
  1181. bitmask, do_mask, chip->shadow_reg_ctrl_6AH);
  1182. snd_azf3328_ctrl_outw(chip, IDX_IO_6AH, chip->shadow_reg_ctrl_6AH);
  1183. }
  1184. static inline void
  1185. snd_azf3328_ctrl_enable_codecs(struct snd_azf3328 *chip, bool enable)
  1186. {
  1187. dev_dbg(chip->card->dev, "codec_enable %d\n", enable);
  1188. /* no idea what exactly is being done here, but I strongly assume it's
  1189. * PM related */
  1190. snd_azf3328_ctrl_reg_6AH_update(
  1191. chip, IO_6A_PAUSE_PLAYBACK_BIT8, enable
  1192. );
  1193. }
  1194. static void
  1195. snd_azf3328_ctrl_codec_activity(struct snd_azf3328 *chip,
  1196. enum snd_azf3328_codec_type codec_type,
  1197. bool enable
  1198. )
  1199. {
  1200. struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type];
  1201. bool need_change = (codec->running != enable);
  1202. dev_dbg(chip->card->dev,
  1203. "codec_activity: %s codec, enable %d, need_change %d\n",
  1204. codec->name, enable, need_change
  1205. );
  1206. if (need_change) {
  1207. static const struct {
  1208. enum snd_azf3328_codec_type other1;
  1209. enum snd_azf3328_codec_type other2;
  1210. } peer_codecs[3] =
  1211. { { AZF_CODEC_CAPTURE, AZF_CODEC_I2S_OUT },
  1212. { AZF_CODEC_PLAYBACK, AZF_CODEC_I2S_OUT },
  1213. { AZF_CODEC_PLAYBACK, AZF_CODEC_CAPTURE } };
  1214. bool call_function;
  1215. if (enable)
  1216. /* if enable codec, call enable_codecs func
  1217. to enable codec supply... */
  1218. call_function = 1;
  1219. else {
  1220. /* ...otherwise call enable_codecs func
  1221. (which globally shuts down operation of codecs)
  1222. only in case the other codecs are currently
  1223. not active either! */
  1224. call_function =
  1225. ((!chip->codecs[peer_codecs[codec_type].other1]
  1226. .running)
  1227. && (!chip->codecs[peer_codecs[codec_type].other2]
  1228. .running));
  1229. }
  1230. if (call_function)
  1231. snd_azf3328_ctrl_enable_codecs(chip, enable);
  1232. /* ...and adjust clock, too
  1233. * (reduce noise and power consumption) */
  1234. if (!enable)
  1235. snd_azf3328_codec_setfmt_lowpower(codec);
  1236. codec->running = enable;
  1237. }
  1238. }
  1239. static void
  1240. snd_azf3328_codec_setdmaa(struct snd_azf3328 *chip,
  1241. struct snd_azf3328_codec_data *codec,
  1242. unsigned long addr,
  1243. unsigned int period_bytes,
  1244. unsigned int buffer_bytes
  1245. )
  1246. {
  1247. WARN_ONCE(period_bytes & 1, "odd period length!?\n");
  1248. WARN_ONCE(buffer_bytes != 2 * period_bytes,
  1249. "missed our input expectations! %u vs. %u\n",
  1250. buffer_bytes, period_bytes);
  1251. if (!codec->running) {
  1252. /* AZF3328 uses a two buffer pointer DMA transfer approach */
  1253. unsigned long flags;
  1254. /* width 32bit (prevent overflow): */
  1255. u32 area_length;
  1256. struct codec_setup_io {
  1257. u32 dma_start_1;
  1258. u32 dma_start_2;
  1259. u32 dma_lengths;
  1260. } __attribute__((packed)) setup_io;
  1261. area_length = buffer_bytes/2;
  1262. setup_io.dma_start_1 = addr;
  1263. setup_io.dma_start_2 = addr+area_length;
  1264. dev_dbg(chip->card->dev,
  1265. "setdma: buffers %08x[%u] / %08x[%u], %u, %u\n",
  1266. setup_io.dma_start_1, area_length,
  1267. setup_io.dma_start_2, area_length,
  1268. period_bytes, buffer_bytes);
  1269. /* Hmm, are we really supposed to decrement this by 1??
  1270. Most definitely certainly not: configuring full length does
  1271. work properly (i.e. likely better), and BTW we
  1272. violated possibly differing frame sizes with this...
  1273. area_length--; |* max. index *|
  1274. */
  1275. /* build combined I/O buffer length word */
  1276. setup_io.dma_lengths = (area_length << 16) | (area_length);
  1277. spin_lock_irqsave(codec->lock, flags);
  1278. snd_azf3328_codec_outl_multi(
  1279. codec, IDX_IO_CODEC_DMA_START_1, &setup_io, 3
  1280. );
  1281. spin_unlock_irqrestore(codec->lock, flags);
  1282. }
  1283. }
  1284. static int
  1285. snd_azf3328_pcm_prepare(struct snd_pcm_substream *substream)
  1286. {
  1287. struct snd_pcm_runtime *runtime = substream->runtime;
  1288. struct snd_azf3328_codec_data *codec = runtime->private_data;
  1289. #if 0
  1290. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  1291. unsigned int count = snd_pcm_lib_period_bytes(substream);
  1292. #endif
  1293. codec->dma_base = runtime->dma_addr;
  1294. #if 0
  1295. snd_azf3328_codec_setfmt(codec,
  1296. runtime->rate,
  1297. snd_pcm_format_width(runtime->format),
  1298. runtime->channels);
  1299. snd_azf3328_codec_setdmaa(chip, codec,
  1300. runtime->dma_addr, count, size);
  1301. #endif
  1302. return 0;
  1303. }
  1304. static int
  1305. snd_azf3328_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
  1306. {
  1307. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1308. struct snd_pcm_runtime *runtime = substream->runtime;
  1309. struct snd_azf3328_codec_data *codec = runtime->private_data;
  1310. int result = 0;
  1311. u16 flags1;
  1312. bool previously_muted = false;
  1313. bool is_main_mixer_playback_codec = (AZF_CODEC_PLAYBACK == codec->type);
  1314. switch (cmd) {
  1315. case SNDRV_PCM_TRIGGER_START:
  1316. dev_dbg(chip->card->dev, "START PCM %s\n", codec->name);
  1317. if (is_main_mixer_playback_codec) {
  1318. /* mute WaveOut (avoid clicking during setup) */
  1319. previously_muted =
  1320. snd_azf3328_mixer_mute_control_pcm(
  1321. chip, 1
  1322. );
  1323. }
  1324. snd_azf3328_codec_setfmt(codec,
  1325. runtime->rate,
  1326. snd_pcm_format_width(runtime->format),
  1327. runtime->channels);
  1328. spin_lock(codec->lock);
  1329. /* first, remember current value: */
  1330. flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS);
  1331. /* stop transfer */
  1332. flags1 &= ~DMA_RESUME;
  1333. snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
  1334. /* FIXME: clear interrupts or what??? */
  1335. snd_azf3328_codec_outw(codec, IDX_IO_CODEC_IRQTYPE, 0xffff);
  1336. spin_unlock(codec->lock);
  1337. snd_azf3328_codec_setdmaa(chip, codec, runtime->dma_addr,
  1338. snd_pcm_lib_period_bytes(substream),
  1339. snd_pcm_lib_buffer_bytes(substream)
  1340. );
  1341. spin_lock(codec->lock);
  1342. #ifdef WIN9X
  1343. /* FIXME: enable playback/recording??? */
  1344. flags1 |= DMA_RUN_SOMETHING1 | DMA_RUN_SOMETHING2;
  1345. snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
  1346. /* start transfer again */
  1347. /* FIXME: what is this value (0x0010)??? */
  1348. flags1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING;
  1349. snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
  1350. #else /* NT4 */
  1351. snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
  1352. 0x0000);
  1353. snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
  1354. DMA_RUN_SOMETHING1);
  1355. snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
  1356. DMA_RUN_SOMETHING1 |
  1357. DMA_RUN_SOMETHING2);
  1358. snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
  1359. DMA_RESUME |
  1360. SOMETHING_ALMOST_ALWAYS_SET |
  1361. DMA_EPILOGUE_SOMETHING |
  1362. DMA_SOMETHING_ELSE);
  1363. #endif
  1364. spin_unlock(codec->lock);
  1365. snd_azf3328_ctrl_codec_activity(chip, codec->type, 1);
  1366. if (is_main_mixer_playback_codec) {
  1367. /* now unmute WaveOut */
  1368. if (!previously_muted)
  1369. snd_azf3328_mixer_mute_control_pcm(
  1370. chip, 0
  1371. );
  1372. }
  1373. dev_dbg(chip->card->dev, "PCM STARTED %s\n", codec->name);
  1374. break;
  1375. case SNDRV_PCM_TRIGGER_RESUME:
  1376. dev_dbg(chip->card->dev, "PCM RESUME %s\n", codec->name);
  1377. /* resume codec if we were active */
  1378. spin_lock(codec->lock);
  1379. if (codec->running)
  1380. snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
  1381. snd_azf3328_codec_inw(
  1382. codec, IDX_IO_CODEC_DMA_FLAGS
  1383. ) | DMA_RESUME
  1384. );
  1385. spin_unlock(codec->lock);
  1386. break;
  1387. case SNDRV_PCM_TRIGGER_STOP:
  1388. dev_dbg(chip->card->dev, "PCM STOP %s\n", codec->name);
  1389. if (is_main_mixer_playback_codec) {
  1390. /* mute WaveOut (avoid clicking during setup) */
  1391. previously_muted =
  1392. snd_azf3328_mixer_mute_control_pcm(
  1393. chip, 1
  1394. );
  1395. }
  1396. spin_lock(codec->lock);
  1397. /* first, remember current value: */
  1398. flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS);
  1399. /* stop transfer */
  1400. flags1 &= ~DMA_RESUME;
  1401. snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
  1402. /* hmm, is this really required? we're resetting the same bit
  1403. * immediately thereafter... */
  1404. flags1 |= DMA_RUN_SOMETHING1;
  1405. snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
  1406. flags1 &= ~DMA_RUN_SOMETHING1;
  1407. snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
  1408. spin_unlock(codec->lock);
  1409. snd_azf3328_ctrl_codec_activity(chip, codec->type, 0);
  1410. if (is_main_mixer_playback_codec) {
  1411. /* now unmute WaveOut */
  1412. if (!previously_muted)
  1413. snd_azf3328_mixer_mute_control_pcm(
  1414. chip, 0
  1415. );
  1416. }
  1417. dev_dbg(chip->card->dev, "PCM STOPPED %s\n", codec->name);
  1418. break;
  1419. case SNDRV_PCM_TRIGGER_SUSPEND:
  1420. dev_dbg(chip->card->dev, "PCM SUSPEND %s\n", codec->name);
  1421. /* make sure codec is stopped */
  1422. snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
  1423. snd_azf3328_codec_inw(
  1424. codec, IDX_IO_CODEC_DMA_FLAGS
  1425. ) & ~DMA_RESUME
  1426. );
  1427. break;
  1428. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  1429. WARN(1, "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n");
  1430. break;
  1431. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  1432. WARN(1, "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n");
  1433. break;
  1434. default:
  1435. WARN(1, "FIXME: unknown trigger mode!\n");
  1436. return -EINVAL;
  1437. }
  1438. return result;
  1439. }
  1440. static snd_pcm_uframes_t
  1441. snd_azf3328_pcm_pointer(struct snd_pcm_substream *substream
  1442. )
  1443. {
  1444. const struct snd_azf3328_codec_data *codec =
  1445. substream->runtime->private_data;
  1446. unsigned long result;
  1447. snd_pcm_uframes_t frmres;
  1448. result = snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_CURRPOS);
  1449. /* calculate offset */
  1450. #ifdef QUERY_HARDWARE
  1451. result -= snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_START_1);
  1452. #else
  1453. result -= codec->dma_base;
  1454. #endif
  1455. frmres = bytes_to_frames( substream->runtime, result);
  1456. dev_dbg(substream->pcm->card->dev, "%08li %s @ 0x%8lx, frames %8ld\n",
  1457. jiffies, codec->name, result, frmres);
  1458. return frmres;
  1459. }
  1460. /******************************************************************/
  1461. #ifdef SUPPORT_GAMEPORT
  1462. static inline void
  1463. snd_azf3328_gameport_irq_enable(struct snd_azf3328 *chip,
  1464. bool enable
  1465. )
  1466. {
  1467. snd_azf3328_io_reg_setb(
  1468. chip->game_io+IDX_GAME_HWCONFIG,
  1469. GAME_HWCFG_IRQ_ENABLE,
  1470. enable
  1471. );
  1472. }
  1473. static inline void
  1474. snd_azf3328_gameport_legacy_address_enable(struct snd_azf3328 *chip,
  1475. bool enable
  1476. )
  1477. {
  1478. snd_azf3328_io_reg_setb(
  1479. chip->game_io+IDX_GAME_HWCONFIG,
  1480. GAME_HWCFG_LEGACY_ADDRESS_ENABLE,
  1481. enable
  1482. );
  1483. }
  1484. static void
  1485. snd_azf3328_gameport_set_counter_frequency(struct snd_azf3328 *chip,
  1486. unsigned int freq_cfg
  1487. )
  1488. {
  1489. snd_azf3328_io_reg_setb(
  1490. chip->game_io+IDX_GAME_HWCONFIG,
  1491. 0x02,
  1492. (freq_cfg & 1) != 0
  1493. );
  1494. snd_azf3328_io_reg_setb(
  1495. chip->game_io+IDX_GAME_HWCONFIG,
  1496. 0x04,
  1497. (freq_cfg & 2) != 0
  1498. );
  1499. }
  1500. static inline void
  1501. snd_azf3328_gameport_axis_circuit_enable(struct snd_azf3328 *chip, bool enable)
  1502. {
  1503. snd_azf3328_ctrl_reg_6AH_update(
  1504. chip, IO_6A_SOMETHING2_GAMEPORT, enable
  1505. );
  1506. }
  1507. static inline void
  1508. snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip)
  1509. {
  1510. /*
  1511. * skeleton handler only
  1512. * (we do not want axis reading in interrupt handler - too much load!)
  1513. */
  1514. dev_dbg(chip->card->dev, "gameport irq\n");
  1515. /* this should ACK the gameport IRQ properly, hopefully. */
  1516. snd_azf3328_game_inw(chip, IDX_GAME_AXIS_VALUE);
  1517. }
  1518. static int
  1519. snd_azf3328_gameport_open(struct gameport *gameport, int mode)
  1520. {
  1521. struct snd_azf3328 *chip = gameport_get_port_data(gameport);
  1522. int res;
  1523. dev_dbg(chip->card->dev, "gameport_open, mode %d\n", mode);
  1524. switch (mode) {
  1525. case GAMEPORT_MODE_COOKED:
  1526. case GAMEPORT_MODE_RAW:
  1527. res = 0;
  1528. break;
  1529. default:
  1530. res = -1;
  1531. break;
  1532. }
  1533. snd_azf3328_gameport_set_counter_frequency(chip,
  1534. GAME_HWCFG_ADC_COUNTER_FREQ_STD);
  1535. snd_azf3328_gameport_axis_circuit_enable(chip, (res == 0));
  1536. return res;
  1537. }
  1538. static void
  1539. snd_azf3328_gameport_close(struct gameport *gameport)
  1540. {
  1541. struct snd_azf3328 *chip = gameport_get_port_data(gameport);
  1542. dev_dbg(chip->card->dev, "gameport_close\n");
  1543. snd_azf3328_gameport_set_counter_frequency(chip,
  1544. GAME_HWCFG_ADC_COUNTER_FREQ_1_200);
  1545. snd_azf3328_gameport_axis_circuit_enable(chip, 0);
  1546. }
  1547. static int
  1548. snd_azf3328_gameport_cooked_read(struct gameport *gameport,
  1549. int *axes,
  1550. int *buttons
  1551. )
  1552. {
  1553. struct snd_azf3328 *chip = gameport_get_port_data(gameport);
  1554. int i;
  1555. u8 val;
  1556. unsigned long flags;
  1557. if (snd_BUG_ON(!chip))
  1558. return 0;
  1559. spin_lock_irqsave(&chip->reg_lock, flags);
  1560. val = snd_azf3328_game_inb(chip, IDX_GAME_LEGACY_COMPATIBLE);
  1561. *buttons = (~(val) >> 4) & 0xf;
  1562. /* ok, this one is a bit dirty: cooked_read is being polled by a timer,
  1563. * thus we're atomic and cannot actively wait in here
  1564. * (which would be useful for us since it probably would be better
  1565. * to trigger a measurement in here, then wait a short amount of
  1566. * time until it's finished, then read values of _this_ measurement).
  1567. *
  1568. * Thus we simply resort to reading values if they're available already
  1569. * and trigger the next measurement.
  1570. */
  1571. val = snd_azf3328_game_inb(chip, IDX_GAME_AXES_CONFIG);
  1572. if (val & GAME_AXES_SAMPLING_READY) {
  1573. for (i = 0; i < ARRAY_SIZE(chip->axes); ++i) {
  1574. /* configure the axis to read */
  1575. val = (i << 4) | 0x0f;
  1576. snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val);
  1577. chip->axes[i] = snd_azf3328_game_inw(
  1578. chip, IDX_GAME_AXIS_VALUE
  1579. );
  1580. }
  1581. }
  1582. /* trigger next sampling of axes, to be evaluated the next time we
  1583. * enter this function */
  1584. /* for some very, very strange reason we cannot enable
  1585. * Measurement Ready monitoring for all axes here,
  1586. * at least not when only one joystick connected */
  1587. val = 0x03; /* we're able to monitor axes 1 and 2 only */
  1588. snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val);
  1589. snd_azf3328_game_outw(chip, IDX_GAME_AXIS_VALUE, 0xffff);
  1590. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1591. for (i = 0; i < ARRAY_SIZE(chip->axes); i++) {
  1592. axes[i] = chip->axes[i];
  1593. if (axes[i] == 0xffff)
  1594. axes[i] = -1;
  1595. }
  1596. dev_dbg(chip->card->dev, "cooked_read: axes %d %d %d %d buttons %d\n",
  1597. axes[0], axes[1], axes[2], axes[3], *buttons);
  1598. return 0;
  1599. }
  1600. static int
  1601. snd_azf3328_gameport(struct snd_azf3328 *chip, int dev)
  1602. {
  1603. struct gameport *gp;
  1604. chip->gameport = gp = gameport_allocate_port();
  1605. if (!gp) {
  1606. dev_err(chip->card->dev, "cannot alloc memory for gameport\n");
  1607. return -ENOMEM;
  1608. }
  1609. gameport_set_name(gp, "AZF3328 Gameport");
  1610. gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
  1611. gameport_set_dev_parent(gp, &chip->pci->dev);
  1612. gp->io = chip->game_io;
  1613. gameport_set_port_data(gp, chip);
  1614. gp->open = snd_azf3328_gameport_open;
  1615. gp->close = snd_azf3328_gameport_close;
  1616. gp->fuzz = 16; /* seems ok */
  1617. gp->cooked_read = snd_azf3328_gameport_cooked_read;
  1618. /* DISABLE legacy address: we don't need it! */
  1619. snd_azf3328_gameport_legacy_address_enable(chip, 0);
  1620. snd_azf3328_gameport_set_counter_frequency(chip,
  1621. GAME_HWCFG_ADC_COUNTER_FREQ_1_200);
  1622. snd_azf3328_gameport_axis_circuit_enable(chip, 0);
  1623. gameport_register_port(chip->gameport);
  1624. return 0;
  1625. }
  1626. static void
  1627. snd_azf3328_gameport_free(struct snd_azf3328 *chip)
  1628. {
  1629. if (chip->gameport) {
  1630. gameport_unregister_port(chip->gameport);
  1631. chip->gameport = NULL;
  1632. }
  1633. snd_azf3328_gameport_irq_enable(chip, 0);
  1634. }
  1635. #else
  1636. static inline int
  1637. snd_azf3328_gameport(struct snd_azf3328 *chip, int dev) { return -ENOSYS; }
  1638. static inline void
  1639. snd_azf3328_gameport_free(struct snd_azf3328 *chip) { }
  1640. static inline void
  1641. snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip)
  1642. {
  1643. dev_warn(chip->card->dev, "huh, game port IRQ occurred!?\n");
  1644. }
  1645. #endif /* SUPPORT_GAMEPORT */
  1646. /******************************************************************/
  1647. static inline void
  1648. snd_azf3328_irq_log_unknown_type(struct snd_azf3328 *chip, u8 which)
  1649. {
  1650. dev_dbg(chip->card->dev,
  1651. "unknown IRQ type (%x) occurred, please report!\n",
  1652. which);
  1653. }
  1654. static inline void
  1655. snd_azf3328_pcm_interrupt(struct snd_azf3328 *chip,
  1656. const struct snd_azf3328_codec_data *first_codec,
  1657. u8 status
  1658. )
  1659. {
  1660. u8 which;
  1661. enum snd_azf3328_codec_type codec_type;
  1662. const struct snd_azf3328_codec_data *codec = first_codec;
  1663. for (codec_type = AZF_CODEC_PLAYBACK;
  1664. codec_type <= AZF_CODEC_I2S_OUT;
  1665. ++codec_type, ++codec) {
  1666. /* skip codec if there's no interrupt for it */
  1667. if (!(status & (1 << codec_type)))
  1668. continue;
  1669. spin_lock(codec->lock);
  1670. which = snd_azf3328_codec_inb(codec, IDX_IO_CODEC_IRQTYPE);
  1671. /* ack all IRQ types immediately */
  1672. snd_azf3328_codec_outb(codec, IDX_IO_CODEC_IRQTYPE, which);
  1673. spin_unlock(codec->lock);
  1674. if (codec->substream) {
  1675. snd_pcm_period_elapsed(codec->substream);
  1676. dev_dbg(chip->card->dev, "%s period done (#%x), @ %x\n",
  1677. codec->name,
  1678. which,
  1679. snd_azf3328_codec_inl(
  1680. codec, IDX_IO_CODEC_DMA_CURRPOS));
  1681. } else
  1682. dev_warn(chip->card->dev, "irq handler problem!\n");
  1683. if (which & IRQ_SOMETHING)
  1684. snd_azf3328_irq_log_unknown_type(chip, which);
  1685. }
  1686. }
  1687. static irqreturn_t
  1688. snd_azf3328_interrupt(int irq, void *dev_id)
  1689. {
  1690. struct snd_azf3328 *chip = dev_id;
  1691. u8 status;
  1692. static unsigned long irq_count;
  1693. status = snd_azf3328_ctrl_inb(chip, IDX_IO_IRQSTATUS);
  1694. /* fast path out, to ease interrupt sharing */
  1695. if (!(status &
  1696. (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT
  1697. |IRQ_GAMEPORT|IRQ_MPU401|IRQ_TIMER)
  1698. ))
  1699. return IRQ_NONE; /* must be interrupt for another device */
  1700. dev_dbg(chip->card->dev,
  1701. "irq_count %ld! IDX_IO_IRQSTATUS %04x\n",
  1702. irq_count++ /* debug-only */,
  1703. status);
  1704. if (status & IRQ_TIMER) {
  1705. /* dev_dbg(chip->card->dev, "timer %ld\n",
  1706. snd_azf3328_codec_inl(chip, IDX_IO_TIMER_VALUE)
  1707. & TIMER_VALUE_MASK
  1708. ); */
  1709. if (chip->timer)
  1710. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  1711. /* ACK timer */
  1712. spin_lock(&chip->reg_lock);
  1713. snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x07);
  1714. spin_unlock(&chip->reg_lock);
  1715. dev_dbg(chip->card->dev, "timer IRQ\n");
  1716. }
  1717. if (status & (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT))
  1718. snd_azf3328_pcm_interrupt(chip, chip->codecs, status);
  1719. if (status & IRQ_GAMEPORT)
  1720. snd_azf3328_gameport_interrupt(chip);
  1721. /* MPU401 has less critical IRQ requirements
  1722. * than timer and playback/recording, right? */
  1723. if (status & IRQ_MPU401) {
  1724. snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
  1725. /* hmm, do we have to ack the IRQ here somehow?
  1726. * If so, then I don't know how yet... */
  1727. dev_dbg(chip->card->dev, "MPU401 IRQ\n");
  1728. }
  1729. return IRQ_HANDLED;
  1730. }
  1731. /*****************************************************************/
  1732. /* as long as we think we have identical snd_pcm_hardware parameters
  1733. for playback, capture and i2s out, we can use the same physical struct
  1734. since the struct is simply being copied into a member.
  1735. */
  1736. static const struct snd_pcm_hardware snd_azf3328_hardware =
  1737. {
  1738. /* FIXME!! Correct? */
  1739. .info = SNDRV_PCM_INFO_MMAP |
  1740. SNDRV_PCM_INFO_INTERLEAVED |
  1741. SNDRV_PCM_INFO_MMAP_VALID,
  1742. .formats = SNDRV_PCM_FMTBIT_S8 |
  1743. SNDRV_PCM_FMTBIT_U8 |
  1744. SNDRV_PCM_FMTBIT_S16_LE |
  1745. SNDRV_PCM_FMTBIT_U16_LE,
  1746. .rates = SNDRV_PCM_RATE_5512 |
  1747. SNDRV_PCM_RATE_8000_48000 |
  1748. SNDRV_PCM_RATE_KNOT,
  1749. .rate_min = AZF_FREQ_4000,
  1750. .rate_max = AZF_FREQ_66200,
  1751. .channels_min = 1,
  1752. .channels_max = 2,
  1753. .buffer_bytes_max = (64*1024),
  1754. .period_bytes_min = 1024,
  1755. .period_bytes_max = (32*1024),
  1756. /* We simply have two DMA areas (instead of a list of descriptors
  1757. such as other cards); I believe that this is a fixed hardware
  1758. attribute and there isn't much driver magic to be done to expand it.
  1759. Thus indicate that we have at least and at most 2 periods. */
  1760. .periods_min = 2,
  1761. .periods_max = 2,
  1762. /* FIXME: maybe that card actually has a FIFO?
  1763. * Hmm, it seems newer revisions do have one, but we still don't know
  1764. * its size... */
  1765. .fifo_size = 0,
  1766. };
  1767. static const unsigned int snd_azf3328_fixed_rates[] = {
  1768. AZF_FREQ_4000,
  1769. AZF_FREQ_4800,
  1770. AZF_FREQ_5512,
  1771. AZF_FREQ_6620,
  1772. AZF_FREQ_8000,
  1773. AZF_FREQ_9600,
  1774. AZF_FREQ_11025,
  1775. AZF_FREQ_13240,
  1776. AZF_FREQ_16000,
  1777. AZF_FREQ_22050,
  1778. AZF_FREQ_32000,
  1779. AZF_FREQ_44100,
  1780. AZF_FREQ_48000,
  1781. AZF_FREQ_66200
  1782. };
  1783. static const struct snd_pcm_hw_constraint_list snd_azf3328_hw_constraints_rates = {
  1784. .count = ARRAY_SIZE(snd_azf3328_fixed_rates),
  1785. .list = snd_azf3328_fixed_rates,
  1786. .mask = 0,
  1787. };
  1788. /*****************************************************************/
  1789. static int
  1790. snd_azf3328_pcm_open(struct snd_pcm_substream *substream,
  1791. enum snd_azf3328_codec_type codec_type
  1792. )
  1793. {
  1794. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1795. struct snd_pcm_runtime *runtime = substream->runtime;
  1796. struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type];
  1797. codec->substream = substream;
  1798. /* same parameters for all our codecs - at least we think so... */
  1799. runtime->hw = snd_azf3328_hardware;
  1800. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  1801. &snd_azf3328_hw_constraints_rates);
  1802. runtime->private_data = codec;
  1803. return 0;
  1804. }
  1805. static int
  1806. snd_azf3328_pcm_playback_open(struct snd_pcm_substream *substream)
  1807. {
  1808. return snd_azf3328_pcm_open(substream, AZF_CODEC_PLAYBACK);
  1809. }
  1810. static int
  1811. snd_azf3328_pcm_capture_open(struct snd_pcm_substream *substream)
  1812. {
  1813. return snd_azf3328_pcm_open(substream, AZF_CODEC_CAPTURE);
  1814. }
  1815. static int
  1816. snd_azf3328_pcm_i2s_out_open(struct snd_pcm_substream *substream)
  1817. {
  1818. return snd_azf3328_pcm_open(substream, AZF_CODEC_I2S_OUT);
  1819. }
  1820. static int
  1821. snd_azf3328_pcm_close(struct snd_pcm_substream *substream
  1822. )
  1823. {
  1824. struct snd_azf3328_codec_data *codec =
  1825. substream->runtime->private_data;
  1826. codec->substream = NULL;
  1827. return 0;
  1828. }
  1829. /******************************************************************/
  1830. static const struct snd_pcm_ops snd_azf3328_playback_ops = {
  1831. .open = snd_azf3328_pcm_playback_open,
  1832. .close = snd_azf3328_pcm_close,
  1833. .prepare = snd_azf3328_pcm_prepare,
  1834. .trigger = snd_azf3328_pcm_trigger,
  1835. .pointer = snd_azf3328_pcm_pointer
  1836. };
  1837. static const struct snd_pcm_ops snd_azf3328_capture_ops = {
  1838. .open = snd_azf3328_pcm_capture_open,
  1839. .close = snd_azf3328_pcm_close,
  1840. .prepare = snd_azf3328_pcm_prepare,
  1841. .trigger = snd_azf3328_pcm_trigger,
  1842. .pointer = snd_azf3328_pcm_pointer
  1843. };
  1844. static const struct snd_pcm_ops snd_azf3328_i2s_out_ops = {
  1845. .open = snd_azf3328_pcm_i2s_out_open,
  1846. .close = snd_azf3328_pcm_close,
  1847. .prepare = snd_azf3328_pcm_prepare,
  1848. .trigger = snd_azf3328_pcm_trigger,
  1849. .pointer = snd_azf3328_pcm_pointer
  1850. };
  1851. static int
  1852. snd_azf3328_pcm(struct snd_azf3328 *chip)
  1853. {
  1854. /* pcm devices */
  1855. enum { AZF_PCMDEV_STD, AZF_PCMDEV_I2S_OUT, NUM_AZF_PCMDEVS };
  1856. struct snd_pcm *pcm;
  1857. int err;
  1858. err = snd_pcm_new(chip->card, "AZF3328 DSP", AZF_PCMDEV_STD,
  1859. 1, 1, &pcm);
  1860. if (err < 0)
  1861. return err;
  1862. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1863. &snd_azf3328_playback_ops);
  1864. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  1865. &snd_azf3328_capture_ops);
  1866. pcm->private_data = chip;
  1867. pcm->info_flags = 0;
  1868. strcpy(pcm->name, chip->card->shortname);
  1869. /* same pcm object for playback/capture (see snd_pcm_new() above) */
  1870. chip->pcm[AZF_CODEC_PLAYBACK] = pcm;
  1871. chip->pcm[AZF_CODEC_CAPTURE] = pcm;
  1872. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
  1873. 64*1024, 64*1024);
  1874. err = snd_pcm_new(chip->card, "AZF3328 I2S OUT", AZF_PCMDEV_I2S_OUT,
  1875. 1, 0, &pcm);
  1876. if (err < 0)
  1877. return err;
  1878. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1879. &snd_azf3328_i2s_out_ops);
  1880. pcm->private_data = chip;
  1881. pcm->info_flags = 0;
  1882. strcpy(pcm->name, chip->card->shortname);
  1883. chip->pcm[AZF_CODEC_I2S_OUT] = pcm;
  1884. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
  1885. 64*1024, 64*1024);
  1886. return 0;
  1887. }
  1888. /******************************************************************/
  1889. /*** NOTE: the physical timer resolution actually is 1024000 ticks per second
  1890. *** (probably derived from main crystal via a divider of 24),
  1891. *** but announcing those attributes to user-space would make programs
  1892. *** configure the timer to a 1 tick value, resulting in an absolutely fatal
  1893. *** timer IRQ storm.
  1894. *** Thus I chose to announce a down-scaled virtual timer to the outside and
  1895. *** calculate real timer countdown values internally.
  1896. *** (the scale factor can be set via module parameter "seqtimer_scaling").
  1897. ***/
  1898. static int
  1899. snd_azf3328_timer_start(struct snd_timer *timer)
  1900. {
  1901. struct snd_azf3328 *chip;
  1902. unsigned long flags;
  1903. unsigned int delay;
  1904. chip = snd_timer_chip(timer);
  1905. delay = ((timer->sticks * seqtimer_scaling) - 1) & TIMER_VALUE_MASK;
  1906. if (delay < 49) {
  1907. /* uhoh, that's not good, since user-space won't know about
  1908. * this timing tweak
  1909. * (we need to do it to avoid a lockup, though) */
  1910. dev_dbg(chip->card->dev, "delay was too low (%d)!\n", delay);
  1911. delay = 49; /* minimum time is 49 ticks */
  1912. }
  1913. dev_dbg(chip->card->dev, "setting timer countdown value %d\n", delay);
  1914. delay |= TIMER_COUNTDOWN_ENABLE | TIMER_IRQ_ENABLE;
  1915. spin_lock_irqsave(&chip->reg_lock, flags);
  1916. snd_azf3328_ctrl_outl(chip, IDX_IO_TIMER_VALUE, delay);
  1917. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1918. return 0;
  1919. }
  1920. static int
  1921. snd_azf3328_timer_stop(struct snd_timer *timer)
  1922. {
  1923. struct snd_azf3328 *chip;
  1924. unsigned long flags;
  1925. chip = snd_timer_chip(timer);
  1926. spin_lock_irqsave(&chip->reg_lock, flags);
  1927. /* disable timer countdown and interrupt */
  1928. /* Hmm, should we write TIMER_IRQ_ACK here?
  1929. YES indeed, otherwise a rogue timer operation - which prompts
  1930. ALSA(?) to call repeated stop() in vain, but NOT start() -
  1931. will never end (value 0x03 is kept shown in control byte).
  1932. Simply manually poking 0x04 _once_ immediately successfully stops
  1933. the hardware/ALSA interrupt activity. */
  1934. snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x04);
  1935. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1936. return 0;
  1937. }
  1938. static int
  1939. snd_azf3328_timer_precise_resolution(struct snd_timer *timer,
  1940. unsigned long *num, unsigned long *den)
  1941. {
  1942. *num = 1;
  1943. *den = 1024000 / seqtimer_scaling;
  1944. return 0;
  1945. }
  1946. static struct snd_timer_hardware snd_azf3328_timer_hw = {
  1947. .flags = SNDRV_TIMER_HW_AUTO,
  1948. .resolution = 977, /* 1000000/1024000 = 0.9765625us */
  1949. .ticks = 1024000, /* max tick count, defined by the value register; actually it's not 1024000, but 1048576, but we don't care */
  1950. .start = snd_azf3328_timer_start,
  1951. .stop = snd_azf3328_timer_stop,
  1952. .precise_resolution = snd_azf3328_timer_precise_resolution,
  1953. };
  1954. static int
  1955. snd_azf3328_timer(struct snd_azf3328 *chip, int device)
  1956. {
  1957. struct snd_timer *timer = NULL;
  1958. struct snd_timer_id tid;
  1959. int err;
  1960. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1961. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1962. tid.card = chip->card->number;
  1963. tid.device = device;
  1964. tid.subdevice = 0;
  1965. snd_azf3328_timer_hw.resolution *= seqtimer_scaling;
  1966. snd_azf3328_timer_hw.ticks /= seqtimer_scaling;
  1967. err = snd_timer_new(chip->card, "AZF3328", &tid, &timer);
  1968. if (err < 0)
  1969. goto out;
  1970. strcpy(timer->name, "AZF3328 timer");
  1971. timer->private_data = chip;
  1972. timer->hw = snd_azf3328_timer_hw;
  1973. chip->timer = timer;
  1974. snd_azf3328_timer_stop(timer);
  1975. err = 0;
  1976. out:
  1977. return err;
  1978. }
  1979. /******************************************************************/
  1980. static int
  1981. snd_azf3328_free(struct snd_azf3328 *chip)
  1982. {
  1983. if (chip->irq < 0)
  1984. goto __end_hw;
  1985. snd_azf3328_mixer_reset(chip);
  1986. snd_azf3328_timer_stop(chip->timer);
  1987. snd_azf3328_gameport_free(chip);
  1988. __end_hw:
  1989. if (chip->irq >= 0)
  1990. free_irq(chip->irq, chip);
  1991. pci_release_regions(chip->pci);
  1992. pci_disable_device(chip->pci);
  1993. kfree(chip);
  1994. return 0;
  1995. }
  1996. static int
  1997. snd_azf3328_dev_free(struct snd_device *device)
  1998. {
  1999. struct snd_azf3328 *chip = device->device_data;
  2000. return snd_azf3328_free(chip);
  2001. }
  2002. #if 0
  2003. /* check whether a bit can be modified */
  2004. static void
  2005. snd_azf3328_test_bit(unsigned unsigned reg, int bit)
  2006. {
  2007. unsigned char val, valoff, valon;
  2008. val = inb(reg);
  2009. outb(val & ~(1 << bit), reg);
  2010. valoff = inb(reg);
  2011. outb(val|(1 << bit), reg);
  2012. valon = inb(reg);
  2013. outb(val, reg);
  2014. printk(KERN_DEBUG "reg %04x bit %d: %02x %02x %02x\n",
  2015. reg, bit, val, valoff, valon
  2016. );
  2017. }
  2018. #endif
  2019. static inline void
  2020. snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip)
  2021. {
  2022. u16 tmp;
  2023. dev_dbg(chip->card->dev,
  2024. "ctrl_io 0x%lx, game_io 0x%lx, mpu_io 0x%lx, "
  2025. "opl3_io 0x%lx, mixer_io 0x%lx, irq %d\n",
  2026. chip->ctrl_io, chip->game_io, chip->mpu_io,
  2027. chip->opl3_io, chip->mixer_io, chip->irq);
  2028. dev_dbg(chip->card->dev,
  2029. "game %02x %02x %02x %02x %02x %02x\n",
  2030. snd_azf3328_game_inb(chip, 0),
  2031. snd_azf3328_game_inb(chip, 1),
  2032. snd_azf3328_game_inb(chip, 2),
  2033. snd_azf3328_game_inb(chip, 3),
  2034. snd_azf3328_game_inb(chip, 4),
  2035. snd_azf3328_game_inb(chip, 5));
  2036. for (tmp = 0; tmp < 0x07; tmp += 1)
  2037. dev_dbg(chip->card->dev,
  2038. "mpu_io 0x%04x\n", inb(chip->mpu_io + tmp));
  2039. for (tmp = 0; tmp <= 0x07; tmp += 1)
  2040. dev_dbg(chip->card->dev,
  2041. "0x%02x: game200 0x%04x, game208 0x%04x\n",
  2042. tmp, inb(0x200 + tmp), inb(0x208 + tmp));
  2043. for (tmp = 0; tmp <= 0x01; tmp += 1)
  2044. dev_dbg(chip->card->dev,
  2045. "0x%02x: mpu300 0x%04x, mpu310 0x%04x, mpu320 0x%04x, "
  2046. "mpu330 0x%04x opl388 0x%04x opl38c 0x%04x\n",
  2047. tmp,
  2048. inb(0x300 + tmp),
  2049. inb(0x310 + tmp),
  2050. inb(0x320 + tmp),
  2051. inb(0x330 + tmp),
  2052. inb(0x388 + tmp),
  2053. inb(0x38c + tmp));
  2054. for (tmp = 0; tmp < AZF_IO_SIZE_CTRL; tmp += 2)
  2055. dev_dbg(chip->card->dev,
  2056. "ctrl 0x%02x: 0x%04x\n",
  2057. tmp, snd_azf3328_ctrl_inw(chip, tmp));
  2058. for (tmp = 0; tmp < AZF_IO_SIZE_MIXER; tmp += 2)
  2059. dev_dbg(chip->card->dev,
  2060. "mixer 0x%02x: 0x%04x\n",
  2061. tmp, snd_azf3328_mixer_inw(chip, tmp));
  2062. }
  2063. static int
  2064. snd_azf3328_create(struct snd_card *card,
  2065. struct pci_dev *pci,
  2066. unsigned long device_type,
  2067. struct snd_azf3328 **rchip)
  2068. {
  2069. struct snd_azf3328 *chip;
  2070. int err;
  2071. static const struct snd_device_ops ops = {
  2072. .dev_free = snd_azf3328_dev_free,
  2073. };
  2074. u8 dma_init;
  2075. enum snd_azf3328_codec_type codec_type;
  2076. struct snd_azf3328_codec_data *codec_setup;
  2077. *rchip = NULL;
  2078. err = pci_enable_device(pci);
  2079. if (err < 0)
  2080. return err;
  2081. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  2082. if (chip == NULL) {
  2083. err = -ENOMEM;
  2084. goto out_err;
  2085. }
  2086. spin_lock_init(&chip->reg_lock);
  2087. chip->card = card;
  2088. chip->pci = pci;
  2089. chip->irq = -1;
  2090. /* check if we can restrict PCI DMA transfers to 24 bits */
  2091. if (dma_set_mask(&pci->dev, DMA_BIT_MASK(24)) < 0 ||
  2092. dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(24)) < 0) {
  2093. dev_err(card->dev,
  2094. "architecture does not support 24bit PCI busmaster DMA\n"
  2095. );
  2096. err = -ENXIO;
  2097. goto out_err;
  2098. }
  2099. err = pci_request_regions(pci, "Aztech AZF3328");
  2100. if (err < 0)
  2101. goto out_err;
  2102. chip->ctrl_io = pci_resource_start(pci, 0);
  2103. chip->game_io = pci_resource_start(pci, 1);
  2104. chip->mpu_io = pci_resource_start(pci, 2);
  2105. chip->opl3_io = pci_resource_start(pci, 3);
  2106. chip->mixer_io = pci_resource_start(pci, 4);
  2107. codec_setup = &chip->codecs[AZF_CODEC_PLAYBACK];
  2108. codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_PLAYBACK;
  2109. codec_setup->lock = &chip->reg_lock;
  2110. codec_setup->type = AZF_CODEC_PLAYBACK;
  2111. codec_setup->name = "PLAYBACK";
  2112. codec_setup = &chip->codecs[AZF_CODEC_CAPTURE];
  2113. codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_CAPTURE;
  2114. codec_setup->lock = &chip->reg_lock;
  2115. codec_setup->type = AZF_CODEC_CAPTURE;
  2116. codec_setup->name = "CAPTURE";
  2117. codec_setup = &chip->codecs[AZF_CODEC_I2S_OUT];
  2118. codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_I2S_OUT;
  2119. codec_setup->lock = &chip->reg_lock;
  2120. codec_setup->type = AZF_CODEC_I2S_OUT;
  2121. codec_setup->name = "I2S_OUT";
  2122. if (request_irq(pci->irq, snd_azf3328_interrupt,
  2123. IRQF_SHARED, KBUILD_MODNAME, chip)) {
  2124. dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
  2125. err = -EBUSY;
  2126. goto out_err;
  2127. }
  2128. chip->irq = pci->irq;
  2129. card->sync_irq = chip->irq;
  2130. pci_set_master(pci);
  2131. snd_azf3328_debug_show_ports(chip);
  2132. err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
  2133. if (err < 0)
  2134. goto out_err;
  2135. /* create mixer interface & switches */
  2136. err = snd_azf3328_mixer_new(chip);
  2137. if (err < 0)
  2138. goto out_err;
  2139. /* standard codec init stuff */
  2140. /* default DMA init value */
  2141. dma_init = DMA_RUN_SOMETHING2|DMA_EPILOGUE_SOMETHING|DMA_SOMETHING_ELSE;
  2142. for (codec_type = AZF_CODEC_PLAYBACK;
  2143. codec_type <= AZF_CODEC_I2S_OUT; ++codec_type) {
  2144. struct snd_azf3328_codec_data *codec =
  2145. &chip->codecs[codec_type];
  2146. /* shutdown codecs to reduce power / noise */
  2147. /* have ...ctrl_codec_activity() act properly */
  2148. codec->running = 1;
  2149. snd_azf3328_ctrl_codec_activity(chip, codec_type, 0);
  2150. spin_lock_irq(codec->lock);
  2151. snd_azf3328_codec_outb(codec, IDX_IO_CODEC_DMA_FLAGS,
  2152. dma_init);
  2153. spin_unlock_irq(codec->lock);
  2154. }
  2155. *rchip = chip;
  2156. err = 0;
  2157. goto out;
  2158. out_err:
  2159. if (chip)
  2160. snd_azf3328_free(chip);
  2161. pci_disable_device(pci);
  2162. out:
  2163. return err;
  2164. }
  2165. static int
  2166. snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
  2167. {
  2168. static int dev;
  2169. struct snd_card *card;
  2170. struct snd_azf3328 *chip;
  2171. struct snd_opl3 *opl3;
  2172. int err;
  2173. if (dev >= SNDRV_CARDS) {
  2174. err = -ENODEV;
  2175. goto out;
  2176. }
  2177. if (!enable[dev]) {
  2178. dev++;
  2179. err = -ENOENT;
  2180. goto out;
  2181. }
  2182. err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
  2183. 0, &card);
  2184. if (err < 0)
  2185. goto out;
  2186. strcpy(card->driver, "AZF3328");
  2187. strcpy(card->shortname, "Aztech AZF3328 (PCI168)");
  2188. err = snd_azf3328_create(card, pci, pci_id->driver_data, &chip);
  2189. if (err < 0)
  2190. goto out_err;
  2191. card->private_data = chip;
  2192. /* chose to use MPU401_HW_AZT2320 ID instead of MPU401_HW_MPU401,
  2193. since our hardware ought to be similar, thus use same ID. */
  2194. err = snd_mpu401_uart_new(
  2195. card, 0,
  2196. MPU401_HW_AZT2320, chip->mpu_io,
  2197. MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
  2198. -1, &chip->rmidi
  2199. );
  2200. if (err < 0) {
  2201. dev_err(card->dev, "no MPU-401 device at 0x%lx?\n",
  2202. chip->mpu_io
  2203. );
  2204. goto out_err;
  2205. }
  2206. err = snd_azf3328_timer(chip, 0);
  2207. if (err < 0)
  2208. goto out_err;
  2209. err = snd_azf3328_pcm(chip);
  2210. if (err < 0)
  2211. goto out_err;
  2212. if (snd_opl3_create(card, chip->opl3_io, chip->opl3_io+2,
  2213. OPL3_HW_AUTO, 1, &opl3) < 0) {
  2214. dev_err(card->dev, "no OPL3 device at 0x%lx-0x%lx?\n",
  2215. chip->opl3_io, chip->opl3_io+2
  2216. );
  2217. } else {
  2218. /* need to use IDs 1, 2 since ID 0 is snd_azf3328_timer above */
  2219. err = snd_opl3_timer_new(opl3, 1, 2);
  2220. if (err < 0)
  2221. goto out_err;
  2222. err = snd_opl3_hwdep_new(opl3, 0, 1, NULL);
  2223. if (err < 0)
  2224. goto out_err;
  2225. opl3->private_data = chip;
  2226. }
  2227. sprintf(card->longname, "%s at 0x%lx, irq %i",
  2228. card->shortname, chip->ctrl_io, chip->irq);
  2229. err = snd_card_register(card);
  2230. if (err < 0)
  2231. goto out_err;
  2232. #ifdef MODULE
  2233. dev_info(card->dev,
  2234. "Sound driver for Aztech AZF3328-based soundcards such as PCI168.\n");
  2235. dev_info(card->dev,
  2236. "Hardware was completely undocumented, unfortunately.\n");
  2237. dev_info(card->dev,
  2238. "Feel free to contact andi AT lisas.de for bug reports etc.!\n");
  2239. dev_info(card->dev,
  2240. "User-scalable sequencer timer set to %dHz (1024000Hz / %d).\n",
  2241. 1024000 / seqtimer_scaling, seqtimer_scaling);
  2242. #endif
  2243. snd_azf3328_gameport(chip, dev);
  2244. pci_set_drvdata(pci, card);
  2245. dev++;
  2246. err = 0;
  2247. goto out;
  2248. out_err:
  2249. dev_err(card->dev, "something failed, exiting\n");
  2250. snd_card_free(card);
  2251. out:
  2252. return err;
  2253. }
  2254. static void
  2255. snd_azf3328_remove(struct pci_dev *pci)
  2256. {
  2257. snd_card_free(pci_get_drvdata(pci));
  2258. }
  2259. #ifdef CONFIG_PM_SLEEP
  2260. static inline void
  2261. snd_azf3328_suspend_regs(const struct snd_azf3328 *chip,
  2262. unsigned long io_addr, unsigned count, u32 *saved_regs)
  2263. {
  2264. unsigned reg;
  2265. for (reg = 0; reg < count; ++reg) {
  2266. *saved_regs = inl(io_addr);
  2267. dev_dbg(chip->card->dev, "suspend: io 0x%04lx: 0x%08x\n",
  2268. io_addr, *saved_regs);
  2269. ++saved_regs;
  2270. io_addr += sizeof(*saved_regs);
  2271. }
  2272. }
  2273. static inline void
  2274. snd_azf3328_resume_regs(const struct snd_azf3328 *chip,
  2275. const u32 *saved_regs,
  2276. unsigned long io_addr,
  2277. unsigned count
  2278. )
  2279. {
  2280. unsigned reg;
  2281. for (reg = 0; reg < count; ++reg) {
  2282. outl(*saved_regs, io_addr);
  2283. dev_dbg(chip->card->dev,
  2284. "resume: io 0x%04lx: 0x%08x --> 0x%08x\n",
  2285. io_addr, *saved_regs, inl(io_addr));
  2286. ++saved_regs;
  2287. io_addr += sizeof(*saved_regs);
  2288. }
  2289. }
  2290. static inline void
  2291. snd_azf3328_suspend_ac97(struct snd_azf3328 *chip)
  2292. {
  2293. #ifdef AZF_USE_AC97_LAYER
  2294. snd_ac97_suspend(chip->ac97);
  2295. #else
  2296. snd_azf3328_suspend_regs(chip, chip->mixer_io,
  2297. ARRAY_SIZE(chip->saved_regs_mixer), chip->saved_regs_mixer);
  2298. /* make sure to disable master volume etc. to prevent looping sound */
  2299. snd_azf3328_mixer_mute_control_master(chip, 1);
  2300. snd_azf3328_mixer_mute_control_pcm(chip, 1);
  2301. #endif /* AZF_USE_AC97_LAYER */
  2302. }
  2303. static inline void
  2304. snd_azf3328_resume_ac97(const struct snd_azf3328 *chip)
  2305. {
  2306. #ifdef AZF_USE_AC97_LAYER
  2307. snd_ac97_resume(chip->ac97);
  2308. #else
  2309. snd_azf3328_resume_regs(chip, chip->saved_regs_mixer, chip->mixer_io,
  2310. ARRAY_SIZE(chip->saved_regs_mixer));
  2311. /* unfortunately with 32bit transfers, IDX_MIXER_PLAY_MASTER (0x02)
  2312. and IDX_MIXER_RESET (offset 0x00) get touched at the same time,
  2313. resulting in a mixer reset condition persisting until _after_
  2314. master vol was restored. Thus master vol needs an extra restore. */
  2315. outw(((u16 *)chip->saved_regs_mixer)[1], chip->mixer_io + 2);
  2316. #endif /* AZF_USE_AC97_LAYER */
  2317. }
  2318. static int
  2319. snd_azf3328_suspend(struct device *dev)
  2320. {
  2321. struct snd_card *card = dev_get_drvdata(dev);
  2322. struct snd_azf3328 *chip = card->private_data;
  2323. u16 *saved_regs_ctrl_u16;
  2324. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  2325. snd_azf3328_suspend_ac97(chip);
  2326. snd_azf3328_suspend_regs(chip, chip->ctrl_io,
  2327. ARRAY_SIZE(chip->saved_regs_ctrl), chip->saved_regs_ctrl);
  2328. /* manually store the one currently relevant write-only reg, too */
  2329. saved_regs_ctrl_u16 = (u16 *)chip->saved_regs_ctrl;
  2330. saved_regs_ctrl_u16[IDX_IO_6AH / 2] = chip->shadow_reg_ctrl_6AH;
  2331. snd_azf3328_suspend_regs(chip, chip->game_io,
  2332. ARRAY_SIZE(chip->saved_regs_game), chip->saved_regs_game);
  2333. snd_azf3328_suspend_regs(chip, chip->mpu_io,
  2334. ARRAY_SIZE(chip->saved_regs_mpu), chip->saved_regs_mpu);
  2335. snd_azf3328_suspend_regs(chip, chip->opl3_io,
  2336. ARRAY_SIZE(chip->saved_regs_opl3), chip->saved_regs_opl3);
  2337. return 0;
  2338. }
  2339. static int
  2340. snd_azf3328_resume(struct device *dev)
  2341. {
  2342. struct snd_card *card = dev_get_drvdata(dev);
  2343. const struct snd_azf3328 *chip = card->private_data;
  2344. snd_azf3328_resume_regs(chip, chip->saved_regs_game, chip->game_io,
  2345. ARRAY_SIZE(chip->saved_regs_game));
  2346. snd_azf3328_resume_regs(chip, chip->saved_regs_mpu, chip->mpu_io,
  2347. ARRAY_SIZE(chip->saved_regs_mpu));
  2348. snd_azf3328_resume_regs(chip, chip->saved_regs_opl3, chip->opl3_io,
  2349. ARRAY_SIZE(chip->saved_regs_opl3));
  2350. snd_azf3328_resume_ac97(chip);
  2351. snd_azf3328_resume_regs(chip, chip->saved_regs_ctrl, chip->ctrl_io,
  2352. ARRAY_SIZE(chip->saved_regs_ctrl));
  2353. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  2354. return 0;
  2355. }
  2356. static SIMPLE_DEV_PM_OPS(snd_azf3328_pm, snd_azf3328_suspend, snd_azf3328_resume);
  2357. #define SND_AZF3328_PM_OPS &snd_azf3328_pm
  2358. #else
  2359. #define SND_AZF3328_PM_OPS NULL
  2360. #endif /* CONFIG_PM_SLEEP */
  2361. static struct pci_driver azf3328_driver = {
  2362. .name = KBUILD_MODNAME,
  2363. .id_table = snd_azf3328_ids,
  2364. .probe = snd_azf3328_probe,
  2365. .remove = snd_azf3328_remove,
  2366. .driver = {
  2367. .pm = SND_AZF3328_PM_OPS,
  2368. },
  2369. };
  2370. module_pci_driver(azf3328_driver);