atiixp.c 44 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * ALSA driver for ATI IXP 150/200/250/300 AC97 controllers
  4. *
  5. * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  6. */
  7. #include <linux/io.h>
  8. #include <linux/delay.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/init.h>
  11. #include <linux/pci.h>
  12. #include <linux/slab.h>
  13. #include <linux/module.h>
  14. #include <linux/mutex.h>
  15. #include <sound/core.h>
  16. #include <sound/pcm.h>
  17. #include <sound/pcm_params.h>
  18. #include <sound/info.h>
  19. #include <sound/ac97_codec.h>
  20. #include <sound/initval.h>
  21. MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
  22. MODULE_DESCRIPTION("ATI IXP AC97 controller");
  23. MODULE_LICENSE("GPL");
  24. MODULE_SUPPORTED_DEVICE("{{ATI,IXP150/200/250/300/400/600}}");
  25. static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
  26. static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
  27. static int ac97_clock = 48000;
  28. static char *ac97_quirk;
  29. static bool spdif_aclink = 1;
  30. static int ac97_codec = -1;
  31. module_param(index, int, 0444);
  32. MODULE_PARM_DESC(index, "Index value for ATI IXP controller.");
  33. module_param(id, charp, 0444);
  34. MODULE_PARM_DESC(id, "ID string for ATI IXP controller.");
  35. module_param(ac97_clock, int, 0444);
  36. MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz).");
  37. module_param(ac97_quirk, charp, 0444);
  38. MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
  39. module_param(ac97_codec, int, 0444);
  40. MODULE_PARM_DESC(ac97_codec, "Specify codec instead of probing.");
  41. module_param(spdif_aclink, bool, 0444);
  42. MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
  43. /* just for backward compatibility */
  44. static bool enable;
  45. module_param(enable, bool, 0444);
  46. /*
  47. */
  48. #define ATI_REG_ISR 0x00 /* interrupt source */
  49. #define ATI_REG_ISR_IN_XRUN (1U<<0)
  50. #define ATI_REG_ISR_IN_STATUS (1U<<1)
  51. #define ATI_REG_ISR_OUT_XRUN (1U<<2)
  52. #define ATI_REG_ISR_OUT_STATUS (1U<<3)
  53. #define ATI_REG_ISR_SPDF_XRUN (1U<<4)
  54. #define ATI_REG_ISR_SPDF_STATUS (1U<<5)
  55. #define ATI_REG_ISR_PHYS_INTR (1U<<8)
  56. #define ATI_REG_ISR_PHYS_MISMATCH (1U<<9)
  57. #define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10)
  58. #define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11)
  59. #define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12)
  60. #define ATI_REG_ISR_NEW_FRAME (1U<<13)
  61. #define ATI_REG_IER 0x04 /* interrupt enable */
  62. #define ATI_REG_IER_IN_XRUN_EN (1U<<0)
  63. #define ATI_REG_IER_IO_STATUS_EN (1U<<1)
  64. #define ATI_REG_IER_OUT_XRUN_EN (1U<<2)
  65. #define ATI_REG_IER_OUT_XRUN_COND (1U<<3)
  66. #define ATI_REG_IER_SPDF_XRUN_EN (1U<<4)
  67. #define ATI_REG_IER_SPDF_STATUS_EN (1U<<5)
  68. #define ATI_REG_IER_PHYS_INTR_EN (1U<<8)
  69. #define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9)
  70. #define ATI_REG_IER_CODEC0_INTR_EN (1U<<10)
  71. #define ATI_REG_IER_CODEC1_INTR_EN (1U<<11)
  72. #define ATI_REG_IER_CODEC2_INTR_EN (1U<<12)
  73. #define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO */
  74. #define ATI_REG_IER_SET_BUS_BUSY (1U<<14) /* (WO) audio is running */
  75. #define ATI_REG_CMD 0x08 /* command */
  76. #define ATI_REG_CMD_POWERDOWN (1U<<0)
  77. #define ATI_REG_CMD_RECEIVE_EN (1U<<1)
  78. #define ATI_REG_CMD_SEND_EN (1U<<2)
  79. #define ATI_REG_CMD_STATUS_MEM (1U<<3)
  80. #define ATI_REG_CMD_SPDF_OUT_EN (1U<<4)
  81. #define ATI_REG_CMD_SPDF_STATUS_MEM (1U<<5)
  82. #define ATI_REG_CMD_SPDF_THRESHOLD (3U<<6)
  83. #define ATI_REG_CMD_SPDF_THRESHOLD_SHIFT 6
  84. #define ATI_REG_CMD_IN_DMA_EN (1U<<8)
  85. #define ATI_REG_CMD_OUT_DMA_EN (1U<<9)
  86. #define ATI_REG_CMD_SPDF_DMA_EN (1U<<10)
  87. #define ATI_REG_CMD_SPDF_OUT_STOPPED (1U<<11)
  88. #define ATI_REG_CMD_SPDF_CONFIG_MASK (7U<<12)
  89. #define ATI_REG_CMD_SPDF_CONFIG_34 (1U<<12)
  90. #define ATI_REG_CMD_SPDF_CONFIG_78 (2U<<12)
  91. #define ATI_REG_CMD_SPDF_CONFIG_69 (3U<<12)
  92. #define ATI_REG_CMD_SPDF_CONFIG_01 (4U<<12)
  93. #define ATI_REG_CMD_INTERLEAVE_SPDF (1U<<16)
  94. #define ATI_REG_CMD_AUDIO_PRESENT (1U<<20)
  95. #define ATI_REG_CMD_INTERLEAVE_IN (1U<<21)
  96. #define ATI_REG_CMD_INTERLEAVE_OUT (1U<<22)
  97. #define ATI_REG_CMD_LOOPBACK_EN (1U<<23)
  98. #define ATI_REG_CMD_PACKED_DIS (1U<<24)
  99. #define ATI_REG_CMD_BURST_EN (1U<<25)
  100. #define ATI_REG_CMD_PANIC_EN (1U<<26)
  101. #define ATI_REG_CMD_MODEM_PRESENT (1U<<27)
  102. #define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28)
  103. #define ATI_REG_CMD_AC_SOFT_RESET (1U<<29)
  104. #define ATI_REG_CMD_AC_SYNC (1U<<30)
  105. #define ATI_REG_CMD_AC_RESET (1U<<31)
  106. #define ATI_REG_PHYS_OUT_ADDR 0x0c
  107. #define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0)
  108. #define ATI_REG_PHYS_OUT_RW (1U<<2)
  109. #define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8)
  110. #define ATI_REG_PHYS_OUT_ADDR_SHIFT 9
  111. #define ATI_REG_PHYS_OUT_DATA_SHIFT 16
  112. #define ATI_REG_PHYS_IN_ADDR 0x10
  113. #define ATI_REG_PHYS_IN_READ_FLAG (1U<<8)
  114. #define ATI_REG_PHYS_IN_ADDR_SHIFT 9
  115. #define ATI_REG_PHYS_IN_DATA_SHIFT 16
  116. #define ATI_REG_SLOTREQ 0x14
  117. #define ATI_REG_COUNTER 0x18
  118. #define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */
  119. #define ATI_REG_COUNTER_BITCLOCK (31U<<8)
  120. #define ATI_REG_IN_FIFO_THRESHOLD 0x1c
  121. #define ATI_REG_IN_DMA_LINKPTR 0x20
  122. #define ATI_REG_IN_DMA_DT_START 0x24 /* RO */
  123. #define ATI_REG_IN_DMA_DT_NEXT 0x28 /* RO */
  124. #define ATI_REG_IN_DMA_DT_CUR 0x2c /* RO */
  125. #define ATI_REG_IN_DMA_DT_SIZE 0x30
  126. #define ATI_REG_OUT_DMA_SLOT 0x34
  127. #define ATI_REG_OUT_DMA_SLOT_BIT(x) (1U << ((x) - 3))
  128. #define ATI_REG_OUT_DMA_SLOT_MASK 0x1ff
  129. #define ATI_REG_OUT_DMA_THRESHOLD_MASK 0xf800
  130. #define ATI_REG_OUT_DMA_THRESHOLD_SHIFT 11
  131. #define ATI_REG_OUT_DMA_LINKPTR 0x38
  132. #define ATI_REG_OUT_DMA_DT_START 0x3c /* RO */
  133. #define ATI_REG_OUT_DMA_DT_NEXT 0x40 /* RO */
  134. #define ATI_REG_OUT_DMA_DT_CUR 0x44 /* RO */
  135. #define ATI_REG_OUT_DMA_DT_SIZE 0x48
  136. #define ATI_REG_SPDF_CMD 0x4c
  137. #define ATI_REG_SPDF_CMD_LFSR (1U<<4)
  138. #define ATI_REG_SPDF_CMD_SINGLE_CH (1U<<5)
  139. #define ATI_REG_SPDF_CMD_LFSR_ACC (0xff<<8) /* RO */
  140. #define ATI_REG_SPDF_DMA_LINKPTR 0x50
  141. #define ATI_REG_SPDF_DMA_DT_START 0x54 /* RO */
  142. #define ATI_REG_SPDF_DMA_DT_NEXT 0x58 /* RO */
  143. #define ATI_REG_SPDF_DMA_DT_CUR 0x5c /* RO */
  144. #define ATI_REG_SPDF_DMA_DT_SIZE 0x60
  145. #define ATI_REG_MODEM_MIRROR 0x7c
  146. #define ATI_REG_AUDIO_MIRROR 0x80
  147. #define ATI_REG_6CH_REORDER 0x84 /* reorder slots for 6ch */
  148. #define ATI_REG_6CH_REORDER_EN (1U<<0) /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */
  149. #define ATI_REG_FIFO_FLUSH 0x88
  150. #define ATI_REG_FIFO_OUT_FLUSH (1U<<0)
  151. #define ATI_REG_FIFO_IN_FLUSH (1U<<1)
  152. /* LINKPTR */
  153. #define ATI_REG_LINKPTR_EN (1U<<0)
  154. /* [INT|OUT|SPDIF]_DMA_DT_SIZE */
  155. #define ATI_REG_DMA_DT_SIZE (0xffffU<<0)
  156. #define ATI_REG_DMA_FIFO_USED (0x1fU<<16)
  157. #define ATI_REG_DMA_FIFO_FREE (0x1fU<<21)
  158. #define ATI_REG_DMA_STATE (7U<<26)
  159. #define ATI_MAX_DESCRIPTORS 256 /* max number of descriptor packets */
  160. struct atiixp;
  161. /*
  162. * DMA packate descriptor
  163. */
  164. struct atiixp_dma_desc {
  165. __le32 addr; /* DMA buffer address */
  166. u16 status; /* status bits */
  167. u16 size; /* size of the packet in dwords */
  168. __le32 next; /* address of the next packet descriptor */
  169. };
  170. /*
  171. * stream enum
  172. */
  173. enum { ATI_DMA_PLAYBACK, ATI_DMA_CAPTURE, ATI_DMA_SPDIF, NUM_ATI_DMAS }; /* DMAs */
  174. enum { ATI_PCM_OUT, ATI_PCM_IN, ATI_PCM_SPDIF, NUM_ATI_PCMS }; /* AC97 pcm slots */
  175. enum { ATI_PCMDEV_ANALOG, ATI_PCMDEV_DIGITAL, NUM_ATI_PCMDEVS }; /* pcm devices */
  176. #define NUM_ATI_CODECS 3
  177. /*
  178. * constants and callbacks for each DMA type
  179. */
  180. struct atiixp_dma_ops {
  181. int type; /* ATI_DMA_XXX */
  182. unsigned int llp_offset; /* LINKPTR offset */
  183. unsigned int dt_cur; /* DT_CUR offset */
  184. /* called from open callback */
  185. void (*enable_dma)(struct atiixp *chip, int on);
  186. /* called from trigger (START/STOP) */
  187. void (*enable_transfer)(struct atiixp *chip, int on);
  188. /* called from trigger (STOP only) */
  189. void (*flush_dma)(struct atiixp *chip);
  190. };
  191. /*
  192. * DMA stream
  193. */
  194. struct atiixp_dma {
  195. const struct atiixp_dma_ops *ops;
  196. struct snd_dma_buffer desc_buf;
  197. struct snd_pcm_substream *substream; /* assigned PCM substream */
  198. unsigned int buf_addr, buf_bytes; /* DMA buffer address, bytes */
  199. unsigned int period_bytes, periods;
  200. int opened;
  201. int running;
  202. int suspended;
  203. int pcm_open_flag;
  204. int ac97_pcm_type; /* index # of ac97_pcm to access, -1 = not used */
  205. unsigned int saved_curptr;
  206. };
  207. /*
  208. * ATI IXP chip
  209. */
  210. struct atiixp {
  211. struct snd_card *card;
  212. struct pci_dev *pci;
  213. unsigned long addr;
  214. void __iomem *remap_addr;
  215. int irq;
  216. struct snd_ac97_bus *ac97_bus;
  217. struct snd_ac97 *ac97[NUM_ATI_CODECS];
  218. spinlock_t reg_lock;
  219. struct atiixp_dma dmas[NUM_ATI_DMAS];
  220. struct ac97_pcm *pcms[NUM_ATI_PCMS];
  221. struct snd_pcm *pcmdevs[NUM_ATI_PCMDEVS];
  222. int max_channels; /* max. channels for PCM out */
  223. unsigned int codec_not_ready_bits; /* for codec detection */
  224. int spdif_over_aclink; /* passed from the module option */
  225. struct mutex open_mutex; /* playback open mutex */
  226. };
  227. /*
  228. */
  229. static const struct pci_device_id snd_atiixp_ids[] = {
  230. { PCI_VDEVICE(ATI, 0x4341), 0 }, /* SB200 */
  231. { PCI_VDEVICE(ATI, 0x4361), 0 }, /* SB300 */
  232. { PCI_VDEVICE(ATI, 0x4370), 0 }, /* SB400 */
  233. { PCI_VDEVICE(ATI, 0x4382), 0 }, /* SB600 */
  234. { 0, }
  235. };
  236. MODULE_DEVICE_TABLE(pci, snd_atiixp_ids);
  237. static const struct snd_pci_quirk atiixp_quirks[] = {
  238. SND_PCI_QUIRK(0x105b, 0x0c81, "Foxconn RC4107MA-RS2", 0),
  239. SND_PCI_QUIRK(0x15bd, 0x3100, "DFI RS482", 0),
  240. { } /* terminator */
  241. };
  242. /*
  243. * lowlevel functions
  244. */
  245. /*
  246. * update the bits of the given register.
  247. * return 1 if the bits changed.
  248. */
  249. static int snd_atiixp_update_bits(struct atiixp *chip, unsigned int reg,
  250. unsigned int mask, unsigned int value)
  251. {
  252. void __iomem *addr = chip->remap_addr + reg;
  253. unsigned int data, old_data;
  254. old_data = data = readl(addr);
  255. data &= ~mask;
  256. data |= value;
  257. if (old_data == data)
  258. return 0;
  259. writel(data, addr);
  260. return 1;
  261. }
  262. /*
  263. * macros for easy use
  264. */
  265. #define atiixp_write(chip,reg,value) \
  266. writel(value, chip->remap_addr + ATI_REG_##reg)
  267. #define atiixp_read(chip,reg) \
  268. readl(chip->remap_addr + ATI_REG_##reg)
  269. #define atiixp_update(chip,reg,mask,val) \
  270. snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val)
  271. /*
  272. * handling DMA packets
  273. *
  274. * we allocate a linear buffer for the DMA, and split it to each packet.
  275. * in a future version, a scatter-gather buffer should be implemented.
  276. */
  277. #define ATI_DESC_LIST_SIZE \
  278. PAGE_ALIGN(ATI_MAX_DESCRIPTORS * sizeof(struct atiixp_dma_desc))
  279. /*
  280. * build packets ring for the given buffer size.
  281. *
  282. * IXP handles the buffer descriptors, which are connected as a linked
  283. * list. although we can change the list dynamically, in this version,
  284. * a static RING of buffer descriptors is used.
  285. *
  286. * the ring is built in this function, and is set up to the hardware.
  287. */
  288. static int atiixp_build_dma_packets(struct atiixp *chip, struct atiixp_dma *dma,
  289. struct snd_pcm_substream *substream,
  290. unsigned int periods,
  291. unsigned int period_bytes)
  292. {
  293. unsigned int i;
  294. u32 addr, desc_addr;
  295. unsigned long flags;
  296. if (periods > ATI_MAX_DESCRIPTORS)
  297. return -ENOMEM;
  298. if (dma->desc_buf.area == NULL) {
  299. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
  300. &chip->pci->dev,
  301. ATI_DESC_LIST_SIZE,
  302. &dma->desc_buf) < 0)
  303. return -ENOMEM;
  304. dma->period_bytes = dma->periods = 0; /* clear */
  305. }
  306. if (dma->periods == periods && dma->period_bytes == period_bytes)
  307. return 0;
  308. /* reset DMA before changing the descriptor table */
  309. spin_lock_irqsave(&chip->reg_lock, flags);
  310. writel(0, chip->remap_addr + dma->ops->llp_offset);
  311. dma->ops->enable_dma(chip, 0);
  312. dma->ops->enable_dma(chip, 1);
  313. spin_unlock_irqrestore(&chip->reg_lock, flags);
  314. /* fill the entries */
  315. addr = (u32)substream->runtime->dma_addr;
  316. desc_addr = (u32)dma->desc_buf.addr;
  317. for (i = 0; i < periods; i++) {
  318. struct atiixp_dma_desc *desc;
  319. desc = &((struct atiixp_dma_desc *)dma->desc_buf.area)[i];
  320. desc->addr = cpu_to_le32(addr);
  321. desc->status = 0;
  322. desc->size = period_bytes >> 2; /* in dwords */
  323. desc_addr += sizeof(struct atiixp_dma_desc);
  324. if (i == periods - 1)
  325. desc->next = cpu_to_le32((u32)dma->desc_buf.addr);
  326. else
  327. desc->next = cpu_to_le32(desc_addr);
  328. addr += period_bytes;
  329. }
  330. writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
  331. chip->remap_addr + dma->ops->llp_offset);
  332. dma->period_bytes = period_bytes;
  333. dma->periods = periods;
  334. return 0;
  335. }
  336. /*
  337. * remove the ring buffer and release it if assigned
  338. */
  339. static void atiixp_clear_dma_packets(struct atiixp *chip, struct atiixp_dma *dma,
  340. struct snd_pcm_substream *substream)
  341. {
  342. if (dma->desc_buf.area) {
  343. writel(0, chip->remap_addr + dma->ops->llp_offset);
  344. snd_dma_free_pages(&dma->desc_buf);
  345. dma->desc_buf.area = NULL;
  346. }
  347. }
  348. /*
  349. * AC97 interface
  350. */
  351. static int snd_atiixp_acquire_codec(struct atiixp *chip)
  352. {
  353. int timeout = 1000;
  354. while (atiixp_read(chip, PHYS_OUT_ADDR) & ATI_REG_PHYS_OUT_ADDR_EN) {
  355. if (! timeout--) {
  356. dev_warn(chip->card->dev, "codec acquire timeout\n");
  357. return -EBUSY;
  358. }
  359. udelay(1);
  360. }
  361. return 0;
  362. }
  363. static unsigned short snd_atiixp_codec_read(struct atiixp *chip, unsigned short codec, unsigned short reg)
  364. {
  365. unsigned int data;
  366. int timeout;
  367. if (snd_atiixp_acquire_codec(chip) < 0)
  368. return 0xffff;
  369. data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
  370. ATI_REG_PHYS_OUT_ADDR_EN |
  371. ATI_REG_PHYS_OUT_RW |
  372. codec;
  373. atiixp_write(chip, PHYS_OUT_ADDR, data);
  374. if (snd_atiixp_acquire_codec(chip) < 0)
  375. return 0xffff;
  376. timeout = 1000;
  377. do {
  378. data = atiixp_read(chip, PHYS_IN_ADDR);
  379. if (data & ATI_REG_PHYS_IN_READ_FLAG)
  380. return data >> ATI_REG_PHYS_IN_DATA_SHIFT;
  381. udelay(1);
  382. } while (--timeout);
  383. /* time out may happen during reset */
  384. if (reg < 0x7c)
  385. dev_warn(chip->card->dev, "codec read timeout (reg %x)\n", reg);
  386. return 0xffff;
  387. }
  388. static void snd_atiixp_codec_write(struct atiixp *chip, unsigned short codec,
  389. unsigned short reg, unsigned short val)
  390. {
  391. unsigned int data;
  392. if (snd_atiixp_acquire_codec(chip) < 0)
  393. return;
  394. data = ((unsigned int)val << ATI_REG_PHYS_OUT_DATA_SHIFT) |
  395. ((unsigned int)reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
  396. ATI_REG_PHYS_OUT_ADDR_EN | codec;
  397. atiixp_write(chip, PHYS_OUT_ADDR, data);
  398. }
  399. static unsigned short snd_atiixp_ac97_read(struct snd_ac97 *ac97,
  400. unsigned short reg)
  401. {
  402. struct atiixp *chip = ac97->private_data;
  403. return snd_atiixp_codec_read(chip, ac97->num, reg);
  404. }
  405. static void snd_atiixp_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
  406. unsigned short val)
  407. {
  408. struct atiixp *chip = ac97->private_data;
  409. snd_atiixp_codec_write(chip, ac97->num, reg, val);
  410. }
  411. /*
  412. * reset AC link
  413. */
  414. static int snd_atiixp_aclink_reset(struct atiixp *chip)
  415. {
  416. int timeout;
  417. /* reset powerdoewn */
  418. if (atiixp_update(chip, CMD, ATI_REG_CMD_POWERDOWN, 0))
  419. udelay(10);
  420. /* perform a software reset */
  421. atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, ATI_REG_CMD_AC_SOFT_RESET);
  422. atiixp_read(chip, CMD);
  423. udelay(10);
  424. atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, 0);
  425. timeout = 10;
  426. while (! (atiixp_read(chip, CMD) & ATI_REG_CMD_ACLINK_ACTIVE)) {
  427. /* do a hard reset */
  428. atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
  429. ATI_REG_CMD_AC_SYNC);
  430. atiixp_read(chip, CMD);
  431. mdelay(1);
  432. atiixp_update(chip, CMD, ATI_REG_CMD_AC_RESET, ATI_REG_CMD_AC_RESET);
  433. if (!--timeout) {
  434. dev_err(chip->card->dev, "codec reset timeout\n");
  435. break;
  436. }
  437. }
  438. /* deassert RESET and assert SYNC to make sure */
  439. atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
  440. ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET);
  441. return 0;
  442. }
  443. #ifdef CONFIG_PM_SLEEP
  444. static int snd_atiixp_aclink_down(struct atiixp *chip)
  445. {
  446. // if (atiixp_read(chip, MODEM_MIRROR) & 0x1) /* modem running, too? */
  447. // return -EBUSY;
  448. atiixp_update(chip, CMD,
  449. ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET,
  450. ATI_REG_CMD_POWERDOWN);
  451. return 0;
  452. }
  453. #endif
  454. /*
  455. * auto-detection of codecs
  456. *
  457. * the IXP chip can generate interrupts for the non-existing codecs.
  458. * NEW_FRAME interrupt is used to make sure that the interrupt is generated
  459. * even if all three codecs are connected.
  460. */
  461. #define ALL_CODEC_NOT_READY \
  462. (ATI_REG_ISR_CODEC0_NOT_READY |\
  463. ATI_REG_ISR_CODEC1_NOT_READY |\
  464. ATI_REG_ISR_CODEC2_NOT_READY)
  465. #define CODEC_CHECK_BITS (ALL_CODEC_NOT_READY|ATI_REG_ISR_NEW_FRAME)
  466. static int ac97_probing_bugs(struct pci_dev *pci)
  467. {
  468. const struct snd_pci_quirk *q;
  469. q = snd_pci_quirk_lookup(pci, atiixp_quirks);
  470. if (q) {
  471. dev_dbg(&pci->dev, "atiixp quirk for %s. Forcing codec %d\n",
  472. snd_pci_quirk_name(q), q->value);
  473. return q->value;
  474. }
  475. /* this hardware doesn't need workarounds. Probe for codec */
  476. return -1;
  477. }
  478. static int snd_atiixp_codec_detect(struct atiixp *chip)
  479. {
  480. int timeout;
  481. chip->codec_not_ready_bits = 0;
  482. if (ac97_codec == -1)
  483. ac97_codec = ac97_probing_bugs(chip->pci);
  484. if (ac97_codec >= 0) {
  485. chip->codec_not_ready_bits |=
  486. CODEC_CHECK_BITS ^ (1 << (ac97_codec + 10));
  487. return 0;
  488. }
  489. atiixp_write(chip, IER, CODEC_CHECK_BITS);
  490. /* wait for the interrupts */
  491. timeout = 50;
  492. while (timeout-- > 0) {
  493. mdelay(1);
  494. if (chip->codec_not_ready_bits)
  495. break;
  496. }
  497. atiixp_write(chip, IER, 0); /* disable irqs */
  498. if ((chip->codec_not_ready_bits & ALL_CODEC_NOT_READY) == ALL_CODEC_NOT_READY) {
  499. dev_err(chip->card->dev, "no codec detected!\n");
  500. return -ENXIO;
  501. }
  502. return 0;
  503. }
  504. /*
  505. * enable DMA and irqs
  506. */
  507. static int snd_atiixp_chip_start(struct atiixp *chip)
  508. {
  509. unsigned int reg;
  510. /* set up spdif, enable burst mode */
  511. reg = atiixp_read(chip, CMD);
  512. reg |= 0x02 << ATI_REG_CMD_SPDF_THRESHOLD_SHIFT;
  513. reg |= ATI_REG_CMD_BURST_EN;
  514. atiixp_write(chip, CMD, reg);
  515. reg = atiixp_read(chip, SPDF_CMD);
  516. reg &= ~(ATI_REG_SPDF_CMD_LFSR|ATI_REG_SPDF_CMD_SINGLE_CH);
  517. atiixp_write(chip, SPDF_CMD, reg);
  518. /* clear all interrupt source */
  519. atiixp_write(chip, ISR, 0xffffffff);
  520. /* enable irqs */
  521. atiixp_write(chip, IER,
  522. ATI_REG_IER_IO_STATUS_EN |
  523. ATI_REG_IER_IN_XRUN_EN |
  524. ATI_REG_IER_OUT_XRUN_EN |
  525. ATI_REG_IER_SPDF_XRUN_EN |
  526. ATI_REG_IER_SPDF_STATUS_EN);
  527. return 0;
  528. }
  529. /*
  530. * disable DMA and IRQs
  531. */
  532. static int snd_atiixp_chip_stop(struct atiixp *chip)
  533. {
  534. /* clear interrupt source */
  535. atiixp_write(chip, ISR, atiixp_read(chip, ISR));
  536. /* disable irqs */
  537. atiixp_write(chip, IER, 0);
  538. return 0;
  539. }
  540. /*
  541. * PCM section
  542. */
  543. /*
  544. * pointer callback simplly reads XXX_DMA_DT_CUR register as the current
  545. * position. when SG-buffer is implemented, the offset must be calculated
  546. * correctly...
  547. */
  548. static snd_pcm_uframes_t snd_atiixp_pcm_pointer(struct snd_pcm_substream *substream)
  549. {
  550. struct atiixp *chip = snd_pcm_substream_chip(substream);
  551. struct snd_pcm_runtime *runtime = substream->runtime;
  552. struct atiixp_dma *dma = runtime->private_data;
  553. unsigned int curptr;
  554. int timeout = 1000;
  555. while (timeout--) {
  556. curptr = readl(chip->remap_addr + dma->ops->dt_cur);
  557. if (curptr < dma->buf_addr)
  558. continue;
  559. curptr -= dma->buf_addr;
  560. if (curptr >= dma->buf_bytes)
  561. continue;
  562. return bytes_to_frames(runtime, curptr);
  563. }
  564. dev_dbg(chip->card->dev, "invalid DMA pointer read 0x%x (buf=%x)\n",
  565. readl(chip->remap_addr + dma->ops->dt_cur), dma->buf_addr);
  566. return 0;
  567. }
  568. /*
  569. * XRUN detected, and stop the PCM substream
  570. */
  571. static void snd_atiixp_xrun_dma(struct atiixp *chip, struct atiixp_dma *dma)
  572. {
  573. if (! dma->substream || ! dma->running)
  574. return;
  575. dev_dbg(chip->card->dev, "XRUN detected (DMA %d)\n", dma->ops->type);
  576. snd_pcm_stop_xrun(dma->substream);
  577. }
  578. /*
  579. * the period ack. update the substream.
  580. */
  581. static void snd_atiixp_update_dma(struct atiixp *chip, struct atiixp_dma *dma)
  582. {
  583. if (! dma->substream || ! dma->running)
  584. return;
  585. snd_pcm_period_elapsed(dma->substream);
  586. }
  587. /* set BUS_BUSY interrupt bit if any DMA is running */
  588. /* call with spinlock held */
  589. static void snd_atiixp_check_bus_busy(struct atiixp *chip)
  590. {
  591. unsigned int bus_busy;
  592. if (atiixp_read(chip, CMD) & (ATI_REG_CMD_SEND_EN |
  593. ATI_REG_CMD_RECEIVE_EN |
  594. ATI_REG_CMD_SPDF_OUT_EN))
  595. bus_busy = ATI_REG_IER_SET_BUS_BUSY;
  596. else
  597. bus_busy = 0;
  598. atiixp_update(chip, IER, ATI_REG_IER_SET_BUS_BUSY, bus_busy);
  599. }
  600. /* common trigger callback
  601. * calling the lowlevel callbacks in it
  602. */
  603. static int snd_atiixp_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
  604. {
  605. struct atiixp *chip = snd_pcm_substream_chip(substream);
  606. struct atiixp_dma *dma = substream->runtime->private_data;
  607. int err = 0;
  608. if (snd_BUG_ON(!dma->ops->enable_transfer ||
  609. !dma->ops->flush_dma))
  610. return -EINVAL;
  611. spin_lock(&chip->reg_lock);
  612. switch (cmd) {
  613. case SNDRV_PCM_TRIGGER_START:
  614. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  615. case SNDRV_PCM_TRIGGER_RESUME:
  616. if (dma->running && dma->suspended &&
  617. cmd == SNDRV_PCM_TRIGGER_RESUME)
  618. writel(dma->saved_curptr, chip->remap_addr +
  619. dma->ops->dt_cur);
  620. dma->ops->enable_transfer(chip, 1);
  621. dma->running = 1;
  622. dma->suspended = 0;
  623. break;
  624. case SNDRV_PCM_TRIGGER_STOP:
  625. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  626. case SNDRV_PCM_TRIGGER_SUSPEND:
  627. dma->suspended = cmd == SNDRV_PCM_TRIGGER_SUSPEND;
  628. if (dma->running && dma->suspended)
  629. dma->saved_curptr = readl(chip->remap_addr +
  630. dma->ops->dt_cur);
  631. dma->ops->enable_transfer(chip, 0);
  632. dma->running = 0;
  633. break;
  634. default:
  635. err = -EINVAL;
  636. break;
  637. }
  638. if (! err) {
  639. snd_atiixp_check_bus_busy(chip);
  640. if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  641. dma->ops->flush_dma(chip);
  642. snd_atiixp_check_bus_busy(chip);
  643. }
  644. }
  645. spin_unlock(&chip->reg_lock);
  646. return err;
  647. }
  648. /*
  649. * lowlevel callbacks for each DMA type
  650. *
  651. * every callback is supposed to be called in chip->reg_lock spinlock
  652. */
  653. /* flush FIFO of analog OUT DMA */
  654. static void atiixp_out_flush_dma(struct atiixp *chip)
  655. {
  656. atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_OUT_FLUSH);
  657. }
  658. /* enable/disable analog OUT DMA */
  659. static void atiixp_out_enable_dma(struct atiixp *chip, int on)
  660. {
  661. unsigned int data;
  662. data = atiixp_read(chip, CMD);
  663. if (on) {
  664. if (data & ATI_REG_CMD_OUT_DMA_EN)
  665. return;
  666. atiixp_out_flush_dma(chip);
  667. data |= ATI_REG_CMD_OUT_DMA_EN;
  668. } else
  669. data &= ~ATI_REG_CMD_OUT_DMA_EN;
  670. atiixp_write(chip, CMD, data);
  671. }
  672. /* start/stop transfer over OUT DMA */
  673. static void atiixp_out_enable_transfer(struct atiixp *chip, int on)
  674. {
  675. atiixp_update(chip, CMD, ATI_REG_CMD_SEND_EN,
  676. on ? ATI_REG_CMD_SEND_EN : 0);
  677. }
  678. /* enable/disable analog IN DMA */
  679. static void atiixp_in_enable_dma(struct atiixp *chip, int on)
  680. {
  681. atiixp_update(chip, CMD, ATI_REG_CMD_IN_DMA_EN,
  682. on ? ATI_REG_CMD_IN_DMA_EN : 0);
  683. }
  684. /* start/stop analog IN DMA */
  685. static void atiixp_in_enable_transfer(struct atiixp *chip, int on)
  686. {
  687. if (on) {
  688. unsigned int data = atiixp_read(chip, CMD);
  689. if (! (data & ATI_REG_CMD_RECEIVE_EN)) {
  690. data |= ATI_REG_CMD_RECEIVE_EN;
  691. #if 0 /* FIXME: this causes the endless loop */
  692. /* wait until slot 3/4 are finished */
  693. while ((atiixp_read(chip, COUNTER) &
  694. ATI_REG_COUNTER_SLOT) != 5)
  695. ;
  696. #endif
  697. atiixp_write(chip, CMD, data);
  698. }
  699. } else
  700. atiixp_update(chip, CMD, ATI_REG_CMD_RECEIVE_EN, 0);
  701. }
  702. /* flush FIFO of analog IN DMA */
  703. static void atiixp_in_flush_dma(struct atiixp *chip)
  704. {
  705. atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_IN_FLUSH);
  706. }
  707. /* enable/disable SPDIF OUT DMA */
  708. static void atiixp_spdif_enable_dma(struct atiixp *chip, int on)
  709. {
  710. atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_DMA_EN,
  711. on ? ATI_REG_CMD_SPDF_DMA_EN : 0);
  712. }
  713. /* start/stop SPDIF OUT DMA */
  714. static void atiixp_spdif_enable_transfer(struct atiixp *chip, int on)
  715. {
  716. unsigned int data;
  717. data = atiixp_read(chip, CMD);
  718. if (on)
  719. data |= ATI_REG_CMD_SPDF_OUT_EN;
  720. else
  721. data &= ~ATI_REG_CMD_SPDF_OUT_EN;
  722. atiixp_write(chip, CMD, data);
  723. }
  724. /* flush FIFO of SPDIF OUT DMA */
  725. static void atiixp_spdif_flush_dma(struct atiixp *chip)
  726. {
  727. int timeout;
  728. /* DMA off, transfer on */
  729. atiixp_spdif_enable_dma(chip, 0);
  730. atiixp_spdif_enable_transfer(chip, 1);
  731. timeout = 100;
  732. do {
  733. if (! (atiixp_read(chip, SPDF_DMA_DT_SIZE) & ATI_REG_DMA_FIFO_USED))
  734. break;
  735. udelay(1);
  736. } while (timeout-- > 0);
  737. atiixp_spdif_enable_transfer(chip, 0);
  738. }
  739. /* set up slots and formats for SPDIF OUT */
  740. static int snd_atiixp_spdif_prepare(struct snd_pcm_substream *substream)
  741. {
  742. struct atiixp *chip = snd_pcm_substream_chip(substream);
  743. spin_lock_irq(&chip->reg_lock);
  744. if (chip->spdif_over_aclink) {
  745. unsigned int data;
  746. /* enable slots 10/11 */
  747. atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK,
  748. ATI_REG_CMD_SPDF_CONFIG_01);
  749. data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK;
  750. data |= ATI_REG_OUT_DMA_SLOT_BIT(10) |
  751. ATI_REG_OUT_DMA_SLOT_BIT(11);
  752. data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
  753. atiixp_write(chip, OUT_DMA_SLOT, data);
  754. atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT,
  755. substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
  756. ATI_REG_CMD_INTERLEAVE_OUT : 0);
  757. } else {
  758. atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK, 0);
  759. atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_SPDF, 0);
  760. }
  761. spin_unlock_irq(&chip->reg_lock);
  762. return 0;
  763. }
  764. /* set up slots and formats for analog OUT */
  765. static int snd_atiixp_playback_prepare(struct snd_pcm_substream *substream)
  766. {
  767. struct atiixp *chip = snd_pcm_substream_chip(substream);
  768. unsigned int data;
  769. spin_lock_irq(&chip->reg_lock);
  770. data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK;
  771. switch (substream->runtime->channels) {
  772. case 8:
  773. data |= ATI_REG_OUT_DMA_SLOT_BIT(10) |
  774. ATI_REG_OUT_DMA_SLOT_BIT(11);
  775. fallthrough;
  776. case 6:
  777. data |= ATI_REG_OUT_DMA_SLOT_BIT(7) |
  778. ATI_REG_OUT_DMA_SLOT_BIT(8);
  779. fallthrough;
  780. case 4:
  781. data |= ATI_REG_OUT_DMA_SLOT_BIT(6) |
  782. ATI_REG_OUT_DMA_SLOT_BIT(9);
  783. fallthrough;
  784. default:
  785. data |= ATI_REG_OUT_DMA_SLOT_BIT(3) |
  786. ATI_REG_OUT_DMA_SLOT_BIT(4);
  787. break;
  788. }
  789. /* set output threshold */
  790. data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
  791. atiixp_write(chip, OUT_DMA_SLOT, data);
  792. atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT,
  793. substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
  794. ATI_REG_CMD_INTERLEAVE_OUT : 0);
  795. /*
  796. * enable 6 channel re-ordering bit if needed
  797. */
  798. atiixp_update(chip, 6CH_REORDER, ATI_REG_6CH_REORDER_EN,
  799. substream->runtime->channels >= 6 ? ATI_REG_6CH_REORDER_EN: 0);
  800. spin_unlock_irq(&chip->reg_lock);
  801. return 0;
  802. }
  803. /* set up slots and formats for analog IN */
  804. static int snd_atiixp_capture_prepare(struct snd_pcm_substream *substream)
  805. {
  806. struct atiixp *chip = snd_pcm_substream_chip(substream);
  807. spin_lock_irq(&chip->reg_lock);
  808. atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_IN,
  809. substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
  810. ATI_REG_CMD_INTERLEAVE_IN : 0);
  811. spin_unlock_irq(&chip->reg_lock);
  812. return 0;
  813. }
  814. /*
  815. * hw_params - allocate the buffer and set up buffer descriptors
  816. */
  817. static int snd_atiixp_pcm_hw_params(struct snd_pcm_substream *substream,
  818. struct snd_pcm_hw_params *hw_params)
  819. {
  820. struct atiixp *chip = snd_pcm_substream_chip(substream);
  821. struct atiixp_dma *dma = substream->runtime->private_data;
  822. int err;
  823. dma->buf_addr = substream->runtime->dma_addr;
  824. dma->buf_bytes = params_buffer_bytes(hw_params);
  825. err = atiixp_build_dma_packets(chip, dma, substream,
  826. params_periods(hw_params),
  827. params_period_bytes(hw_params));
  828. if (err < 0)
  829. return err;
  830. if (dma->ac97_pcm_type >= 0) {
  831. struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type];
  832. /* PCM is bound to AC97 codec(s)
  833. * set up the AC97 codecs
  834. */
  835. if (dma->pcm_open_flag) {
  836. snd_ac97_pcm_close(pcm);
  837. dma->pcm_open_flag = 0;
  838. }
  839. err = snd_ac97_pcm_open(pcm, params_rate(hw_params),
  840. params_channels(hw_params),
  841. pcm->r[0].slots);
  842. if (err >= 0)
  843. dma->pcm_open_flag = 1;
  844. }
  845. return err;
  846. }
  847. static int snd_atiixp_pcm_hw_free(struct snd_pcm_substream *substream)
  848. {
  849. struct atiixp *chip = snd_pcm_substream_chip(substream);
  850. struct atiixp_dma *dma = substream->runtime->private_data;
  851. if (dma->pcm_open_flag) {
  852. struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type];
  853. snd_ac97_pcm_close(pcm);
  854. dma->pcm_open_flag = 0;
  855. }
  856. atiixp_clear_dma_packets(chip, dma, substream);
  857. return 0;
  858. }
  859. /*
  860. * pcm hardware definition, identical for all DMA types
  861. */
  862. static const struct snd_pcm_hardware snd_atiixp_pcm_hw =
  863. {
  864. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  865. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  866. SNDRV_PCM_INFO_PAUSE |
  867. SNDRV_PCM_INFO_RESUME |
  868. SNDRV_PCM_INFO_MMAP_VALID),
  869. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
  870. .rates = SNDRV_PCM_RATE_48000,
  871. .rate_min = 48000,
  872. .rate_max = 48000,
  873. .channels_min = 2,
  874. .channels_max = 2,
  875. .buffer_bytes_max = 256 * 1024,
  876. .period_bytes_min = 32,
  877. .period_bytes_max = 128 * 1024,
  878. .periods_min = 2,
  879. .periods_max = ATI_MAX_DESCRIPTORS,
  880. };
  881. static int snd_atiixp_pcm_open(struct snd_pcm_substream *substream,
  882. struct atiixp_dma *dma, int pcm_type)
  883. {
  884. struct atiixp *chip = snd_pcm_substream_chip(substream);
  885. struct snd_pcm_runtime *runtime = substream->runtime;
  886. int err;
  887. if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma))
  888. return -EINVAL;
  889. if (dma->opened)
  890. return -EBUSY;
  891. dma->substream = substream;
  892. runtime->hw = snd_atiixp_pcm_hw;
  893. dma->ac97_pcm_type = pcm_type;
  894. if (pcm_type >= 0) {
  895. runtime->hw.rates = chip->pcms[pcm_type]->rates;
  896. snd_pcm_limit_hw_rates(runtime);
  897. } else {
  898. /* direct SPDIF */
  899. runtime->hw.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
  900. }
  901. if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
  902. return err;
  903. runtime->private_data = dma;
  904. /* enable DMA bits */
  905. spin_lock_irq(&chip->reg_lock);
  906. dma->ops->enable_dma(chip, 1);
  907. spin_unlock_irq(&chip->reg_lock);
  908. dma->opened = 1;
  909. return 0;
  910. }
  911. static int snd_atiixp_pcm_close(struct snd_pcm_substream *substream,
  912. struct atiixp_dma *dma)
  913. {
  914. struct atiixp *chip = snd_pcm_substream_chip(substream);
  915. /* disable DMA bits */
  916. if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma))
  917. return -EINVAL;
  918. spin_lock_irq(&chip->reg_lock);
  919. dma->ops->enable_dma(chip, 0);
  920. spin_unlock_irq(&chip->reg_lock);
  921. dma->substream = NULL;
  922. dma->opened = 0;
  923. return 0;
  924. }
  925. /*
  926. */
  927. static int snd_atiixp_playback_open(struct snd_pcm_substream *substream)
  928. {
  929. struct atiixp *chip = snd_pcm_substream_chip(substream);
  930. int err;
  931. mutex_lock(&chip->open_mutex);
  932. err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 0);
  933. mutex_unlock(&chip->open_mutex);
  934. if (err < 0)
  935. return err;
  936. substream->runtime->hw.channels_max = chip->max_channels;
  937. if (chip->max_channels > 2)
  938. /* channels must be even */
  939. snd_pcm_hw_constraint_step(substream->runtime, 0,
  940. SNDRV_PCM_HW_PARAM_CHANNELS, 2);
  941. return 0;
  942. }
  943. static int snd_atiixp_playback_close(struct snd_pcm_substream *substream)
  944. {
  945. struct atiixp *chip = snd_pcm_substream_chip(substream);
  946. int err;
  947. mutex_lock(&chip->open_mutex);
  948. err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
  949. mutex_unlock(&chip->open_mutex);
  950. return err;
  951. }
  952. static int snd_atiixp_capture_open(struct snd_pcm_substream *substream)
  953. {
  954. struct atiixp *chip = snd_pcm_substream_chip(substream);
  955. return snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_CAPTURE], 1);
  956. }
  957. static int snd_atiixp_capture_close(struct snd_pcm_substream *substream)
  958. {
  959. struct atiixp *chip = snd_pcm_substream_chip(substream);
  960. return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_CAPTURE]);
  961. }
  962. static int snd_atiixp_spdif_open(struct snd_pcm_substream *substream)
  963. {
  964. struct atiixp *chip = snd_pcm_substream_chip(substream);
  965. int err;
  966. mutex_lock(&chip->open_mutex);
  967. if (chip->spdif_over_aclink) /* share DMA_PLAYBACK */
  968. err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 2);
  969. else
  970. err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_SPDIF], -1);
  971. mutex_unlock(&chip->open_mutex);
  972. return err;
  973. }
  974. static int snd_atiixp_spdif_close(struct snd_pcm_substream *substream)
  975. {
  976. struct atiixp *chip = snd_pcm_substream_chip(substream);
  977. int err;
  978. mutex_lock(&chip->open_mutex);
  979. if (chip->spdif_over_aclink)
  980. err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
  981. else
  982. err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_SPDIF]);
  983. mutex_unlock(&chip->open_mutex);
  984. return err;
  985. }
  986. /* AC97 playback */
  987. static const struct snd_pcm_ops snd_atiixp_playback_ops = {
  988. .open = snd_atiixp_playback_open,
  989. .close = snd_atiixp_playback_close,
  990. .hw_params = snd_atiixp_pcm_hw_params,
  991. .hw_free = snd_atiixp_pcm_hw_free,
  992. .prepare = snd_atiixp_playback_prepare,
  993. .trigger = snd_atiixp_pcm_trigger,
  994. .pointer = snd_atiixp_pcm_pointer,
  995. };
  996. /* AC97 capture */
  997. static const struct snd_pcm_ops snd_atiixp_capture_ops = {
  998. .open = snd_atiixp_capture_open,
  999. .close = snd_atiixp_capture_close,
  1000. .hw_params = snd_atiixp_pcm_hw_params,
  1001. .hw_free = snd_atiixp_pcm_hw_free,
  1002. .prepare = snd_atiixp_capture_prepare,
  1003. .trigger = snd_atiixp_pcm_trigger,
  1004. .pointer = snd_atiixp_pcm_pointer,
  1005. };
  1006. /* SPDIF playback */
  1007. static const struct snd_pcm_ops snd_atiixp_spdif_ops = {
  1008. .open = snd_atiixp_spdif_open,
  1009. .close = snd_atiixp_spdif_close,
  1010. .hw_params = snd_atiixp_pcm_hw_params,
  1011. .hw_free = snd_atiixp_pcm_hw_free,
  1012. .prepare = snd_atiixp_spdif_prepare,
  1013. .trigger = snd_atiixp_pcm_trigger,
  1014. .pointer = snd_atiixp_pcm_pointer,
  1015. };
  1016. static const struct ac97_pcm atiixp_pcm_defs[] = {
  1017. /* front PCM */
  1018. {
  1019. .exclusive = 1,
  1020. .r = { {
  1021. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  1022. (1 << AC97_SLOT_PCM_RIGHT) |
  1023. (1 << AC97_SLOT_PCM_CENTER) |
  1024. (1 << AC97_SLOT_PCM_SLEFT) |
  1025. (1 << AC97_SLOT_PCM_SRIGHT) |
  1026. (1 << AC97_SLOT_LFE)
  1027. }
  1028. }
  1029. },
  1030. /* PCM IN #1 */
  1031. {
  1032. .stream = 1,
  1033. .exclusive = 1,
  1034. .r = { {
  1035. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  1036. (1 << AC97_SLOT_PCM_RIGHT)
  1037. }
  1038. }
  1039. },
  1040. /* S/PDIF OUT (optional) */
  1041. {
  1042. .exclusive = 1,
  1043. .spdif = 1,
  1044. .r = { {
  1045. .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
  1046. (1 << AC97_SLOT_SPDIF_RIGHT2)
  1047. }
  1048. }
  1049. },
  1050. };
  1051. static const struct atiixp_dma_ops snd_atiixp_playback_dma_ops = {
  1052. .type = ATI_DMA_PLAYBACK,
  1053. .llp_offset = ATI_REG_OUT_DMA_LINKPTR,
  1054. .dt_cur = ATI_REG_OUT_DMA_DT_CUR,
  1055. .enable_dma = atiixp_out_enable_dma,
  1056. .enable_transfer = atiixp_out_enable_transfer,
  1057. .flush_dma = atiixp_out_flush_dma,
  1058. };
  1059. static const struct atiixp_dma_ops snd_atiixp_capture_dma_ops = {
  1060. .type = ATI_DMA_CAPTURE,
  1061. .llp_offset = ATI_REG_IN_DMA_LINKPTR,
  1062. .dt_cur = ATI_REG_IN_DMA_DT_CUR,
  1063. .enable_dma = atiixp_in_enable_dma,
  1064. .enable_transfer = atiixp_in_enable_transfer,
  1065. .flush_dma = atiixp_in_flush_dma,
  1066. };
  1067. static const struct atiixp_dma_ops snd_atiixp_spdif_dma_ops = {
  1068. .type = ATI_DMA_SPDIF,
  1069. .llp_offset = ATI_REG_SPDF_DMA_LINKPTR,
  1070. .dt_cur = ATI_REG_SPDF_DMA_DT_CUR,
  1071. .enable_dma = atiixp_spdif_enable_dma,
  1072. .enable_transfer = atiixp_spdif_enable_transfer,
  1073. .flush_dma = atiixp_spdif_flush_dma,
  1074. };
  1075. static int snd_atiixp_pcm_new(struct atiixp *chip)
  1076. {
  1077. struct snd_pcm *pcm;
  1078. struct snd_pcm_chmap *chmap;
  1079. struct snd_ac97_bus *pbus = chip->ac97_bus;
  1080. int err, i, num_pcms;
  1081. /* initialize constants */
  1082. chip->dmas[ATI_DMA_PLAYBACK].ops = &snd_atiixp_playback_dma_ops;
  1083. chip->dmas[ATI_DMA_CAPTURE].ops = &snd_atiixp_capture_dma_ops;
  1084. if (! chip->spdif_over_aclink)
  1085. chip->dmas[ATI_DMA_SPDIF].ops = &snd_atiixp_spdif_dma_ops;
  1086. /* assign AC97 pcm */
  1087. if (chip->spdif_over_aclink)
  1088. num_pcms = 3;
  1089. else
  1090. num_pcms = 2;
  1091. err = snd_ac97_pcm_assign(pbus, num_pcms, atiixp_pcm_defs);
  1092. if (err < 0)
  1093. return err;
  1094. for (i = 0; i < num_pcms; i++)
  1095. chip->pcms[i] = &pbus->pcms[i];
  1096. chip->max_channels = 2;
  1097. if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
  1098. if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_LFE))
  1099. chip->max_channels = 6;
  1100. else
  1101. chip->max_channels = 4;
  1102. }
  1103. /* PCM #0: analog I/O */
  1104. err = snd_pcm_new(chip->card, "ATI IXP AC97",
  1105. ATI_PCMDEV_ANALOG, 1, 1, &pcm);
  1106. if (err < 0)
  1107. return err;
  1108. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_playback_ops);
  1109. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_atiixp_capture_ops);
  1110. pcm->private_data = chip;
  1111. strcpy(pcm->name, "ATI IXP AC97");
  1112. chip->pcmdevs[ATI_PCMDEV_ANALOG] = pcm;
  1113. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  1114. &chip->pci->dev, 64*1024, 128*1024);
  1115. err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1116. snd_pcm_alt_chmaps, chip->max_channels, 0,
  1117. &chmap);
  1118. if (err < 0)
  1119. return err;
  1120. chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
  1121. chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
  1122. /* no SPDIF support on codec? */
  1123. if (chip->pcms[ATI_PCM_SPDIF] && ! chip->pcms[ATI_PCM_SPDIF]->rates)
  1124. return 0;
  1125. /* FIXME: non-48k sample rate doesn't work on my test machine with AD1888 */
  1126. if (chip->pcms[ATI_PCM_SPDIF])
  1127. chip->pcms[ATI_PCM_SPDIF]->rates = SNDRV_PCM_RATE_48000;
  1128. /* PCM #1: spdif playback */
  1129. err = snd_pcm_new(chip->card, "ATI IXP IEC958",
  1130. ATI_PCMDEV_DIGITAL, 1, 0, &pcm);
  1131. if (err < 0)
  1132. return err;
  1133. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_spdif_ops);
  1134. pcm->private_data = chip;
  1135. if (chip->spdif_over_aclink)
  1136. strcpy(pcm->name, "ATI IXP IEC958 (AC97)");
  1137. else
  1138. strcpy(pcm->name, "ATI IXP IEC958 (Direct)");
  1139. chip->pcmdevs[ATI_PCMDEV_DIGITAL] = pcm;
  1140. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  1141. &chip->pci->dev, 64*1024, 128*1024);
  1142. /* pre-select AC97 SPDIF slots 10/11 */
  1143. for (i = 0; i < NUM_ATI_CODECS; i++) {
  1144. if (chip->ac97[i])
  1145. snd_ac97_update_bits(chip->ac97[i],
  1146. AC97_EXTENDED_STATUS,
  1147. 0x03 << 4, 0x03 << 4);
  1148. }
  1149. return 0;
  1150. }
  1151. /*
  1152. * interrupt handler
  1153. */
  1154. static irqreturn_t snd_atiixp_interrupt(int irq, void *dev_id)
  1155. {
  1156. struct atiixp *chip = dev_id;
  1157. unsigned int status;
  1158. status = atiixp_read(chip, ISR);
  1159. if (! status)
  1160. return IRQ_NONE;
  1161. /* process audio DMA */
  1162. if (status & ATI_REG_ISR_OUT_XRUN)
  1163. snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
  1164. else if (status & ATI_REG_ISR_OUT_STATUS)
  1165. snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
  1166. if (status & ATI_REG_ISR_IN_XRUN)
  1167. snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
  1168. else if (status & ATI_REG_ISR_IN_STATUS)
  1169. snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
  1170. if (! chip->spdif_over_aclink) {
  1171. if (status & ATI_REG_ISR_SPDF_XRUN)
  1172. snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_SPDIF]);
  1173. else if (status & ATI_REG_ISR_SPDF_STATUS)
  1174. snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_SPDIF]);
  1175. }
  1176. /* for codec detection */
  1177. if (status & CODEC_CHECK_BITS) {
  1178. unsigned int detected;
  1179. detected = status & CODEC_CHECK_BITS;
  1180. spin_lock(&chip->reg_lock);
  1181. chip->codec_not_ready_bits |= detected;
  1182. atiixp_update(chip, IER, detected, 0); /* disable the detected irqs */
  1183. spin_unlock(&chip->reg_lock);
  1184. }
  1185. /* ack */
  1186. atiixp_write(chip, ISR, status);
  1187. return IRQ_HANDLED;
  1188. }
  1189. /*
  1190. * ac97 mixer section
  1191. */
  1192. static const struct ac97_quirk ac97_quirks[] = {
  1193. {
  1194. .subvendor = 0x103c,
  1195. .subdevice = 0x006b,
  1196. .name = "HP Pavilion ZV5030US",
  1197. .type = AC97_TUNE_MUTE_LED
  1198. },
  1199. {
  1200. .subvendor = 0x103c,
  1201. .subdevice = 0x308b,
  1202. .name = "HP nx6125",
  1203. .type = AC97_TUNE_MUTE_LED
  1204. },
  1205. {
  1206. .subvendor = 0x103c,
  1207. .subdevice = 0x3091,
  1208. .name = "unknown HP",
  1209. .type = AC97_TUNE_MUTE_LED
  1210. },
  1211. { } /* terminator */
  1212. };
  1213. static int snd_atiixp_mixer_new(struct atiixp *chip, int clock,
  1214. const char *quirk_override)
  1215. {
  1216. struct snd_ac97_bus *pbus;
  1217. struct snd_ac97_template ac97;
  1218. int i, err;
  1219. int codec_count;
  1220. static const struct snd_ac97_bus_ops ops = {
  1221. .write = snd_atiixp_ac97_write,
  1222. .read = snd_atiixp_ac97_read,
  1223. };
  1224. static const unsigned int codec_skip[NUM_ATI_CODECS] = {
  1225. ATI_REG_ISR_CODEC0_NOT_READY,
  1226. ATI_REG_ISR_CODEC1_NOT_READY,
  1227. ATI_REG_ISR_CODEC2_NOT_READY,
  1228. };
  1229. if (snd_atiixp_codec_detect(chip) < 0)
  1230. return -ENXIO;
  1231. if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0)
  1232. return err;
  1233. pbus->clock = clock;
  1234. chip->ac97_bus = pbus;
  1235. codec_count = 0;
  1236. for (i = 0; i < NUM_ATI_CODECS; i++) {
  1237. if (chip->codec_not_ready_bits & codec_skip[i])
  1238. continue;
  1239. memset(&ac97, 0, sizeof(ac97));
  1240. ac97.private_data = chip;
  1241. ac97.pci = chip->pci;
  1242. ac97.num = i;
  1243. ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
  1244. if (! chip->spdif_over_aclink)
  1245. ac97.scaps |= AC97_SCAP_NO_SPDIF;
  1246. if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
  1247. chip->ac97[i] = NULL; /* to be sure */
  1248. dev_dbg(chip->card->dev,
  1249. "codec %d not available for audio\n", i);
  1250. continue;
  1251. }
  1252. codec_count++;
  1253. }
  1254. if (! codec_count) {
  1255. dev_err(chip->card->dev, "no codec available\n");
  1256. return -ENODEV;
  1257. }
  1258. snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
  1259. return 0;
  1260. }
  1261. #ifdef CONFIG_PM_SLEEP
  1262. /*
  1263. * power management
  1264. */
  1265. static int snd_atiixp_suspend(struct device *dev)
  1266. {
  1267. struct snd_card *card = dev_get_drvdata(dev);
  1268. struct atiixp *chip = card->private_data;
  1269. int i;
  1270. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  1271. for (i = 0; i < NUM_ATI_CODECS; i++)
  1272. snd_ac97_suspend(chip->ac97[i]);
  1273. snd_atiixp_aclink_down(chip);
  1274. snd_atiixp_chip_stop(chip);
  1275. return 0;
  1276. }
  1277. static int snd_atiixp_resume(struct device *dev)
  1278. {
  1279. struct snd_card *card = dev_get_drvdata(dev);
  1280. struct atiixp *chip = card->private_data;
  1281. int i;
  1282. snd_atiixp_aclink_reset(chip);
  1283. snd_atiixp_chip_start(chip);
  1284. for (i = 0; i < NUM_ATI_CODECS; i++)
  1285. snd_ac97_resume(chip->ac97[i]);
  1286. for (i = 0; i < NUM_ATI_PCMDEVS; i++)
  1287. if (chip->pcmdevs[i]) {
  1288. struct atiixp_dma *dma = &chip->dmas[i];
  1289. if (dma->substream && dma->suspended) {
  1290. dma->ops->enable_dma(chip, 1);
  1291. dma->substream->ops->prepare(dma->substream);
  1292. writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
  1293. chip->remap_addr + dma->ops->llp_offset);
  1294. }
  1295. }
  1296. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  1297. return 0;
  1298. }
  1299. static SIMPLE_DEV_PM_OPS(snd_atiixp_pm, snd_atiixp_suspend, snd_atiixp_resume);
  1300. #define SND_ATIIXP_PM_OPS &snd_atiixp_pm
  1301. #else
  1302. #define SND_ATIIXP_PM_OPS NULL
  1303. #endif /* CONFIG_PM_SLEEP */
  1304. /*
  1305. * proc interface for register dump
  1306. */
  1307. static void snd_atiixp_proc_read(struct snd_info_entry *entry,
  1308. struct snd_info_buffer *buffer)
  1309. {
  1310. struct atiixp *chip = entry->private_data;
  1311. int i;
  1312. for (i = 0; i < 256; i += 4)
  1313. snd_iprintf(buffer, "%02x: %08x\n", i, readl(chip->remap_addr + i));
  1314. }
  1315. static void snd_atiixp_proc_init(struct atiixp *chip)
  1316. {
  1317. snd_card_ro_proc_new(chip->card, "atiixp", chip, snd_atiixp_proc_read);
  1318. }
  1319. /*
  1320. * destructor
  1321. */
  1322. static int snd_atiixp_free(struct atiixp *chip)
  1323. {
  1324. if (chip->irq < 0)
  1325. goto __hw_end;
  1326. snd_atiixp_chip_stop(chip);
  1327. __hw_end:
  1328. if (chip->irq >= 0)
  1329. free_irq(chip->irq, chip);
  1330. iounmap(chip->remap_addr);
  1331. pci_release_regions(chip->pci);
  1332. pci_disable_device(chip->pci);
  1333. kfree(chip);
  1334. return 0;
  1335. }
  1336. static int snd_atiixp_dev_free(struct snd_device *device)
  1337. {
  1338. struct atiixp *chip = device->device_data;
  1339. return snd_atiixp_free(chip);
  1340. }
  1341. /*
  1342. * constructor for chip instance
  1343. */
  1344. static int snd_atiixp_create(struct snd_card *card,
  1345. struct pci_dev *pci,
  1346. struct atiixp **r_chip)
  1347. {
  1348. static const struct snd_device_ops ops = {
  1349. .dev_free = snd_atiixp_dev_free,
  1350. };
  1351. struct atiixp *chip;
  1352. int err;
  1353. if ((err = pci_enable_device(pci)) < 0)
  1354. return err;
  1355. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  1356. if (chip == NULL) {
  1357. pci_disable_device(pci);
  1358. return -ENOMEM;
  1359. }
  1360. spin_lock_init(&chip->reg_lock);
  1361. mutex_init(&chip->open_mutex);
  1362. chip->card = card;
  1363. chip->pci = pci;
  1364. chip->irq = -1;
  1365. if ((err = pci_request_regions(pci, "ATI IXP AC97")) < 0) {
  1366. pci_disable_device(pci);
  1367. kfree(chip);
  1368. return err;
  1369. }
  1370. chip->addr = pci_resource_start(pci, 0);
  1371. chip->remap_addr = pci_ioremap_bar(pci, 0);
  1372. if (chip->remap_addr == NULL) {
  1373. dev_err(card->dev, "AC'97 space ioremap problem\n");
  1374. snd_atiixp_free(chip);
  1375. return -EIO;
  1376. }
  1377. if (request_irq(pci->irq, snd_atiixp_interrupt, IRQF_SHARED,
  1378. KBUILD_MODNAME, chip)) {
  1379. dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
  1380. snd_atiixp_free(chip);
  1381. return -EBUSY;
  1382. }
  1383. chip->irq = pci->irq;
  1384. card->sync_irq = chip->irq;
  1385. pci_set_master(pci);
  1386. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  1387. snd_atiixp_free(chip);
  1388. return err;
  1389. }
  1390. *r_chip = chip;
  1391. return 0;
  1392. }
  1393. static int snd_atiixp_probe(struct pci_dev *pci,
  1394. const struct pci_device_id *pci_id)
  1395. {
  1396. struct snd_card *card;
  1397. struct atiixp *chip;
  1398. int err;
  1399. err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
  1400. if (err < 0)
  1401. return err;
  1402. strcpy(card->driver, spdif_aclink ? "ATIIXP" : "ATIIXP-SPDMA");
  1403. strcpy(card->shortname, "ATI IXP");
  1404. if ((err = snd_atiixp_create(card, pci, &chip)) < 0)
  1405. goto __error;
  1406. card->private_data = chip;
  1407. if ((err = snd_atiixp_aclink_reset(chip)) < 0)
  1408. goto __error;
  1409. chip->spdif_over_aclink = spdif_aclink;
  1410. if ((err = snd_atiixp_mixer_new(chip, ac97_clock, ac97_quirk)) < 0)
  1411. goto __error;
  1412. if ((err = snd_atiixp_pcm_new(chip)) < 0)
  1413. goto __error;
  1414. snd_atiixp_proc_init(chip);
  1415. snd_atiixp_chip_start(chip);
  1416. snprintf(card->longname, sizeof(card->longname),
  1417. "%s rev %x with %s at %#lx, irq %i", card->shortname,
  1418. pci->revision,
  1419. chip->ac97[0] ? snd_ac97_get_short_name(chip->ac97[0]) : "?",
  1420. chip->addr, chip->irq);
  1421. if ((err = snd_card_register(card)) < 0)
  1422. goto __error;
  1423. pci_set_drvdata(pci, card);
  1424. return 0;
  1425. __error:
  1426. snd_card_free(card);
  1427. return err;
  1428. }
  1429. static void snd_atiixp_remove(struct pci_dev *pci)
  1430. {
  1431. snd_card_free(pci_get_drvdata(pci));
  1432. }
  1433. static struct pci_driver atiixp_driver = {
  1434. .name = KBUILD_MODNAME,
  1435. .id_table = snd_atiixp_ids,
  1436. .probe = snd_atiixp_probe,
  1437. .remove = snd_atiixp_remove,
  1438. .driver = {
  1439. .pm = SND_ATIIXP_PM_OPS,
  1440. },
  1441. };
  1442. module_pci_driver(atiixp_driver);