als4000.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * card-als4000.c - driver for Avance Logic ALS4000 based soundcards.
  4. * Copyright (C) 2000 by Bart Hartgers <bart@etpmod.phys.tue.nl>,
  5. * Jaroslav Kysela <perex@perex.cz>
  6. * Copyright (C) 2002, 2008 by Andreas Mohr <hw7oshyuv3001@sneakemail.com>
  7. *
  8. * Framework borrowed from Massimo Piccioni's card-als100.c.
  9. *
  10. * NOTES
  11. *
  12. * Since Avance does not provide any meaningful documentation, and I
  13. * bought an ALS4000 based soundcard, I was forced to base this driver
  14. * on reverse engineering.
  15. *
  16. * Note: this is no longer true (thank you!):
  17. * pretty verbose chip docu (ALS4000a.PDF) can be found on the ALSA web site.
  18. * Page numbers stated anywhere below with the "SPECS_PAGE:" tag
  19. * refer to: ALS4000a.PDF specs Ver 1.0, May 28th, 1998.
  20. *
  21. * The ALS4000 seems to be the PCI-cousin of the ALS100. It contains an
  22. * ALS100-like SB DSP/mixer, an OPL3 synth, a MPU401 and a gameport
  23. * interface. These subsystems can be mapped into ISA io-port space,
  24. * using the PCI-interface. In addition, the PCI-bit provides DMA and IRQ
  25. * services to the subsystems.
  26. *
  27. * While ALS4000 is very similar to a SoundBlaster, the differences in
  28. * DMA and capturing require more changes to the SoundBlaster than
  29. * desirable, so I made this separate driver.
  30. *
  31. * The ALS4000 can do real full duplex playback/capture.
  32. *
  33. * FMDAC:
  34. * - 0x4f -> port 0x14
  35. * - port 0x15 |= 1
  36. *
  37. * Enable/disable 3D sound:
  38. * - 0x50 -> port 0x14
  39. * - change bit 6 (0x40) of port 0x15
  40. *
  41. * Set QSound:
  42. * - 0xdb -> port 0x14
  43. * - set port 0x15:
  44. * 0x3e (mode 3), 0x3c (mode 2), 0x3a (mode 1), 0x38 (mode 0)
  45. *
  46. * Set KSound:
  47. * - value -> some port 0x0c0d
  48. *
  49. * ToDo:
  50. * - by default, don't enable legacy game and use PCI game I/O
  51. * - power management? (card can do voice wakeup according to datasheet!!)
  52. */
  53. #include <linux/io.h>
  54. #include <linux/init.h>
  55. #include <linux/pci.h>
  56. #include <linux/gameport.h>
  57. #include <linux/module.h>
  58. #include <linux/dma-mapping.h>
  59. #include <sound/core.h>
  60. #include <sound/pcm.h>
  61. #include <sound/rawmidi.h>
  62. #include <sound/mpu401.h>
  63. #include <sound/opl3.h>
  64. #include <sound/sb.h>
  65. #include <sound/initval.h>
  66. MODULE_AUTHOR("Bart Hartgers <bart@etpmod.phys.tue.nl>, Andreas Mohr");
  67. MODULE_DESCRIPTION("Avance Logic ALS4000");
  68. MODULE_LICENSE("GPL");
  69. MODULE_SUPPORTED_DEVICE("{{Avance Logic,ALS4000}}");
  70. #if IS_REACHABLE(CONFIG_GAMEPORT)
  71. #define SUPPORT_JOYSTICK 1
  72. #endif
  73. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  74. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  75. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  76. #ifdef SUPPORT_JOYSTICK
  77. static int joystick_port[SNDRV_CARDS];
  78. #endif
  79. module_param_array(index, int, NULL, 0444);
  80. MODULE_PARM_DESC(index, "Index value for ALS4000 soundcard.");
  81. module_param_array(id, charp, NULL, 0444);
  82. MODULE_PARM_DESC(id, "ID string for ALS4000 soundcard.");
  83. module_param_array(enable, bool, NULL, 0444);
  84. MODULE_PARM_DESC(enable, "Enable ALS4000 soundcard.");
  85. #ifdef SUPPORT_JOYSTICK
  86. module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
  87. MODULE_PARM_DESC(joystick_port, "Joystick port address for ALS4000 soundcard. (0 = disabled)");
  88. #endif
  89. struct snd_card_als4000 {
  90. /* most frequent access first */
  91. unsigned long iobase;
  92. struct pci_dev *pci;
  93. struct snd_sb *chip;
  94. #ifdef SUPPORT_JOYSTICK
  95. struct gameport *gameport;
  96. #endif
  97. };
  98. static const struct pci_device_id snd_als4000_ids[] = {
  99. { 0x4005, 0x4000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ALS4000 */
  100. { 0, }
  101. };
  102. MODULE_DEVICE_TABLE(pci, snd_als4000_ids);
  103. enum als4k_iobase_t {
  104. /* IOx: B == Byte, W = Word, D = DWord; SPECS_PAGE: 37 */
  105. ALS4K_IOD_00_AC97_ACCESS = 0x00,
  106. ALS4K_IOW_04_AC97_READ = 0x04,
  107. ALS4K_IOB_06_AC97_STATUS = 0x06,
  108. ALS4K_IOB_07_IRQSTATUS = 0x07,
  109. ALS4K_IOD_08_GCR_DATA = 0x08,
  110. ALS4K_IOB_0C_GCR_INDEX = 0x0c,
  111. ALS4K_IOB_0E_IRQTYPE_SB_CR1E_MPU = 0x0e,
  112. ALS4K_IOB_10_ADLIB_ADDR0 = 0x10,
  113. ALS4K_IOB_11_ADLIB_ADDR1 = 0x11,
  114. ALS4K_IOB_12_ADLIB_ADDR2 = 0x12,
  115. ALS4K_IOB_13_ADLIB_ADDR3 = 0x13,
  116. ALS4K_IOB_14_MIXER_INDEX = 0x14,
  117. ALS4K_IOB_15_MIXER_DATA = 0x15,
  118. ALS4K_IOB_16_ESP_RESET = 0x16,
  119. ALS4K_IOB_16_ACK_FOR_CR1E = 0x16, /* 2nd function */
  120. ALS4K_IOB_18_OPL_ADDR0 = 0x18,
  121. ALS4K_IOB_19_OPL_ADDR1 = 0x19,
  122. ALS4K_IOB_1A_ESP_RD_DATA = 0x1a,
  123. ALS4K_IOB_1C_ESP_CMD_DATA = 0x1c,
  124. ALS4K_IOB_1C_ESP_WR_STATUS = 0x1c, /* 2nd function */
  125. ALS4K_IOB_1E_ESP_RD_STATUS8 = 0x1e,
  126. ALS4K_IOB_1F_ESP_RD_STATUS16 = 0x1f,
  127. ALS4K_IOB_20_ESP_GAMEPORT_200 = 0x20,
  128. ALS4K_IOB_21_ESP_GAMEPORT_201 = 0x21,
  129. ALS4K_IOB_30_MIDI_DATA = 0x30,
  130. ALS4K_IOB_31_MIDI_STATUS = 0x31,
  131. ALS4K_IOB_31_MIDI_COMMAND = 0x31, /* 2nd function */
  132. };
  133. enum als4k_iobase_0e_t {
  134. ALS4K_IOB_0E_MPU_IRQ = 0x10,
  135. ALS4K_IOB_0E_CR1E_IRQ = 0x40,
  136. ALS4K_IOB_0E_SB_DMA_IRQ = 0x80,
  137. };
  138. enum als4k_gcr_t { /* all registers 32bit wide; SPECS_PAGE: 38 to 42 */
  139. ALS4K_GCR8C_MISC_CTRL = 0x8c,
  140. ALS4K_GCR90_TEST_MODE_REG = 0x90,
  141. ALS4K_GCR91_DMA0_ADDR = 0x91,
  142. ALS4K_GCR92_DMA0_MODE_COUNT = 0x92,
  143. ALS4K_GCR93_DMA1_ADDR = 0x93,
  144. ALS4K_GCR94_DMA1_MODE_COUNT = 0x94,
  145. ALS4K_GCR95_DMA3_ADDR = 0x95,
  146. ALS4K_GCR96_DMA3_MODE_COUNT = 0x96,
  147. ALS4K_GCR99_DMA_EMULATION_CTRL = 0x99,
  148. ALS4K_GCRA0_FIFO1_CURRENT_ADDR = 0xa0,
  149. ALS4K_GCRA1_FIFO1_STATUS_BYTECOUNT = 0xa1,
  150. ALS4K_GCRA2_FIFO2_PCIADDR = 0xa2,
  151. ALS4K_GCRA3_FIFO2_COUNT = 0xa3,
  152. ALS4K_GCRA4_FIFO2_CURRENT_ADDR = 0xa4,
  153. ALS4K_GCRA5_FIFO1_STATUS_BYTECOUNT = 0xa5,
  154. ALS4K_GCRA6_PM_CTRL = 0xa6,
  155. ALS4K_GCRA7_PCI_ACCESS_STORAGE = 0xa7,
  156. ALS4K_GCRA8_LEGACY_CFG1 = 0xa8,
  157. ALS4K_GCRA9_LEGACY_CFG2 = 0xa9,
  158. ALS4K_GCRFF_DUMMY_SCRATCH = 0xff,
  159. };
  160. enum als4k_gcr8c_t {
  161. ALS4K_GCR8C_IRQ_MASK_CTRL_ENABLE = 0x8000,
  162. ALS4K_GCR8C_CHIP_REV_MASK = 0xf0000
  163. };
  164. static inline void snd_als4k_iobase_writeb(unsigned long iobase,
  165. enum als4k_iobase_t reg,
  166. u8 val)
  167. {
  168. outb(val, iobase + reg);
  169. }
  170. static inline void snd_als4k_iobase_writel(unsigned long iobase,
  171. enum als4k_iobase_t reg,
  172. u32 val)
  173. {
  174. outl(val, iobase + reg);
  175. }
  176. static inline u8 snd_als4k_iobase_readb(unsigned long iobase,
  177. enum als4k_iobase_t reg)
  178. {
  179. return inb(iobase + reg);
  180. }
  181. static inline u32 snd_als4k_iobase_readl(unsigned long iobase,
  182. enum als4k_iobase_t reg)
  183. {
  184. return inl(iobase + reg);
  185. }
  186. static inline void snd_als4k_gcr_write_addr(unsigned long iobase,
  187. enum als4k_gcr_t reg,
  188. u32 val)
  189. {
  190. snd_als4k_iobase_writeb(iobase, ALS4K_IOB_0C_GCR_INDEX, reg);
  191. snd_als4k_iobase_writel(iobase, ALS4K_IOD_08_GCR_DATA, val);
  192. }
  193. static inline void snd_als4k_gcr_write(struct snd_sb *sb,
  194. enum als4k_gcr_t reg,
  195. u32 val)
  196. {
  197. snd_als4k_gcr_write_addr(sb->alt_port, reg, val);
  198. }
  199. static inline u32 snd_als4k_gcr_read_addr(unsigned long iobase,
  200. enum als4k_gcr_t reg)
  201. {
  202. /* SPECS_PAGE: 37/38 */
  203. snd_als4k_iobase_writeb(iobase, ALS4K_IOB_0C_GCR_INDEX, reg);
  204. return snd_als4k_iobase_readl(iobase, ALS4K_IOD_08_GCR_DATA);
  205. }
  206. static inline u32 snd_als4k_gcr_read(struct snd_sb *sb, enum als4k_gcr_t reg)
  207. {
  208. return snd_als4k_gcr_read_addr(sb->alt_port, reg);
  209. }
  210. enum als4k_cr_t { /* all registers 8bit wide; SPECS_PAGE: 20 to 23 */
  211. ALS4K_CR0_SB_CONFIG = 0x00,
  212. ALS4K_CR2_MISC_CONTROL = 0x02,
  213. ALS4K_CR3_CONFIGURATION = 0x03,
  214. ALS4K_CR17_FIFO_STATUS = 0x17,
  215. ALS4K_CR18_ESP_MAJOR_VERSION = 0x18,
  216. ALS4K_CR19_ESP_MINOR_VERSION = 0x19,
  217. ALS4K_CR1A_MPU401_UART_MODE_CONTROL = 0x1a,
  218. ALS4K_CR1C_FIFO2_BLOCK_LENGTH_LO = 0x1c,
  219. ALS4K_CR1D_FIFO2_BLOCK_LENGTH_HI = 0x1d,
  220. ALS4K_CR1E_FIFO2_CONTROL = 0x1e, /* secondary PCM FIFO (recording) */
  221. ALS4K_CR3A_MISC_CONTROL = 0x3a,
  222. ALS4K_CR3B_CRC32_BYTE0 = 0x3b, /* for testing, activate via CR3A */
  223. ALS4K_CR3C_CRC32_BYTE1 = 0x3c,
  224. ALS4K_CR3D_CRC32_BYTE2 = 0x3d,
  225. ALS4K_CR3E_CRC32_BYTE3 = 0x3e,
  226. };
  227. enum als4k_cr0_t {
  228. ALS4K_CR0_DMA_CONTIN_MODE_CTRL = 0x02, /* IRQ/FIFO controlled for 0/1 */
  229. ALS4K_CR0_DMA_90H_MODE_CTRL = 0x04, /* IRQ/FIFO controlled for 0/1 */
  230. ALS4K_CR0_MX80_81_REG_WRITE_ENABLE = 0x80,
  231. };
  232. static inline void snd_als4_cr_write(struct snd_sb *chip,
  233. enum als4k_cr_t reg,
  234. u8 data)
  235. {
  236. /* Control Register is reg | 0xc0 (bit 7, 6 set) on sbmixer_index
  237. * NOTE: assumes chip->mixer_lock to be locked externally already!
  238. * SPECS_PAGE: 6 */
  239. snd_sbmixer_write(chip, reg | 0xc0, data);
  240. }
  241. static inline u8 snd_als4_cr_read(struct snd_sb *chip,
  242. enum als4k_cr_t reg)
  243. {
  244. /* NOTE: assumes chip->mixer_lock to be locked externally already! */
  245. return snd_sbmixer_read(chip, reg | 0xc0);
  246. }
  247. static void snd_als4000_set_rate(struct snd_sb *chip, unsigned int rate)
  248. {
  249. if (!(chip->mode & SB_RATE_LOCK)) {
  250. snd_sbdsp_command(chip, SB_DSP_SAMPLE_RATE_OUT);
  251. snd_sbdsp_command(chip, rate>>8);
  252. snd_sbdsp_command(chip, rate);
  253. }
  254. }
  255. static inline void snd_als4000_set_capture_dma(struct snd_sb *chip,
  256. dma_addr_t addr, unsigned size)
  257. {
  258. /* SPECS_PAGE: 40 */
  259. snd_als4k_gcr_write(chip, ALS4K_GCRA2_FIFO2_PCIADDR, addr);
  260. snd_als4k_gcr_write(chip, ALS4K_GCRA3_FIFO2_COUNT, (size-1));
  261. }
  262. static inline void snd_als4000_set_playback_dma(struct snd_sb *chip,
  263. dma_addr_t addr,
  264. unsigned size)
  265. {
  266. /* SPECS_PAGE: 38 */
  267. snd_als4k_gcr_write(chip, ALS4K_GCR91_DMA0_ADDR, addr);
  268. snd_als4k_gcr_write(chip, ALS4K_GCR92_DMA0_MODE_COUNT,
  269. (size-1)|0x180000);
  270. }
  271. #define ALS4000_FORMAT_SIGNED (1<<0)
  272. #define ALS4000_FORMAT_16BIT (1<<1)
  273. #define ALS4000_FORMAT_STEREO (1<<2)
  274. static int snd_als4000_get_format(struct snd_pcm_runtime *runtime)
  275. {
  276. int result;
  277. result = 0;
  278. if (snd_pcm_format_signed(runtime->format))
  279. result |= ALS4000_FORMAT_SIGNED;
  280. if (snd_pcm_format_physical_width(runtime->format) == 16)
  281. result |= ALS4000_FORMAT_16BIT;
  282. if (runtime->channels > 1)
  283. result |= ALS4000_FORMAT_STEREO;
  284. return result;
  285. }
  286. /* structure for setting up playback */
  287. static const struct {
  288. unsigned char dsp_cmd, dma_on, dma_off, format;
  289. } playback_cmd_vals[]={
  290. /* ALS4000_FORMAT_U8_MONO */
  291. { SB_DSP4_OUT8_AI, SB_DSP_DMA8_ON, SB_DSP_DMA8_OFF, SB_DSP4_MODE_UNS_MONO },
  292. /* ALS4000_FORMAT_S8_MONO */
  293. { SB_DSP4_OUT8_AI, SB_DSP_DMA8_ON, SB_DSP_DMA8_OFF, SB_DSP4_MODE_SIGN_MONO },
  294. /* ALS4000_FORMAT_U16L_MONO */
  295. { SB_DSP4_OUT16_AI, SB_DSP_DMA16_ON, SB_DSP_DMA16_OFF, SB_DSP4_MODE_UNS_MONO },
  296. /* ALS4000_FORMAT_S16L_MONO */
  297. { SB_DSP4_OUT16_AI, SB_DSP_DMA16_ON, SB_DSP_DMA16_OFF, SB_DSP4_MODE_SIGN_MONO },
  298. /* ALS4000_FORMAT_U8_STEREO */
  299. { SB_DSP4_OUT8_AI, SB_DSP_DMA8_ON, SB_DSP_DMA8_OFF, SB_DSP4_MODE_UNS_STEREO },
  300. /* ALS4000_FORMAT_S8_STEREO */
  301. { SB_DSP4_OUT8_AI, SB_DSP_DMA8_ON, SB_DSP_DMA8_OFF, SB_DSP4_MODE_SIGN_STEREO },
  302. /* ALS4000_FORMAT_U16L_STEREO */
  303. { SB_DSP4_OUT16_AI, SB_DSP_DMA16_ON, SB_DSP_DMA16_OFF, SB_DSP4_MODE_UNS_STEREO },
  304. /* ALS4000_FORMAT_S16L_STEREO */
  305. { SB_DSP4_OUT16_AI, SB_DSP_DMA16_ON, SB_DSP_DMA16_OFF, SB_DSP4_MODE_SIGN_STEREO },
  306. };
  307. #define playback_cmd(chip) (playback_cmd_vals[(chip)->playback_format])
  308. /* structure for setting up capture */
  309. enum { CMD_WIDTH8=0x04, CMD_SIGNED=0x10, CMD_MONO=0x80, CMD_STEREO=0xA0 };
  310. static const unsigned char capture_cmd_vals[]=
  311. {
  312. CMD_WIDTH8|CMD_MONO, /* ALS4000_FORMAT_U8_MONO */
  313. CMD_WIDTH8|CMD_SIGNED|CMD_MONO, /* ALS4000_FORMAT_S8_MONO */
  314. CMD_MONO, /* ALS4000_FORMAT_U16L_MONO */
  315. CMD_SIGNED|CMD_MONO, /* ALS4000_FORMAT_S16L_MONO */
  316. CMD_WIDTH8|CMD_STEREO, /* ALS4000_FORMAT_U8_STEREO */
  317. CMD_WIDTH8|CMD_SIGNED|CMD_STEREO, /* ALS4000_FORMAT_S8_STEREO */
  318. CMD_STEREO, /* ALS4000_FORMAT_U16L_STEREO */
  319. CMD_SIGNED|CMD_STEREO, /* ALS4000_FORMAT_S16L_STEREO */
  320. };
  321. #define capture_cmd(chip) (capture_cmd_vals[(chip)->capture_format])
  322. static int snd_als4000_capture_prepare(struct snd_pcm_substream *substream)
  323. {
  324. struct snd_sb *chip = snd_pcm_substream_chip(substream);
  325. struct snd_pcm_runtime *runtime = substream->runtime;
  326. unsigned long size;
  327. unsigned count;
  328. chip->capture_format = snd_als4000_get_format(runtime);
  329. size = snd_pcm_lib_buffer_bytes(substream);
  330. count = snd_pcm_lib_period_bytes(substream);
  331. if (chip->capture_format & ALS4000_FORMAT_16BIT)
  332. count >>= 1;
  333. count--;
  334. spin_lock_irq(&chip->reg_lock);
  335. snd_als4000_set_rate(chip, runtime->rate);
  336. snd_als4000_set_capture_dma(chip, runtime->dma_addr, size);
  337. spin_unlock_irq(&chip->reg_lock);
  338. spin_lock_irq(&chip->mixer_lock);
  339. snd_als4_cr_write(chip, ALS4K_CR1C_FIFO2_BLOCK_LENGTH_LO, count & 0xff);
  340. snd_als4_cr_write(chip, ALS4K_CR1D_FIFO2_BLOCK_LENGTH_HI, count >> 8);
  341. spin_unlock_irq(&chip->mixer_lock);
  342. return 0;
  343. }
  344. static int snd_als4000_playback_prepare(struct snd_pcm_substream *substream)
  345. {
  346. struct snd_sb *chip = snd_pcm_substream_chip(substream);
  347. struct snd_pcm_runtime *runtime = substream->runtime;
  348. unsigned long size;
  349. unsigned count;
  350. chip->playback_format = snd_als4000_get_format(runtime);
  351. size = snd_pcm_lib_buffer_bytes(substream);
  352. count = snd_pcm_lib_period_bytes(substream);
  353. if (chip->playback_format & ALS4000_FORMAT_16BIT)
  354. count >>= 1;
  355. count--;
  356. /* FIXME: from second playback on, there's a lot more clicks and pops
  357. * involved here than on first playback. Fiddling with
  358. * tons of different settings didn't help (DMA, speaker on/off,
  359. * reordering, ...). Something seems to get enabled on playback
  360. * that I haven't found out how to disable again, which then causes
  361. * the switching pops to reach the speakers the next time here. */
  362. spin_lock_irq(&chip->reg_lock);
  363. snd_als4000_set_rate(chip, runtime->rate);
  364. snd_als4000_set_playback_dma(chip, runtime->dma_addr, size);
  365. /* SPEAKER_ON not needed, since dma_on seems to also enable speaker */
  366. /* snd_sbdsp_command(chip, SB_DSP_SPEAKER_ON); */
  367. snd_sbdsp_command(chip, playback_cmd(chip).dsp_cmd);
  368. snd_sbdsp_command(chip, playback_cmd(chip).format);
  369. snd_sbdsp_command(chip, count & 0xff);
  370. snd_sbdsp_command(chip, count >> 8);
  371. snd_sbdsp_command(chip, playback_cmd(chip).dma_off);
  372. spin_unlock_irq(&chip->reg_lock);
  373. return 0;
  374. }
  375. static int snd_als4000_capture_trigger(struct snd_pcm_substream *substream, int cmd)
  376. {
  377. struct snd_sb *chip = snd_pcm_substream_chip(substream);
  378. int result = 0;
  379. /* FIXME race condition in here!!!
  380. chip->mode non-atomic update gets consistently protected
  381. by reg_lock always, _except_ for this place!!
  382. Probably need to take reg_lock as outer (or inner??) lock, too.
  383. (or serialize both lock operations? probably not, though... - racy?)
  384. */
  385. spin_lock(&chip->mixer_lock);
  386. switch (cmd) {
  387. case SNDRV_PCM_TRIGGER_START:
  388. case SNDRV_PCM_TRIGGER_RESUME:
  389. chip->mode |= SB_RATE_LOCK_CAPTURE;
  390. snd_als4_cr_write(chip, ALS4K_CR1E_FIFO2_CONTROL,
  391. capture_cmd(chip));
  392. break;
  393. case SNDRV_PCM_TRIGGER_STOP:
  394. case SNDRV_PCM_TRIGGER_SUSPEND:
  395. chip->mode &= ~SB_RATE_LOCK_CAPTURE;
  396. snd_als4_cr_write(chip, ALS4K_CR1E_FIFO2_CONTROL,
  397. capture_cmd(chip));
  398. break;
  399. default:
  400. result = -EINVAL;
  401. break;
  402. }
  403. spin_unlock(&chip->mixer_lock);
  404. return result;
  405. }
  406. static int snd_als4000_playback_trigger(struct snd_pcm_substream *substream, int cmd)
  407. {
  408. struct snd_sb *chip = snd_pcm_substream_chip(substream);
  409. int result = 0;
  410. spin_lock(&chip->reg_lock);
  411. switch (cmd) {
  412. case SNDRV_PCM_TRIGGER_START:
  413. case SNDRV_PCM_TRIGGER_RESUME:
  414. chip->mode |= SB_RATE_LOCK_PLAYBACK;
  415. snd_sbdsp_command(chip, playback_cmd(chip).dma_on);
  416. break;
  417. case SNDRV_PCM_TRIGGER_STOP:
  418. case SNDRV_PCM_TRIGGER_SUSPEND:
  419. snd_sbdsp_command(chip, playback_cmd(chip).dma_off);
  420. chip->mode &= ~SB_RATE_LOCK_PLAYBACK;
  421. break;
  422. default:
  423. result = -EINVAL;
  424. break;
  425. }
  426. spin_unlock(&chip->reg_lock);
  427. return result;
  428. }
  429. static snd_pcm_uframes_t snd_als4000_capture_pointer(struct snd_pcm_substream *substream)
  430. {
  431. struct snd_sb *chip = snd_pcm_substream_chip(substream);
  432. unsigned int result;
  433. spin_lock(&chip->reg_lock);
  434. result = snd_als4k_gcr_read(chip, ALS4K_GCRA4_FIFO2_CURRENT_ADDR);
  435. spin_unlock(&chip->reg_lock);
  436. result &= 0xffff;
  437. return bytes_to_frames( substream->runtime, result );
  438. }
  439. static snd_pcm_uframes_t snd_als4000_playback_pointer(struct snd_pcm_substream *substream)
  440. {
  441. struct snd_sb *chip = snd_pcm_substream_chip(substream);
  442. unsigned result;
  443. spin_lock(&chip->reg_lock);
  444. result = snd_als4k_gcr_read(chip, ALS4K_GCRA0_FIFO1_CURRENT_ADDR);
  445. spin_unlock(&chip->reg_lock);
  446. result &= 0xffff;
  447. return bytes_to_frames( substream->runtime, result );
  448. }
  449. /* FIXME: this IRQ routine doesn't really support IRQ sharing (we always
  450. * return IRQ_HANDLED no matter whether we actually had an IRQ flag or not).
  451. * ALS4000a.PDF writes that while ACKing IRQ in PCI block will *not* ACK
  452. * the IRQ in the SB core, ACKing IRQ in SB block *will* ACK the PCI IRQ
  453. * register (alt_port + ALS4K_IOB_0E_IRQTYPE_SB_CR1E_MPU). Probably something
  454. * could be optimized here to query/write one register only...
  455. * And even if both registers need to be queried, then there's still the
  456. * question of whether it's actually correct to ACK PCI IRQ before reading
  457. * SB IRQ like we do now, since ALS4000a.PDF mentions that PCI IRQ will *clear*
  458. * SB IRQ status.
  459. * (hmm, SPECS_PAGE: 38 mentions it the other way around!)
  460. * And do we *really* need the lock here for *reading* SB_DSP4_IRQSTATUS??
  461. * */
  462. static irqreturn_t snd_als4000_interrupt(int irq, void *dev_id)
  463. {
  464. struct snd_sb *chip = dev_id;
  465. unsigned pci_irqstatus;
  466. unsigned sb_irqstatus;
  467. /* find out which bit of the ALS4000 PCI block produced the interrupt,
  468. SPECS_PAGE: 38, 5 */
  469. pci_irqstatus = snd_als4k_iobase_readb(chip->alt_port,
  470. ALS4K_IOB_0E_IRQTYPE_SB_CR1E_MPU);
  471. if ((pci_irqstatus & ALS4K_IOB_0E_SB_DMA_IRQ)
  472. && (chip->playback_substream)) /* playback */
  473. snd_pcm_period_elapsed(chip->playback_substream);
  474. if ((pci_irqstatus & ALS4K_IOB_0E_CR1E_IRQ)
  475. && (chip->capture_substream)) /* capturing */
  476. snd_pcm_period_elapsed(chip->capture_substream);
  477. if ((pci_irqstatus & ALS4K_IOB_0E_MPU_IRQ)
  478. && (chip->rmidi)) /* MPU401 interrupt */
  479. snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
  480. /* ACK the PCI block IRQ */
  481. snd_als4k_iobase_writeb(chip->alt_port,
  482. ALS4K_IOB_0E_IRQTYPE_SB_CR1E_MPU, pci_irqstatus);
  483. spin_lock(&chip->mixer_lock);
  484. /* SPECS_PAGE: 20 */
  485. sb_irqstatus = snd_sbmixer_read(chip, SB_DSP4_IRQSTATUS);
  486. spin_unlock(&chip->mixer_lock);
  487. if (sb_irqstatus & SB_IRQTYPE_8BIT)
  488. snd_sb_ack_8bit(chip);
  489. if (sb_irqstatus & SB_IRQTYPE_16BIT)
  490. snd_sb_ack_16bit(chip);
  491. if (sb_irqstatus & SB_IRQTYPE_MPUIN)
  492. inb(chip->mpu_port);
  493. if (sb_irqstatus & ALS4K_IRQTYPE_CR1E_DMA)
  494. snd_als4k_iobase_readb(chip->alt_port,
  495. ALS4K_IOB_16_ACK_FOR_CR1E);
  496. /* dev_dbg(chip->card->dev, "als4000: irq 0x%04x 0x%04x\n",
  497. pci_irqstatus, sb_irqstatus); */
  498. /* only ack the things we actually handled above */
  499. return IRQ_RETVAL(
  500. (pci_irqstatus & (ALS4K_IOB_0E_SB_DMA_IRQ|ALS4K_IOB_0E_CR1E_IRQ|
  501. ALS4K_IOB_0E_MPU_IRQ))
  502. || (sb_irqstatus & (SB_IRQTYPE_8BIT|SB_IRQTYPE_16BIT|
  503. SB_IRQTYPE_MPUIN|ALS4K_IRQTYPE_CR1E_DMA))
  504. );
  505. }
  506. /*****************************************************************/
  507. static const struct snd_pcm_hardware snd_als4000_playback =
  508. {
  509. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  510. SNDRV_PCM_INFO_MMAP_VALID),
  511. .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
  512. SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE, /* formats */
  513. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  514. .rate_min = 4000,
  515. .rate_max = 48000,
  516. .channels_min = 1,
  517. .channels_max = 2,
  518. .buffer_bytes_max = 65536,
  519. .period_bytes_min = 64,
  520. .period_bytes_max = 65536,
  521. .periods_min = 1,
  522. .periods_max = 1024,
  523. .fifo_size = 0
  524. };
  525. static const struct snd_pcm_hardware snd_als4000_capture =
  526. {
  527. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  528. SNDRV_PCM_INFO_MMAP_VALID),
  529. .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
  530. SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE, /* formats */
  531. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  532. .rate_min = 4000,
  533. .rate_max = 48000,
  534. .channels_min = 1,
  535. .channels_max = 2,
  536. .buffer_bytes_max = 65536,
  537. .period_bytes_min = 64,
  538. .period_bytes_max = 65536,
  539. .periods_min = 1,
  540. .periods_max = 1024,
  541. .fifo_size = 0
  542. };
  543. /*****************************************************************/
  544. static int snd_als4000_playback_open(struct snd_pcm_substream *substream)
  545. {
  546. struct snd_sb *chip = snd_pcm_substream_chip(substream);
  547. struct snd_pcm_runtime *runtime = substream->runtime;
  548. chip->playback_substream = substream;
  549. runtime->hw = snd_als4000_playback;
  550. return 0;
  551. }
  552. static int snd_als4000_playback_close(struct snd_pcm_substream *substream)
  553. {
  554. struct snd_sb *chip = snd_pcm_substream_chip(substream);
  555. chip->playback_substream = NULL;
  556. return 0;
  557. }
  558. static int snd_als4000_capture_open(struct snd_pcm_substream *substream)
  559. {
  560. struct snd_sb *chip = snd_pcm_substream_chip(substream);
  561. struct snd_pcm_runtime *runtime = substream->runtime;
  562. chip->capture_substream = substream;
  563. runtime->hw = snd_als4000_capture;
  564. return 0;
  565. }
  566. static int snd_als4000_capture_close(struct snd_pcm_substream *substream)
  567. {
  568. struct snd_sb *chip = snd_pcm_substream_chip(substream);
  569. chip->capture_substream = NULL;
  570. return 0;
  571. }
  572. /******************************************************************/
  573. static const struct snd_pcm_ops snd_als4000_playback_ops = {
  574. .open = snd_als4000_playback_open,
  575. .close = snd_als4000_playback_close,
  576. .prepare = snd_als4000_playback_prepare,
  577. .trigger = snd_als4000_playback_trigger,
  578. .pointer = snd_als4000_playback_pointer
  579. };
  580. static const struct snd_pcm_ops snd_als4000_capture_ops = {
  581. .open = snd_als4000_capture_open,
  582. .close = snd_als4000_capture_close,
  583. .prepare = snd_als4000_capture_prepare,
  584. .trigger = snd_als4000_capture_trigger,
  585. .pointer = snd_als4000_capture_pointer
  586. };
  587. static int snd_als4000_pcm(struct snd_sb *chip, int device)
  588. {
  589. struct snd_pcm *pcm;
  590. int err;
  591. err = snd_pcm_new(chip->card, "ALS4000 DSP", device, 1, 1, &pcm);
  592. if (err < 0)
  593. return err;
  594. pcm->private_data = chip;
  595. pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
  596. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_als4000_playback_ops);
  597. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_als4000_capture_ops);
  598. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  599. &chip->pci->dev, 64*1024, 64*1024);
  600. chip->pcm = pcm;
  601. return 0;
  602. }
  603. /******************************************************************/
  604. static void snd_als4000_set_addr(unsigned long iobase,
  605. unsigned int sb_io,
  606. unsigned int mpu_io,
  607. unsigned int opl_io,
  608. unsigned int game_io)
  609. {
  610. u32 cfg1 = 0;
  611. u32 cfg2 = 0;
  612. if (mpu_io > 0)
  613. cfg2 |= (mpu_io | 1) << 16;
  614. if (sb_io > 0)
  615. cfg2 |= (sb_io | 1);
  616. if (game_io > 0)
  617. cfg1 |= (game_io | 1) << 16;
  618. if (opl_io > 0)
  619. cfg1 |= (opl_io | 1);
  620. snd_als4k_gcr_write_addr(iobase, ALS4K_GCRA8_LEGACY_CFG1, cfg1);
  621. snd_als4k_gcr_write_addr(iobase, ALS4K_GCRA9_LEGACY_CFG2, cfg2);
  622. }
  623. static void snd_als4000_configure(struct snd_sb *chip)
  624. {
  625. u8 tmp;
  626. int i;
  627. /* do some more configuration */
  628. spin_lock_irq(&chip->mixer_lock);
  629. tmp = snd_als4_cr_read(chip, ALS4K_CR0_SB_CONFIG);
  630. snd_als4_cr_write(chip, ALS4K_CR0_SB_CONFIG,
  631. tmp|ALS4K_CR0_MX80_81_REG_WRITE_ENABLE);
  632. /* always select DMA channel 0, since we do not actually use DMA
  633. * SPECS_PAGE: 19/20 */
  634. snd_sbmixer_write(chip, SB_DSP4_DMASETUP, SB_DMASETUP_DMA0);
  635. snd_als4_cr_write(chip, ALS4K_CR0_SB_CONFIG,
  636. tmp & ~ALS4K_CR0_MX80_81_REG_WRITE_ENABLE);
  637. spin_unlock_irq(&chip->mixer_lock);
  638. spin_lock_irq(&chip->reg_lock);
  639. /* enable interrupts */
  640. snd_als4k_gcr_write(chip, ALS4K_GCR8C_MISC_CTRL,
  641. ALS4K_GCR8C_IRQ_MASK_CTRL_ENABLE);
  642. /* SPECS_PAGE: 39 */
  643. for (i = ALS4K_GCR91_DMA0_ADDR; i <= ALS4K_GCR96_DMA3_MODE_COUNT; ++i)
  644. snd_als4k_gcr_write(chip, i, 0);
  645. /* enable burst mode to prevent dropouts during high PCI bus usage */
  646. snd_als4k_gcr_write(chip, ALS4K_GCR99_DMA_EMULATION_CTRL,
  647. (snd_als4k_gcr_read(chip, ALS4K_GCR99_DMA_EMULATION_CTRL) & ~0x07) | 0x04);
  648. spin_unlock_irq(&chip->reg_lock);
  649. }
  650. #ifdef SUPPORT_JOYSTICK
  651. static int snd_als4000_create_gameport(struct snd_card_als4000 *acard, int dev)
  652. {
  653. struct gameport *gp;
  654. struct resource *r;
  655. int io_port;
  656. if (joystick_port[dev] == 0)
  657. return -ENODEV;
  658. if (joystick_port[dev] == 1) { /* auto-detect */
  659. for (io_port = 0x200; io_port <= 0x218; io_port += 8) {
  660. r = request_region(io_port, 8, "ALS4000 gameport");
  661. if (r)
  662. break;
  663. }
  664. } else {
  665. io_port = joystick_port[dev];
  666. r = request_region(io_port, 8, "ALS4000 gameport");
  667. }
  668. if (!r) {
  669. dev_warn(&acard->pci->dev, "cannot reserve joystick ports\n");
  670. return -EBUSY;
  671. }
  672. acard->gameport = gp = gameport_allocate_port();
  673. if (!gp) {
  674. dev_err(&acard->pci->dev, "cannot allocate memory for gameport\n");
  675. release_and_free_resource(r);
  676. return -ENOMEM;
  677. }
  678. gameport_set_name(gp, "ALS4000 Gameport");
  679. gameport_set_phys(gp, "pci%s/gameport0", pci_name(acard->pci));
  680. gameport_set_dev_parent(gp, &acard->pci->dev);
  681. gp->io = io_port;
  682. gameport_set_port_data(gp, r);
  683. /* Enable legacy joystick port */
  684. snd_als4000_set_addr(acard->iobase, 0, 0, 0, 1);
  685. gameport_register_port(acard->gameport);
  686. return 0;
  687. }
  688. static void snd_als4000_free_gameport(struct snd_card_als4000 *acard)
  689. {
  690. if (acard->gameport) {
  691. struct resource *r = gameport_get_port_data(acard->gameport);
  692. gameport_unregister_port(acard->gameport);
  693. acard->gameport = NULL;
  694. /* disable joystick */
  695. snd_als4000_set_addr(acard->iobase, 0, 0, 0, 0);
  696. release_and_free_resource(r);
  697. }
  698. }
  699. #else
  700. static inline int snd_als4000_create_gameport(struct snd_card_als4000 *acard, int dev) { return -ENOSYS; }
  701. static inline void snd_als4000_free_gameport(struct snd_card_als4000 *acard) { }
  702. #endif
  703. static void snd_card_als4000_free( struct snd_card *card )
  704. {
  705. struct snd_card_als4000 *acard = card->private_data;
  706. /* make sure that interrupts are disabled */
  707. snd_als4k_gcr_write_addr(acard->iobase, ALS4K_GCR8C_MISC_CTRL, 0);
  708. /* free resources */
  709. snd_als4000_free_gameport(acard);
  710. pci_release_regions(acard->pci);
  711. pci_disable_device(acard->pci);
  712. }
  713. static int snd_card_als4000_probe(struct pci_dev *pci,
  714. const struct pci_device_id *pci_id)
  715. {
  716. static int dev;
  717. struct snd_card *card;
  718. struct snd_card_als4000 *acard;
  719. unsigned long iobase;
  720. struct snd_sb *chip;
  721. struct snd_opl3 *opl3;
  722. unsigned short word;
  723. int err;
  724. if (dev >= SNDRV_CARDS)
  725. return -ENODEV;
  726. if (!enable[dev]) {
  727. dev++;
  728. return -ENOENT;
  729. }
  730. /* enable PCI device */
  731. if ((err = pci_enable_device(pci)) < 0) {
  732. return err;
  733. }
  734. /* check, if we can restrict PCI DMA transfers to 24 bits */
  735. if (dma_set_mask(&pci->dev, DMA_BIT_MASK(24)) < 0 ||
  736. dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(24)) < 0) {
  737. dev_err(&pci->dev, "architecture does not support 24bit PCI busmaster DMA\n");
  738. pci_disable_device(pci);
  739. return -ENXIO;
  740. }
  741. if ((err = pci_request_regions(pci, "ALS4000")) < 0) {
  742. pci_disable_device(pci);
  743. return err;
  744. }
  745. iobase = pci_resource_start(pci, 0);
  746. pci_read_config_word(pci, PCI_COMMAND, &word);
  747. pci_write_config_word(pci, PCI_COMMAND, word | PCI_COMMAND_IO);
  748. pci_set_master(pci);
  749. err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
  750. sizeof(*acard) /* private_data: acard */,
  751. &card);
  752. if (err < 0) {
  753. pci_release_regions(pci);
  754. pci_disable_device(pci);
  755. return err;
  756. }
  757. acard = card->private_data;
  758. acard->pci = pci;
  759. acard->iobase = iobase;
  760. card->private_free = snd_card_als4000_free;
  761. /* disable all legacy ISA stuff */
  762. snd_als4000_set_addr(acard->iobase, 0, 0, 0, 0);
  763. if ((err = snd_sbdsp_create(card,
  764. iobase + ALS4K_IOB_10_ADLIB_ADDR0,
  765. pci->irq,
  766. /* internally registered as IRQF_SHARED in case of ALS4000 SB */
  767. snd_als4000_interrupt,
  768. -1,
  769. -1,
  770. SB_HW_ALS4000,
  771. &chip)) < 0) {
  772. goto out_err;
  773. }
  774. acard->chip = chip;
  775. chip->pci = pci;
  776. chip->alt_port = iobase;
  777. snd_als4000_configure(chip);
  778. strcpy(card->driver, "ALS4000");
  779. strcpy(card->shortname, "Avance Logic ALS4000");
  780. sprintf(card->longname, "%s at 0x%lx, irq %i",
  781. card->shortname, chip->alt_port, chip->irq);
  782. if ((err = snd_mpu401_uart_new( card, 0, MPU401_HW_ALS4000,
  783. iobase + ALS4K_IOB_30_MIDI_DATA,
  784. MPU401_INFO_INTEGRATED |
  785. MPU401_INFO_IRQ_HOOK,
  786. -1, &chip->rmidi)) < 0) {
  787. dev_err(&pci->dev, "no MPU-401 device at 0x%lx?\n",
  788. iobase + ALS4K_IOB_30_MIDI_DATA);
  789. goto out_err;
  790. }
  791. /* FIXME: ALS4000 has interesting MPU401 configuration features
  792. * at ALS4K_CR1A_MPU401_UART_MODE_CONTROL
  793. * (pass-thru / UART switching, fast MIDI clock, etc.),
  794. * however there doesn't seem to be an ALSA API for this...
  795. * SPECS_PAGE: 21 */
  796. if ((err = snd_als4000_pcm(chip, 0)) < 0) {
  797. goto out_err;
  798. }
  799. if ((err = snd_sbmixer_new(chip)) < 0) {
  800. goto out_err;
  801. }
  802. if (snd_opl3_create(card,
  803. iobase + ALS4K_IOB_10_ADLIB_ADDR0,
  804. iobase + ALS4K_IOB_12_ADLIB_ADDR2,
  805. OPL3_HW_AUTO, 1, &opl3) < 0) {
  806. dev_err(&pci->dev, "no OPL device at 0x%lx-0x%lx?\n",
  807. iobase + ALS4K_IOB_10_ADLIB_ADDR0,
  808. iobase + ALS4K_IOB_12_ADLIB_ADDR2);
  809. } else {
  810. if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
  811. goto out_err;
  812. }
  813. }
  814. snd_als4000_create_gameport(acard, dev);
  815. if ((err = snd_card_register(card)) < 0) {
  816. goto out_err;
  817. }
  818. pci_set_drvdata(pci, card);
  819. dev++;
  820. err = 0;
  821. goto out;
  822. out_err:
  823. snd_card_free(card);
  824. out:
  825. return err;
  826. }
  827. static void snd_card_als4000_remove(struct pci_dev *pci)
  828. {
  829. snd_card_free(pci_get_drvdata(pci));
  830. }
  831. #ifdef CONFIG_PM_SLEEP
  832. static int snd_als4000_suspend(struct device *dev)
  833. {
  834. struct snd_card *card = dev_get_drvdata(dev);
  835. struct snd_card_als4000 *acard = card->private_data;
  836. struct snd_sb *chip = acard->chip;
  837. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  838. snd_sbmixer_suspend(chip);
  839. return 0;
  840. }
  841. static int snd_als4000_resume(struct device *dev)
  842. {
  843. struct snd_card *card = dev_get_drvdata(dev);
  844. struct snd_card_als4000 *acard = card->private_data;
  845. struct snd_sb *chip = acard->chip;
  846. snd_als4000_configure(chip);
  847. snd_sbdsp_reset(chip);
  848. snd_sbmixer_resume(chip);
  849. #ifdef SUPPORT_JOYSTICK
  850. if (acard->gameport)
  851. snd_als4000_set_addr(acard->iobase, 0, 0, 0, 1);
  852. #endif
  853. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  854. return 0;
  855. }
  856. static SIMPLE_DEV_PM_OPS(snd_als4000_pm, snd_als4000_suspend, snd_als4000_resume);
  857. #define SND_ALS4000_PM_OPS &snd_als4000_pm
  858. #else
  859. #define SND_ALS4000_PM_OPS NULL
  860. #endif /* CONFIG_PM_SLEEP */
  861. static struct pci_driver als4000_driver = {
  862. .name = KBUILD_MODNAME,
  863. .id_table = snd_als4000_ids,
  864. .probe = snd_card_als4000_probe,
  865. .remove = snd_card_als4000_remove,
  866. .driver = {
  867. .pm = SND_ALS4000_PM_OPS,
  868. },
  869. };
  870. module_pci_driver(als4000_driver);