ad1889.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Analog Devices 1889 audio driver
  3. *
  4. * This is a driver for the AD1889 PCI audio chipset found
  5. * on the HP PA-RISC [BCJ]-xxx0 workstations.
  6. *
  7. * Copyright (C) 2004-2005, Kyle McMartin <kyle@parisc-linux.org>
  8. * Copyright (C) 2005, Thibaut Varene <varenet@parisc-linux.org>
  9. * Based on the OSS AD1889 driver by Randolph Chung <tausq@debian.org>
  10. *
  11. * TODO:
  12. * Do we need to take care of CCS register?
  13. * Maybe we could use finer grained locking (separate locks for pb/cap)?
  14. * Wishlist:
  15. * Control Interface (mixer) support
  16. * Better AC97 support (VSR...)?
  17. * PM support
  18. * MIDI support
  19. * Game Port support
  20. * SG DMA support (this will need *a lot* of work)
  21. */
  22. #include <linux/init.h>
  23. #include <linux/pci.h>
  24. #include <linux/dma-mapping.h>
  25. #include <linux/slab.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/compiler.h>
  28. #include <linux/delay.h>
  29. #include <linux/module.h>
  30. #include <linux/io.h>
  31. #include <sound/core.h>
  32. #include <sound/pcm.h>
  33. #include <sound/initval.h>
  34. #include <sound/ac97_codec.h>
  35. #include "ad1889.h"
  36. #include "ac97/ac97_id.h"
  37. #define AD1889_DRVVER "Version: 1.7"
  38. MODULE_AUTHOR("Kyle McMartin <kyle@parisc-linux.org>, Thibaut Varene <t-bone@parisc-linux.org>");
  39. MODULE_DESCRIPTION("Analog Devices AD1889 ALSA sound driver");
  40. MODULE_LICENSE("GPL");
  41. MODULE_SUPPORTED_DEVICE("{{Analog Devices,AD1889}}");
  42. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  43. module_param_array(index, int, NULL, 0444);
  44. MODULE_PARM_DESC(index, "Index value for the AD1889 soundcard.");
  45. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  46. module_param_array(id, charp, NULL, 0444);
  47. MODULE_PARM_DESC(id, "ID string for the AD1889 soundcard.");
  48. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  49. module_param_array(enable, bool, NULL, 0444);
  50. MODULE_PARM_DESC(enable, "Enable AD1889 soundcard.");
  51. static char *ac97_quirk[SNDRV_CARDS];
  52. module_param_array(ac97_quirk, charp, NULL, 0444);
  53. MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
  54. #define DEVNAME "ad1889"
  55. #define PFX DEVNAME ": "
  56. /* keep track of some hw registers */
  57. struct ad1889_register_state {
  58. u16 reg; /* reg setup */
  59. u32 addr; /* dma base address */
  60. unsigned long size; /* DMA buffer size */
  61. };
  62. struct snd_ad1889 {
  63. struct snd_card *card;
  64. struct pci_dev *pci;
  65. int irq;
  66. unsigned long bar;
  67. void __iomem *iobase;
  68. struct snd_ac97 *ac97;
  69. struct snd_ac97_bus *ac97_bus;
  70. struct snd_pcm *pcm;
  71. struct snd_info_entry *proc;
  72. struct snd_pcm_substream *psubs;
  73. struct snd_pcm_substream *csubs;
  74. /* playback register state */
  75. struct ad1889_register_state wave;
  76. struct ad1889_register_state ramc;
  77. spinlock_t lock;
  78. };
  79. static inline u16
  80. ad1889_readw(struct snd_ad1889 *chip, unsigned reg)
  81. {
  82. return readw(chip->iobase + reg);
  83. }
  84. static inline void
  85. ad1889_writew(struct snd_ad1889 *chip, unsigned reg, u16 val)
  86. {
  87. writew(val, chip->iobase + reg);
  88. }
  89. static inline u32
  90. ad1889_readl(struct snd_ad1889 *chip, unsigned reg)
  91. {
  92. return readl(chip->iobase + reg);
  93. }
  94. static inline void
  95. ad1889_writel(struct snd_ad1889 *chip, unsigned reg, u32 val)
  96. {
  97. writel(val, chip->iobase + reg);
  98. }
  99. static inline void
  100. ad1889_unmute(struct snd_ad1889 *chip)
  101. {
  102. u16 st;
  103. st = ad1889_readw(chip, AD_DS_WADA) &
  104. ~(AD_DS_WADA_RWAM | AD_DS_WADA_LWAM);
  105. ad1889_writew(chip, AD_DS_WADA, st);
  106. ad1889_readw(chip, AD_DS_WADA);
  107. }
  108. static inline void
  109. ad1889_mute(struct snd_ad1889 *chip)
  110. {
  111. u16 st;
  112. st = ad1889_readw(chip, AD_DS_WADA) | AD_DS_WADA_RWAM | AD_DS_WADA_LWAM;
  113. ad1889_writew(chip, AD_DS_WADA, st);
  114. ad1889_readw(chip, AD_DS_WADA);
  115. }
  116. static inline void
  117. ad1889_load_adc_buffer_address(struct snd_ad1889 *chip, u32 address)
  118. {
  119. ad1889_writel(chip, AD_DMA_ADCBA, address);
  120. ad1889_writel(chip, AD_DMA_ADCCA, address);
  121. }
  122. static inline void
  123. ad1889_load_adc_buffer_count(struct snd_ad1889 *chip, u32 count)
  124. {
  125. ad1889_writel(chip, AD_DMA_ADCBC, count);
  126. ad1889_writel(chip, AD_DMA_ADCCC, count);
  127. }
  128. static inline void
  129. ad1889_load_adc_interrupt_count(struct snd_ad1889 *chip, u32 count)
  130. {
  131. ad1889_writel(chip, AD_DMA_ADCIB, count);
  132. ad1889_writel(chip, AD_DMA_ADCIC, count);
  133. }
  134. static inline void
  135. ad1889_load_wave_buffer_address(struct snd_ad1889 *chip, u32 address)
  136. {
  137. ad1889_writel(chip, AD_DMA_WAVBA, address);
  138. ad1889_writel(chip, AD_DMA_WAVCA, address);
  139. }
  140. static inline void
  141. ad1889_load_wave_buffer_count(struct snd_ad1889 *chip, u32 count)
  142. {
  143. ad1889_writel(chip, AD_DMA_WAVBC, count);
  144. ad1889_writel(chip, AD_DMA_WAVCC, count);
  145. }
  146. static inline void
  147. ad1889_load_wave_interrupt_count(struct snd_ad1889 *chip, u32 count)
  148. {
  149. ad1889_writel(chip, AD_DMA_WAVIB, count);
  150. ad1889_writel(chip, AD_DMA_WAVIC, count);
  151. }
  152. static void
  153. ad1889_channel_reset(struct snd_ad1889 *chip, unsigned int channel)
  154. {
  155. u16 reg;
  156. if (channel & AD_CHAN_WAV) {
  157. /* Disable wave channel */
  158. reg = ad1889_readw(chip, AD_DS_WSMC) & ~AD_DS_WSMC_WAEN;
  159. ad1889_writew(chip, AD_DS_WSMC, reg);
  160. chip->wave.reg = reg;
  161. /* disable IRQs */
  162. reg = ad1889_readw(chip, AD_DMA_WAV);
  163. reg &= AD_DMA_IM_DIS;
  164. reg &= ~AD_DMA_LOOP;
  165. ad1889_writew(chip, AD_DMA_WAV, reg);
  166. /* clear IRQ and address counters and pointers */
  167. ad1889_load_wave_buffer_address(chip, 0x0);
  168. ad1889_load_wave_buffer_count(chip, 0x0);
  169. ad1889_load_wave_interrupt_count(chip, 0x0);
  170. /* flush */
  171. ad1889_readw(chip, AD_DMA_WAV);
  172. }
  173. if (channel & AD_CHAN_ADC) {
  174. /* Disable ADC channel */
  175. reg = ad1889_readw(chip, AD_DS_RAMC) & ~AD_DS_RAMC_ADEN;
  176. ad1889_writew(chip, AD_DS_RAMC, reg);
  177. chip->ramc.reg = reg;
  178. reg = ad1889_readw(chip, AD_DMA_ADC);
  179. reg &= AD_DMA_IM_DIS;
  180. reg &= ~AD_DMA_LOOP;
  181. ad1889_writew(chip, AD_DMA_ADC, reg);
  182. ad1889_load_adc_buffer_address(chip, 0x0);
  183. ad1889_load_adc_buffer_count(chip, 0x0);
  184. ad1889_load_adc_interrupt_count(chip, 0x0);
  185. /* flush */
  186. ad1889_readw(chip, AD_DMA_ADC);
  187. }
  188. }
  189. static u16
  190. snd_ad1889_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
  191. {
  192. struct snd_ad1889 *chip = ac97->private_data;
  193. return ad1889_readw(chip, AD_AC97_BASE + reg);
  194. }
  195. static void
  196. snd_ad1889_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
  197. {
  198. struct snd_ad1889 *chip = ac97->private_data;
  199. ad1889_writew(chip, AD_AC97_BASE + reg, val);
  200. }
  201. static int
  202. snd_ad1889_ac97_ready(struct snd_ad1889 *chip)
  203. {
  204. int retry = 400; /* average needs 352 msec */
  205. while (!(ad1889_readw(chip, AD_AC97_ACIC) & AD_AC97_ACIC_ACRDY)
  206. && --retry)
  207. usleep_range(1000, 2000);
  208. if (!retry) {
  209. dev_err(chip->card->dev, "[%s] Link is not ready.\n",
  210. __func__);
  211. return -EIO;
  212. }
  213. dev_dbg(chip->card->dev, "[%s] ready after %d ms\n", __func__, 400 - retry);
  214. return 0;
  215. }
  216. static const struct snd_pcm_hardware snd_ad1889_playback_hw = {
  217. .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  218. SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BLOCK_TRANSFER,
  219. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  220. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  221. .rate_min = 8000, /* docs say 7000, but we're lazy */
  222. .rate_max = 48000,
  223. .channels_min = 1,
  224. .channels_max = 2,
  225. .buffer_bytes_max = BUFFER_BYTES_MAX,
  226. .period_bytes_min = PERIOD_BYTES_MIN,
  227. .period_bytes_max = PERIOD_BYTES_MAX,
  228. .periods_min = PERIODS_MIN,
  229. .periods_max = PERIODS_MAX,
  230. /*.fifo_size = 0,*/
  231. };
  232. static const struct snd_pcm_hardware snd_ad1889_capture_hw = {
  233. .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  234. SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BLOCK_TRANSFER,
  235. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  236. .rates = SNDRV_PCM_RATE_48000,
  237. .rate_min = 48000, /* docs say we could to VSR, but we're lazy */
  238. .rate_max = 48000,
  239. .channels_min = 1,
  240. .channels_max = 2,
  241. .buffer_bytes_max = BUFFER_BYTES_MAX,
  242. .period_bytes_min = PERIOD_BYTES_MIN,
  243. .period_bytes_max = PERIOD_BYTES_MAX,
  244. .periods_min = PERIODS_MIN,
  245. .periods_max = PERIODS_MAX,
  246. /*.fifo_size = 0,*/
  247. };
  248. static int
  249. snd_ad1889_playback_open(struct snd_pcm_substream *ss)
  250. {
  251. struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
  252. struct snd_pcm_runtime *rt = ss->runtime;
  253. chip->psubs = ss;
  254. rt->hw = snd_ad1889_playback_hw;
  255. return 0;
  256. }
  257. static int
  258. snd_ad1889_capture_open(struct snd_pcm_substream *ss)
  259. {
  260. struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
  261. struct snd_pcm_runtime *rt = ss->runtime;
  262. chip->csubs = ss;
  263. rt->hw = snd_ad1889_capture_hw;
  264. return 0;
  265. }
  266. static int
  267. snd_ad1889_playback_close(struct snd_pcm_substream *ss)
  268. {
  269. struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
  270. chip->psubs = NULL;
  271. return 0;
  272. }
  273. static int
  274. snd_ad1889_capture_close(struct snd_pcm_substream *ss)
  275. {
  276. struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
  277. chip->csubs = NULL;
  278. return 0;
  279. }
  280. static int
  281. snd_ad1889_playback_prepare(struct snd_pcm_substream *ss)
  282. {
  283. struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
  284. struct snd_pcm_runtime *rt = ss->runtime;
  285. unsigned int size = snd_pcm_lib_buffer_bytes(ss);
  286. unsigned int count = snd_pcm_lib_period_bytes(ss);
  287. u16 reg;
  288. ad1889_channel_reset(chip, AD_CHAN_WAV);
  289. reg = ad1889_readw(chip, AD_DS_WSMC);
  290. /* Mask out 16-bit / Stereo */
  291. reg &= ~(AD_DS_WSMC_WA16 | AD_DS_WSMC_WAST);
  292. if (snd_pcm_format_width(rt->format) == 16)
  293. reg |= AD_DS_WSMC_WA16;
  294. if (rt->channels > 1)
  295. reg |= AD_DS_WSMC_WAST;
  296. /* let's make sure we don't clobber ourselves */
  297. spin_lock_irq(&chip->lock);
  298. chip->wave.size = size;
  299. chip->wave.reg = reg;
  300. chip->wave.addr = rt->dma_addr;
  301. ad1889_writew(chip, AD_DS_WSMC, chip->wave.reg);
  302. /* Set sample rates on the codec */
  303. ad1889_writew(chip, AD_DS_WAS, rt->rate);
  304. /* Set up DMA */
  305. ad1889_load_wave_buffer_address(chip, chip->wave.addr);
  306. ad1889_load_wave_buffer_count(chip, size);
  307. ad1889_load_wave_interrupt_count(chip, count);
  308. /* writes flush */
  309. ad1889_readw(chip, AD_DS_WSMC);
  310. spin_unlock_irq(&chip->lock);
  311. dev_dbg(chip->card->dev,
  312. "prepare playback: addr = 0x%x, count = %u, size = %u, reg = 0x%x, rate = %u\n",
  313. chip->wave.addr, count, size, reg, rt->rate);
  314. return 0;
  315. }
  316. static int
  317. snd_ad1889_capture_prepare(struct snd_pcm_substream *ss)
  318. {
  319. struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
  320. struct snd_pcm_runtime *rt = ss->runtime;
  321. unsigned int size = snd_pcm_lib_buffer_bytes(ss);
  322. unsigned int count = snd_pcm_lib_period_bytes(ss);
  323. u16 reg;
  324. ad1889_channel_reset(chip, AD_CHAN_ADC);
  325. reg = ad1889_readw(chip, AD_DS_RAMC);
  326. /* Mask out 16-bit / Stereo */
  327. reg &= ~(AD_DS_RAMC_AD16 | AD_DS_RAMC_ADST);
  328. if (snd_pcm_format_width(rt->format) == 16)
  329. reg |= AD_DS_RAMC_AD16;
  330. if (rt->channels > 1)
  331. reg |= AD_DS_RAMC_ADST;
  332. /* let's make sure we don't clobber ourselves */
  333. spin_lock_irq(&chip->lock);
  334. chip->ramc.size = size;
  335. chip->ramc.reg = reg;
  336. chip->ramc.addr = rt->dma_addr;
  337. ad1889_writew(chip, AD_DS_RAMC, chip->ramc.reg);
  338. /* Set up DMA */
  339. ad1889_load_adc_buffer_address(chip, chip->ramc.addr);
  340. ad1889_load_adc_buffer_count(chip, size);
  341. ad1889_load_adc_interrupt_count(chip, count);
  342. /* writes flush */
  343. ad1889_readw(chip, AD_DS_RAMC);
  344. spin_unlock_irq(&chip->lock);
  345. dev_dbg(chip->card->dev,
  346. "prepare capture: addr = 0x%x, count = %u, size = %u, reg = 0x%x, rate = %u\n",
  347. chip->ramc.addr, count, size, reg, rt->rate);
  348. return 0;
  349. }
  350. /* this is called in atomic context with IRQ disabled.
  351. Must be as fast as possible and not sleep.
  352. DMA should be *triggered* by this call.
  353. The WSMC "WAEN" bit triggers DMA Wave On/Off */
  354. static int
  355. snd_ad1889_playback_trigger(struct snd_pcm_substream *ss, int cmd)
  356. {
  357. u16 wsmc;
  358. struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
  359. wsmc = ad1889_readw(chip, AD_DS_WSMC);
  360. switch (cmd) {
  361. case SNDRV_PCM_TRIGGER_START:
  362. /* enable DMA loop & interrupts */
  363. ad1889_writew(chip, AD_DMA_WAV, AD_DMA_LOOP | AD_DMA_IM_CNT);
  364. wsmc |= AD_DS_WSMC_WAEN;
  365. /* 1 to clear CHSS bit */
  366. ad1889_writel(chip, AD_DMA_CHSS, AD_DMA_CHSS_WAVS);
  367. ad1889_unmute(chip);
  368. break;
  369. case SNDRV_PCM_TRIGGER_STOP:
  370. ad1889_mute(chip);
  371. wsmc &= ~AD_DS_WSMC_WAEN;
  372. break;
  373. default:
  374. snd_BUG();
  375. return -EINVAL;
  376. }
  377. chip->wave.reg = wsmc;
  378. ad1889_writew(chip, AD_DS_WSMC, wsmc);
  379. ad1889_readw(chip, AD_DS_WSMC); /* flush */
  380. /* reset the chip when STOP - will disable IRQs */
  381. if (cmd == SNDRV_PCM_TRIGGER_STOP)
  382. ad1889_channel_reset(chip, AD_CHAN_WAV);
  383. return 0;
  384. }
  385. /* this is called in atomic context with IRQ disabled.
  386. Must be as fast as possible and not sleep.
  387. DMA should be *triggered* by this call.
  388. The RAMC "ADEN" bit triggers DMA ADC On/Off */
  389. static int
  390. snd_ad1889_capture_trigger(struct snd_pcm_substream *ss, int cmd)
  391. {
  392. u16 ramc;
  393. struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
  394. ramc = ad1889_readw(chip, AD_DS_RAMC);
  395. switch (cmd) {
  396. case SNDRV_PCM_TRIGGER_START:
  397. /* enable DMA loop & interrupts */
  398. ad1889_writew(chip, AD_DMA_ADC, AD_DMA_LOOP | AD_DMA_IM_CNT);
  399. ramc |= AD_DS_RAMC_ADEN;
  400. /* 1 to clear CHSS bit */
  401. ad1889_writel(chip, AD_DMA_CHSS, AD_DMA_CHSS_ADCS);
  402. break;
  403. case SNDRV_PCM_TRIGGER_STOP:
  404. ramc &= ~AD_DS_RAMC_ADEN;
  405. break;
  406. default:
  407. return -EINVAL;
  408. }
  409. chip->ramc.reg = ramc;
  410. ad1889_writew(chip, AD_DS_RAMC, ramc);
  411. ad1889_readw(chip, AD_DS_RAMC); /* flush */
  412. /* reset the chip when STOP - will disable IRQs */
  413. if (cmd == SNDRV_PCM_TRIGGER_STOP)
  414. ad1889_channel_reset(chip, AD_CHAN_ADC);
  415. return 0;
  416. }
  417. /* Called in atomic context with IRQ disabled */
  418. static snd_pcm_uframes_t
  419. snd_ad1889_playback_pointer(struct snd_pcm_substream *ss)
  420. {
  421. size_t ptr = 0;
  422. struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
  423. if (unlikely(!(chip->wave.reg & AD_DS_WSMC_WAEN)))
  424. return 0;
  425. ptr = ad1889_readl(chip, AD_DMA_WAVCA);
  426. ptr -= chip->wave.addr;
  427. if (snd_BUG_ON(ptr >= chip->wave.size))
  428. return 0;
  429. return bytes_to_frames(ss->runtime, ptr);
  430. }
  431. /* Called in atomic context with IRQ disabled */
  432. static snd_pcm_uframes_t
  433. snd_ad1889_capture_pointer(struct snd_pcm_substream *ss)
  434. {
  435. size_t ptr = 0;
  436. struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
  437. if (unlikely(!(chip->ramc.reg & AD_DS_RAMC_ADEN)))
  438. return 0;
  439. ptr = ad1889_readl(chip, AD_DMA_ADCCA);
  440. ptr -= chip->ramc.addr;
  441. if (snd_BUG_ON(ptr >= chip->ramc.size))
  442. return 0;
  443. return bytes_to_frames(ss->runtime, ptr);
  444. }
  445. static const struct snd_pcm_ops snd_ad1889_playback_ops = {
  446. .open = snd_ad1889_playback_open,
  447. .close = snd_ad1889_playback_close,
  448. .prepare = snd_ad1889_playback_prepare,
  449. .trigger = snd_ad1889_playback_trigger,
  450. .pointer = snd_ad1889_playback_pointer,
  451. };
  452. static const struct snd_pcm_ops snd_ad1889_capture_ops = {
  453. .open = snd_ad1889_capture_open,
  454. .close = snd_ad1889_capture_close,
  455. .prepare = snd_ad1889_capture_prepare,
  456. .trigger = snd_ad1889_capture_trigger,
  457. .pointer = snd_ad1889_capture_pointer,
  458. };
  459. static irqreturn_t
  460. snd_ad1889_interrupt(int irq, void *dev_id)
  461. {
  462. unsigned long st;
  463. struct snd_ad1889 *chip = dev_id;
  464. st = ad1889_readl(chip, AD_DMA_DISR);
  465. /* clear ISR */
  466. ad1889_writel(chip, AD_DMA_DISR, st);
  467. st &= AD_INTR_MASK;
  468. if (unlikely(!st))
  469. return IRQ_NONE;
  470. if (st & (AD_DMA_DISR_PMAI|AD_DMA_DISR_PTAI))
  471. dev_dbg(chip->card->dev,
  472. "Unexpected master or target abort interrupt!\n");
  473. if ((st & AD_DMA_DISR_WAVI) && chip->psubs)
  474. snd_pcm_period_elapsed(chip->psubs);
  475. if ((st & AD_DMA_DISR_ADCI) && chip->csubs)
  476. snd_pcm_period_elapsed(chip->csubs);
  477. return IRQ_HANDLED;
  478. }
  479. static int
  480. snd_ad1889_pcm_init(struct snd_ad1889 *chip, int device)
  481. {
  482. int err;
  483. struct snd_pcm *pcm;
  484. err = snd_pcm_new(chip->card, chip->card->driver, device, 1, 1, &pcm);
  485. if (err < 0)
  486. return err;
  487. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  488. &snd_ad1889_playback_ops);
  489. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  490. &snd_ad1889_capture_ops);
  491. pcm->private_data = chip;
  492. pcm->info_flags = 0;
  493. strcpy(pcm->name, chip->card->shortname);
  494. chip->pcm = pcm;
  495. chip->psubs = NULL;
  496. chip->csubs = NULL;
  497. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
  498. BUFFER_BYTES_MAX / 2, BUFFER_BYTES_MAX);
  499. return 0;
  500. }
  501. static void
  502. snd_ad1889_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
  503. {
  504. struct snd_ad1889 *chip = entry->private_data;
  505. u16 reg;
  506. int tmp;
  507. reg = ad1889_readw(chip, AD_DS_WSMC);
  508. snd_iprintf(buffer, "Wave output: %s\n",
  509. (reg & AD_DS_WSMC_WAEN) ? "enabled" : "disabled");
  510. snd_iprintf(buffer, "Wave Channels: %s\n",
  511. (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono");
  512. snd_iprintf(buffer, "Wave Quality: %d-bit linear\n",
  513. (reg & AD_DS_WSMC_WA16) ? 16 : 8);
  514. /* WARQ is at offset 12 */
  515. tmp = (reg & AD_DS_WSMC_WARQ) ?
  516. ((((reg & AD_DS_WSMC_WARQ) >> 12) & 0x01) ? 12 : 18) : 4;
  517. tmp /= (reg & AD_DS_WSMC_WAST) ? 2 : 1;
  518. snd_iprintf(buffer, "Wave FIFO: %d %s words\n\n", tmp,
  519. (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono");
  520. snd_iprintf(buffer, "Synthesis output: %s\n",
  521. reg & AD_DS_WSMC_SYEN ? "enabled" : "disabled");
  522. /* SYRQ is at offset 4 */
  523. tmp = (reg & AD_DS_WSMC_SYRQ) ?
  524. ((((reg & AD_DS_WSMC_SYRQ) >> 4) & 0x01) ? 12 : 18) : 4;
  525. tmp /= (reg & AD_DS_WSMC_WAST) ? 2 : 1;
  526. snd_iprintf(buffer, "Synthesis FIFO: %d %s words\n\n", tmp,
  527. (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono");
  528. reg = ad1889_readw(chip, AD_DS_RAMC);
  529. snd_iprintf(buffer, "ADC input: %s\n",
  530. (reg & AD_DS_RAMC_ADEN) ? "enabled" : "disabled");
  531. snd_iprintf(buffer, "ADC Channels: %s\n",
  532. (reg & AD_DS_RAMC_ADST) ? "stereo" : "mono");
  533. snd_iprintf(buffer, "ADC Quality: %d-bit linear\n",
  534. (reg & AD_DS_RAMC_AD16) ? 16 : 8);
  535. /* ACRQ is at offset 4 */
  536. tmp = (reg & AD_DS_RAMC_ACRQ) ?
  537. ((((reg & AD_DS_RAMC_ACRQ) >> 4) & 0x01) ? 12 : 18) : 4;
  538. tmp /= (reg & AD_DS_RAMC_ADST) ? 2 : 1;
  539. snd_iprintf(buffer, "ADC FIFO: %d %s words\n\n", tmp,
  540. (reg & AD_DS_RAMC_ADST) ? "stereo" : "mono");
  541. snd_iprintf(buffer, "Resampler input: %s\n",
  542. reg & AD_DS_RAMC_REEN ? "enabled" : "disabled");
  543. /* RERQ is at offset 12 */
  544. tmp = (reg & AD_DS_RAMC_RERQ) ?
  545. ((((reg & AD_DS_RAMC_RERQ) >> 12) & 0x01) ? 12 : 18) : 4;
  546. tmp /= (reg & AD_DS_RAMC_ADST) ? 2 : 1;
  547. snd_iprintf(buffer, "Resampler FIFO: %d %s words\n\n", tmp,
  548. (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono");
  549. /* doc says LSB represents -1.5dB, but the max value (-94.5dB)
  550. suggests that LSB is -3dB, which is more coherent with the logarithmic
  551. nature of the dB scale */
  552. reg = ad1889_readw(chip, AD_DS_WADA);
  553. snd_iprintf(buffer, "Left: %s, -%d dB\n",
  554. (reg & AD_DS_WADA_LWAM) ? "mute" : "unmute",
  555. ((reg & AD_DS_WADA_LWAA) >> 8) * 3);
  556. reg = ad1889_readw(chip, AD_DS_WADA);
  557. snd_iprintf(buffer, "Right: %s, -%d dB\n",
  558. (reg & AD_DS_WADA_RWAM) ? "mute" : "unmute",
  559. (reg & AD_DS_WADA_RWAA) * 3);
  560. reg = ad1889_readw(chip, AD_DS_WAS);
  561. snd_iprintf(buffer, "Wave samplerate: %u Hz\n", reg);
  562. reg = ad1889_readw(chip, AD_DS_RES);
  563. snd_iprintf(buffer, "Resampler samplerate: %u Hz\n", reg);
  564. }
  565. static void
  566. snd_ad1889_proc_init(struct snd_ad1889 *chip)
  567. {
  568. snd_card_ro_proc_new(chip->card, chip->card->driver,
  569. chip, snd_ad1889_proc_read);
  570. }
  571. static const struct ac97_quirk ac97_quirks[] = {
  572. {
  573. .subvendor = 0x11d4, /* AD */
  574. .subdevice = 0x1889, /* AD1889 */
  575. .codec_id = AC97_ID_AD1819,
  576. .name = "AD1889",
  577. .type = AC97_TUNE_HP_ONLY
  578. },
  579. { } /* terminator */
  580. };
  581. static void
  582. snd_ad1889_ac97_xinit(struct snd_ad1889 *chip)
  583. {
  584. u16 reg;
  585. reg = ad1889_readw(chip, AD_AC97_ACIC);
  586. reg |= AD_AC97_ACIC_ACRD; /* Reset Disable */
  587. ad1889_writew(chip, AD_AC97_ACIC, reg);
  588. ad1889_readw(chip, AD_AC97_ACIC); /* flush posted write */
  589. udelay(10);
  590. /* Interface Enable */
  591. reg |= AD_AC97_ACIC_ACIE;
  592. ad1889_writew(chip, AD_AC97_ACIC, reg);
  593. snd_ad1889_ac97_ready(chip);
  594. /* Audio Stream Output | Variable Sample Rate Mode */
  595. reg = ad1889_readw(chip, AD_AC97_ACIC);
  596. reg |= AD_AC97_ACIC_ASOE | AD_AC97_ACIC_VSRM;
  597. ad1889_writew(chip, AD_AC97_ACIC, reg);
  598. ad1889_readw(chip, AD_AC97_ACIC); /* flush posted write */
  599. }
  600. static void
  601. snd_ad1889_ac97_bus_free(struct snd_ac97_bus *bus)
  602. {
  603. struct snd_ad1889 *chip = bus->private_data;
  604. chip->ac97_bus = NULL;
  605. }
  606. static void
  607. snd_ad1889_ac97_free(struct snd_ac97 *ac97)
  608. {
  609. struct snd_ad1889 *chip = ac97->private_data;
  610. chip->ac97 = NULL;
  611. }
  612. static int
  613. snd_ad1889_ac97_init(struct snd_ad1889 *chip, const char *quirk_override)
  614. {
  615. int err;
  616. struct snd_ac97_template ac97;
  617. static const struct snd_ac97_bus_ops ops = {
  618. .write = snd_ad1889_ac97_write,
  619. .read = snd_ad1889_ac97_read,
  620. };
  621. /* doing that here, it works. */
  622. snd_ad1889_ac97_xinit(chip);
  623. err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus);
  624. if (err < 0)
  625. return err;
  626. chip->ac97_bus->private_free = snd_ad1889_ac97_bus_free;
  627. memset(&ac97, 0, sizeof(ac97));
  628. ac97.private_data = chip;
  629. ac97.private_free = snd_ad1889_ac97_free;
  630. ac97.pci = chip->pci;
  631. err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97);
  632. if (err < 0)
  633. return err;
  634. snd_ac97_tune_hardware(chip->ac97, ac97_quirks, quirk_override);
  635. return 0;
  636. }
  637. static int
  638. snd_ad1889_free(struct snd_ad1889 *chip)
  639. {
  640. if (chip->irq < 0)
  641. goto skip_hw;
  642. spin_lock_irq(&chip->lock);
  643. ad1889_mute(chip);
  644. /* Turn off interrupt on count and zero DMA registers */
  645. ad1889_channel_reset(chip, AD_CHAN_WAV | AD_CHAN_ADC);
  646. /* clear DISR. If we don't, we'd better jump off the Eiffel Tower */
  647. ad1889_writel(chip, AD_DMA_DISR, AD_DMA_DISR_PTAI | AD_DMA_DISR_PMAI);
  648. ad1889_readl(chip, AD_DMA_DISR); /* flush, dammit! */
  649. spin_unlock_irq(&chip->lock);
  650. if (chip->irq >= 0)
  651. free_irq(chip->irq, chip);
  652. skip_hw:
  653. iounmap(chip->iobase);
  654. pci_release_regions(chip->pci);
  655. pci_disable_device(chip->pci);
  656. kfree(chip);
  657. return 0;
  658. }
  659. static int
  660. snd_ad1889_dev_free(struct snd_device *device)
  661. {
  662. struct snd_ad1889 *chip = device->device_data;
  663. return snd_ad1889_free(chip);
  664. }
  665. static int
  666. snd_ad1889_init(struct snd_ad1889 *chip)
  667. {
  668. ad1889_writew(chip, AD_DS_CCS, AD_DS_CCS_CLKEN); /* turn on clock */
  669. ad1889_readw(chip, AD_DS_CCS); /* flush posted write */
  670. usleep_range(10000, 11000);
  671. /* enable Master and Target abort interrupts */
  672. ad1889_writel(chip, AD_DMA_DISR, AD_DMA_DISR_PMAE | AD_DMA_DISR_PTAE);
  673. return 0;
  674. }
  675. static int
  676. snd_ad1889_create(struct snd_card *card,
  677. struct pci_dev *pci,
  678. struct snd_ad1889 **rchip)
  679. {
  680. int err;
  681. struct snd_ad1889 *chip;
  682. static const struct snd_device_ops ops = {
  683. .dev_free = snd_ad1889_dev_free,
  684. };
  685. *rchip = NULL;
  686. if ((err = pci_enable_device(pci)) < 0)
  687. return err;
  688. /* check PCI availability (32bit DMA) */
  689. if (dma_set_mask(&pci->dev, DMA_BIT_MASK(32)) < 0 ||
  690. dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32)) < 0) {
  691. dev_err(card->dev, "error setting 32-bit DMA mask.\n");
  692. pci_disable_device(pci);
  693. return -ENXIO;
  694. }
  695. /* allocate chip specific data with zero-filled memory */
  696. if ((chip = kzalloc(sizeof(*chip), GFP_KERNEL)) == NULL) {
  697. pci_disable_device(pci);
  698. return -ENOMEM;
  699. }
  700. chip->card = card;
  701. card->private_data = chip;
  702. chip->pci = pci;
  703. chip->irq = -1;
  704. /* (1) PCI resource allocation */
  705. if ((err = pci_request_regions(pci, card->driver)) < 0)
  706. goto free_and_ret;
  707. chip->bar = pci_resource_start(pci, 0);
  708. chip->iobase = pci_ioremap_bar(pci, 0);
  709. if (chip->iobase == NULL) {
  710. dev_err(card->dev, "unable to reserve region.\n");
  711. err = -EBUSY;
  712. goto free_and_ret;
  713. }
  714. pci_set_master(pci);
  715. spin_lock_init(&chip->lock); /* only now can we call ad1889_free */
  716. if (request_irq(pci->irq, snd_ad1889_interrupt,
  717. IRQF_SHARED, KBUILD_MODNAME, chip)) {
  718. dev_err(card->dev, "cannot obtain IRQ %d\n", pci->irq);
  719. snd_ad1889_free(chip);
  720. return -EBUSY;
  721. }
  722. chip->irq = pci->irq;
  723. card->sync_irq = chip->irq;
  724. /* (2) initialization of the chip hardware */
  725. if ((err = snd_ad1889_init(chip)) < 0) {
  726. snd_ad1889_free(chip);
  727. return err;
  728. }
  729. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  730. snd_ad1889_free(chip);
  731. return err;
  732. }
  733. *rchip = chip;
  734. return 0;
  735. free_and_ret:
  736. kfree(chip);
  737. pci_disable_device(pci);
  738. return err;
  739. }
  740. static int
  741. snd_ad1889_probe(struct pci_dev *pci,
  742. const struct pci_device_id *pci_id)
  743. {
  744. int err;
  745. static int devno;
  746. struct snd_card *card;
  747. struct snd_ad1889 *chip;
  748. /* (1) */
  749. if (devno >= SNDRV_CARDS)
  750. return -ENODEV;
  751. if (!enable[devno]) {
  752. devno++;
  753. return -ENOENT;
  754. }
  755. /* (2) */
  756. err = snd_card_new(&pci->dev, index[devno], id[devno], THIS_MODULE,
  757. 0, &card);
  758. /* XXX REVISIT: we can probably allocate chip in this call */
  759. if (err < 0)
  760. return err;
  761. strcpy(card->driver, "AD1889");
  762. strcpy(card->shortname, "Analog Devices AD1889");
  763. /* (3) */
  764. err = snd_ad1889_create(card, pci, &chip);
  765. if (err < 0)
  766. goto free_and_ret;
  767. /* (4) */
  768. sprintf(card->longname, "%s at 0x%lx irq %i",
  769. card->shortname, chip->bar, chip->irq);
  770. /* (5) */
  771. /* register AC97 mixer */
  772. err = snd_ad1889_ac97_init(chip, ac97_quirk[devno]);
  773. if (err < 0)
  774. goto free_and_ret;
  775. err = snd_ad1889_pcm_init(chip, 0);
  776. if (err < 0)
  777. goto free_and_ret;
  778. /* register proc interface */
  779. snd_ad1889_proc_init(chip);
  780. /* (6) */
  781. err = snd_card_register(card);
  782. if (err < 0)
  783. goto free_and_ret;
  784. /* (7) */
  785. pci_set_drvdata(pci, card);
  786. devno++;
  787. return 0;
  788. free_and_ret:
  789. snd_card_free(card);
  790. return err;
  791. }
  792. static void
  793. snd_ad1889_remove(struct pci_dev *pci)
  794. {
  795. snd_card_free(pci_get_drvdata(pci));
  796. }
  797. static const struct pci_device_id snd_ad1889_ids[] = {
  798. { PCI_DEVICE(PCI_VENDOR_ID_ANALOG_DEVICES, PCI_DEVICE_ID_AD1889JS) },
  799. { 0, },
  800. };
  801. MODULE_DEVICE_TABLE(pci, snd_ad1889_ids);
  802. static struct pci_driver ad1889_pci_driver = {
  803. .name = KBUILD_MODNAME,
  804. .id_table = snd_ad1889_ids,
  805. .probe = snd_ad1889_probe,
  806. .remove = snd_ad1889_remove,
  807. };
  808. module_pci_driver(ad1889_pci_driver);