hdac_controller.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * HD-audio controller helpers
  4. */
  5. #include <linux/kernel.h>
  6. #include <linux/delay.h>
  7. #include <linux/export.h>
  8. #include <sound/core.h>
  9. #include <sound/hdaudio.h>
  10. #include <sound/hda_register.h>
  11. #include "local.h"
  12. /* clear CORB read pointer properly */
  13. static void azx_clear_corbrp(struct hdac_bus *bus)
  14. {
  15. int timeout;
  16. for (timeout = 1000; timeout > 0; timeout--) {
  17. if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST)
  18. break;
  19. udelay(1);
  20. }
  21. if (timeout <= 0)
  22. dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n",
  23. snd_hdac_chip_readw(bus, CORBRP));
  24. snd_hdac_chip_writew(bus, CORBRP, 0);
  25. for (timeout = 1000; timeout > 0; timeout--) {
  26. if (snd_hdac_chip_readw(bus, CORBRP) == 0)
  27. break;
  28. udelay(1);
  29. }
  30. if (timeout <= 0)
  31. dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n",
  32. snd_hdac_chip_readw(bus, CORBRP));
  33. }
  34. /**
  35. * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers
  36. * @bus: HD-audio core bus
  37. */
  38. void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus)
  39. {
  40. WARN_ON_ONCE(!bus->rb.area);
  41. spin_lock_irq(&bus->reg_lock);
  42. /* CORB set up */
  43. bus->corb.addr = bus->rb.addr;
  44. bus->corb.buf = (__le32 *)bus->rb.area;
  45. snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr);
  46. snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr));
  47. /* set the corb size to 256 entries (ULI requires explicitly) */
  48. snd_hdac_chip_writeb(bus, CORBSIZE, 0x02);
  49. /* set the corb write pointer to 0 */
  50. snd_hdac_chip_writew(bus, CORBWP, 0);
  51. /* reset the corb hw read pointer */
  52. snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST);
  53. if (!bus->corbrp_self_clear)
  54. azx_clear_corbrp(bus);
  55. /* enable corb dma */
  56. snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN);
  57. /* RIRB set up */
  58. bus->rirb.addr = bus->rb.addr + 2048;
  59. bus->rirb.buf = (__le32 *)(bus->rb.area + 2048);
  60. bus->rirb.wp = bus->rirb.rp = 0;
  61. memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds));
  62. snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr);
  63. snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr));
  64. /* set the rirb size to 256 entries (ULI requires explicitly) */
  65. snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02);
  66. /* reset the rirb hw write pointer */
  67. snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST);
  68. /* set N=1, get RIRB response interrupt for new entry */
  69. snd_hdac_chip_writew(bus, RINTCNT, 1);
  70. /* enable rirb dma and response irq */
  71. snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
  72. /* Accept unsolicited responses */
  73. snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL);
  74. spin_unlock_irq(&bus->reg_lock);
  75. }
  76. EXPORT_SYMBOL_GPL(snd_hdac_bus_init_cmd_io);
  77. /* wait for cmd dmas till they are stopped */
  78. static void hdac_wait_for_cmd_dmas(struct hdac_bus *bus)
  79. {
  80. unsigned long timeout;
  81. timeout = jiffies + msecs_to_jiffies(100);
  82. while ((snd_hdac_chip_readb(bus, RIRBCTL) & AZX_RBCTL_DMA_EN)
  83. && time_before(jiffies, timeout))
  84. udelay(10);
  85. timeout = jiffies + msecs_to_jiffies(100);
  86. while ((snd_hdac_chip_readb(bus, CORBCTL) & AZX_CORBCTL_RUN)
  87. && time_before(jiffies, timeout))
  88. udelay(10);
  89. }
  90. /**
  91. * snd_hdac_bus_stop_cmd_io - clean up CORB/RIRB buffers
  92. * @bus: HD-audio core bus
  93. */
  94. void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus)
  95. {
  96. spin_lock_irq(&bus->reg_lock);
  97. /* disable ringbuffer DMAs */
  98. snd_hdac_chip_writeb(bus, RIRBCTL, 0);
  99. snd_hdac_chip_writeb(bus, CORBCTL, 0);
  100. spin_unlock_irq(&bus->reg_lock);
  101. hdac_wait_for_cmd_dmas(bus);
  102. spin_lock_irq(&bus->reg_lock);
  103. /* disable unsolicited responses */
  104. snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0);
  105. spin_unlock_irq(&bus->reg_lock);
  106. }
  107. EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_cmd_io);
  108. static unsigned int azx_command_addr(u32 cmd)
  109. {
  110. unsigned int addr = cmd >> 28;
  111. if (snd_BUG_ON(addr >= HDA_MAX_CODECS))
  112. addr = 0;
  113. return addr;
  114. }
  115. /**
  116. * snd_hdac_bus_send_cmd - send a command verb via CORB
  117. * @bus: HD-audio core bus
  118. * @val: encoded verb value to send
  119. *
  120. * Returns zero for success or a negative error code.
  121. */
  122. int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val)
  123. {
  124. unsigned int addr = azx_command_addr(val);
  125. unsigned int wp, rp;
  126. spin_lock_irq(&bus->reg_lock);
  127. bus->last_cmd[azx_command_addr(val)] = val;
  128. /* add command to corb */
  129. wp = snd_hdac_chip_readw(bus, CORBWP);
  130. if (wp == 0xffff) {
  131. /* something wrong, controller likely turned to D3 */
  132. spin_unlock_irq(&bus->reg_lock);
  133. return -EIO;
  134. }
  135. wp++;
  136. wp %= AZX_MAX_CORB_ENTRIES;
  137. rp = snd_hdac_chip_readw(bus, CORBRP);
  138. if (wp == rp) {
  139. /* oops, it's full */
  140. spin_unlock_irq(&bus->reg_lock);
  141. return -EAGAIN;
  142. }
  143. bus->rirb.cmds[addr]++;
  144. bus->corb.buf[wp] = cpu_to_le32(val);
  145. snd_hdac_chip_writew(bus, CORBWP, wp);
  146. spin_unlock_irq(&bus->reg_lock);
  147. return 0;
  148. }
  149. EXPORT_SYMBOL_GPL(snd_hdac_bus_send_cmd);
  150. #define AZX_RIRB_EX_UNSOL_EV (1<<4)
  151. /**
  152. * snd_hdac_bus_update_rirb - retrieve RIRB entries
  153. * @bus: HD-audio core bus
  154. *
  155. * Usually called from interrupt handler.
  156. * The caller needs bus->reg_lock spinlock before calling this.
  157. */
  158. void snd_hdac_bus_update_rirb(struct hdac_bus *bus)
  159. {
  160. unsigned int rp, wp;
  161. unsigned int addr;
  162. u32 res, res_ex;
  163. wp = snd_hdac_chip_readw(bus, RIRBWP);
  164. if (wp == 0xffff) {
  165. /* something wrong, controller likely turned to D3 */
  166. return;
  167. }
  168. if (wp == bus->rirb.wp)
  169. return;
  170. bus->rirb.wp = wp;
  171. while (bus->rirb.rp != wp) {
  172. bus->rirb.rp++;
  173. bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
  174. rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */
  175. res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]);
  176. res = le32_to_cpu(bus->rirb.buf[rp]);
  177. addr = res_ex & 0xf;
  178. if (addr >= HDA_MAX_CODECS) {
  179. dev_err(bus->dev,
  180. "spurious response %#x:%#x, rp = %d, wp = %d",
  181. res, res_ex, bus->rirb.rp, wp);
  182. snd_BUG();
  183. } else if (res_ex & AZX_RIRB_EX_UNSOL_EV)
  184. snd_hdac_bus_queue_event(bus, res, res_ex);
  185. else if (bus->rirb.cmds[addr]) {
  186. bus->rirb.res[addr] = res;
  187. bus->rirb.cmds[addr]--;
  188. if (!bus->rirb.cmds[addr] &&
  189. waitqueue_active(&bus->rirb_wq))
  190. wake_up(&bus->rirb_wq);
  191. } else {
  192. dev_err_ratelimited(bus->dev,
  193. "spurious response %#x:%#x, last cmd=%#08x\n",
  194. res, res_ex, bus->last_cmd[addr]);
  195. }
  196. }
  197. }
  198. EXPORT_SYMBOL_GPL(snd_hdac_bus_update_rirb);
  199. /**
  200. * snd_hdac_bus_get_response - receive a response via RIRB
  201. * @bus: HD-audio core bus
  202. * @addr: codec address
  203. * @res: pointer to store the value, NULL when not needed
  204. *
  205. * Returns zero if a value is read, or a negative error code.
  206. */
  207. int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
  208. unsigned int *res)
  209. {
  210. unsigned long timeout;
  211. unsigned long loopcounter;
  212. wait_queue_entry_t wait;
  213. bool warned = false;
  214. init_wait_entry(&wait, 0);
  215. timeout = jiffies + msecs_to_jiffies(1000);
  216. for (loopcounter = 0;; loopcounter++) {
  217. spin_lock_irq(&bus->reg_lock);
  218. if (!bus->polling_mode)
  219. prepare_to_wait(&bus->rirb_wq, &wait,
  220. TASK_UNINTERRUPTIBLE);
  221. if (bus->polling_mode)
  222. snd_hdac_bus_update_rirb(bus);
  223. if (!bus->rirb.cmds[addr]) {
  224. if (res)
  225. *res = bus->rirb.res[addr]; /* the last value */
  226. if (!bus->polling_mode)
  227. finish_wait(&bus->rirb_wq, &wait);
  228. spin_unlock_irq(&bus->reg_lock);
  229. return 0;
  230. }
  231. spin_unlock_irq(&bus->reg_lock);
  232. if (time_after(jiffies, timeout))
  233. break;
  234. #define LOOP_COUNT_MAX 3000
  235. if (!bus->polling_mode) {
  236. schedule_timeout(msecs_to_jiffies(2));
  237. } else if (bus->needs_damn_long_delay ||
  238. loopcounter > LOOP_COUNT_MAX) {
  239. if (loopcounter > LOOP_COUNT_MAX && !warned) {
  240. dev_dbg_ratelimited(bus->dev,
  241. "too slow response, last cmd=%#08x\n",
  242. bus->last_cmd[addr]);
  243. warned = true;
  244. }
  245. msleep(2); /* temporary workaround */
  246. } else {
  247. udelay(10);
  248. cond_resched();
  249. }
  250. }
  251. if (!bus->polling_mode)
  252. finish_wait(&bus->rirb_wq, &wait);
  253. return -EIO;
  254. }
  255. EXPORT_SYMBOL_GPL(snd_hdac_bus_get_response);
  256. #define HDAC_MAX_CAPS 10
  257. /**
  258. * snd_hdac_bus_parse_capabilities - parse capability structure
  259. * @bus: the pointer to bus object
  260. *
  261. * Returns 0 if successful, or a negative error code.
  262. */
  263. int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus)
  264. {
  265. unsigned int cur_cap;
  266. unsigned int offset;
  267. unsigned int counter = 0;
  268. offset = snd_hdac_chip_readw(bus, LLCH);
  269. /* Lets walk the linked capabilities list */
  270. do {
  271. cur_cap = _snd_hdac_chip_readl(bus, offset);
  272. dev_dbg(bus->dev, "Capability version: 0x%x\n",
  273. (cur_cap & AZX_CAP_HDR_VER_MASK) >> AZX_CAP_HDR_VER_OFF);
  274. dev_dbg(bus->dev, "HDA capability ID: 0x%x\n",
  275. (cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF);
  276. if (cur_cap == -1) {
  277. dev_dbg(bus->dev, "Invalid capability reg read\n");
  278. break;
  279. }
  280. switch ((cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF) {
  281. case AZX_ML_CAP_ID:
  282. dev_dbg(bus->dev, "Found ML capability\n");
  283. bus->mlcap = bus->remap_addr + offset;
  284. break;
  285. case AZX_GTS_CAP_ID:
  286. dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset);
  287. bus->gtscap = bus->remap_addr + offset;
  288. break;
  289. case AZX_PP_CAP_ID:
  290. /* PP capability found, the Audio DSP is present */
  291. dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset);
  292. bus->ppcap = bus->remap_addr + offset;
  293. break;
  294. case AZX_SPB_CAP_ID:
  295. /* SPIB capability found, handler function */
  296. dev_dbg(bus->dev, "Found SPB capability\n");
  297. bus->spbcap = bus->remap_addr + offset;
  298. break;
  299. case AZX_DRSM_CAP_ID:
  300. /* DMA resume capability found, handler function */
  301. dev_dbg(bus->dev, "Found DRSM capability\n");
  302. bus->drsmcap = bus->remap_addr + offset;
  303. break;
  304. default:
  305. dev_err(bus->dev, "Unknown capability %d\n", cur_cap);
  306. cur_cap = 0;
  307. break;
  308. }
  309. counter++;
  310. if (counter > HDAC_MAX_CAPS) {
  311. dev_err(bus->dev, "We exceeded HDAC capabilities!!!\n");
  312. break;
  313. }
  314. /* read the offset of next capability */
  315. offset = cur_cap & AZX_CAP_HDR_NXT_PTR_MASK;
  316. } while (offset);
  317. return 0;
  318. }
  319. EXPORT_SYMBOL_GPL(snd_hdac_bus_parse_capabilities);
  320. /*
  321. * Lowlevel interface
  322. */
  323. /**
  324. * snd_hdac_bus_enter_link_reset - enter link reset
  325. * @bus: HD-audio core bus
  326. *
  327. * Enter to the link reset state.
  328. */
  329. void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus)
  330. {
  331. unsigned long timeout;
  332. /* reset controller */
  333. snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0);
  334. timeout = jiffies + msecs_to_jiffies(100);
  335. while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) &&
  336. time_before(jiffies, timeout))
  337. usleep_range(500, 1000);
  338. }
  339. EXPORT_SYMBOL_GPL(snd_hdac_bus_enter_link_reset);
  340. /**
  341. * snd_hdac_bus_exit_link_reset - exit link reset
  342. * @bus: HD-audio core bus
  343. *
  344. * Exit from the link reset state.
  345. */
  346. void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus)
  347. {
  348. unsigned long timeout;
  349. snd_hdac_chip_updateb(bus, GCTL, AZX_GCTL_RESET, AZX_GCTL_RESET);
  350. timeout = jiffies + msecs_to_jiffies(100);
  351. while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout))
  352. usleep_range(500, 1000);
  353. }
  354. EXPORT_SYMBOL_GPL(snd_hdac_bus_exit_link_reset);
  355. /* reset codec link */
  356. int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset)
  357. {
  358. if (!full_reset)
  359. goto skip_reset;
  360. /* clear STATESTS if not in reset */
  361. if (snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET)
  362. snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
  363. /* reset controller */
  364. snd_hdac_bus_enter_link_reset(bus);
  365. /* delay for >= 100us for codec PLL to settle per spec
  366. * Rev 0.9 section 5.5.1
  367. */
  368. usleep_range(500, 1000);
  369. /* Bring controller out of reset */
  370. snd_hdac_bus_exit_link_reset(bus);
  371. /* Brent Chartrand said to wait >= 540us for codecs to initialize */
  372. usleep_range(1000, 1200);
  373. skip_reset:
  374. /* check to see if controller is ready */
  375. if (!snd_hdac_chip_readb(bus, GCTL)) {
  376. dev_dbg(bus->dev, "controller not ready!\n");
  377. return -EBUSY;
  378. }
  379. /* detect codecs */
  380. if (!bus->codec_mask) {
  381. bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
  382. dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
  383. }
  384. return 0;
  385. }
  386. EXPORT_SYMBOL_GPL(snd_hdac_bus_reset_link);
  387. /* enable interrupts */
  388. static void azx_int_enable(struct hdac_bus *bus)
  389. {
  390. /* enable controller CIE and GIE */
  391. snd_hdac_chip_updatel(bus, INTCTL,
  392. AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN,
  393. AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN);
  394. }
  395. /* disable interrupts */
  396. static void azx_int_disable(struct hdac_bus *bus)
  397. {
  398. struct hdac_stream *azx_dev;
  399. /* disable interrupts in stream descriptor */
  400. list_for_each_entry(azx_dev, &bus->stream_list, list)
  401. snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_INT_MASK, 0);
  402. /* disable SIE for all streams */
  403. snd_hdac_chip_writeb(bus, INTCTL, 0);
  404. /* disable controller CIE and GIE */
  405. snd_hdac_chip_updatel(bus, INTCTL, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN, 0);
  406. }
  407. /* clear interrupts */
  408. static void azx_int_clear(struct hdac_bus *bus)
  409. {
  410. struct hdac_stream *azx_dev;
  411. /* clear stream status */
  412. list_for_each_entry(azx_dev, &bus->stream_list, list)
  413. snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
  414. /* clear STATESTS */
  415. snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
  416. /* clear rirb status */
  417. snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
  418. /* clear int status */
  419. snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
  420. }
  421. /**
  422. * snd_hdac_bus_init_chip - reset and start the controller registers
  423. * @bus: HD-audio core bus
  424. * @full_reset: Do full reset
  425. */
  426. bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
  427. {
  428. if (bus->chip_init)
  429. return false;
  430. /* reset controller */
  431. snd_hdac_bus_reset_link(bus, full_reset);
  432. /* clear interrupts */
  433. azx_int_clear(bus);
  434. /* initialize the codec command I/O */
  435. snd_hdac_bus_init_cmd_io(bus);
  436. /* enable interrupts after CORB/RIRB buffers are initialized above */
  437. azx_int_enable(bus);
  438. /* program the position buffer */
  439. if (bus->use_posbuf && bus->posbuf.addr) {
  440. snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr);
  441. snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr));
  442. }
  443. bus->chip_init = true;
  444. return true;
  445. }
  446. EXPORT_SYMBOL_GPL(snd_hdac_bus_init_chip);
  447. /**
  448. * snd_hdac_bus_stop_chip - disable the whole IRQ and I/Os
  449. * @bus: HD-audio core bus
  450. */
  451. void snd_hdac_bus_stop_chip(struct hdac_bus *bus)
  452. {
  453. if (!bus->chip_init)
  454. return;
  455. /* disable interrupts */
  456. azx_int_disable(bus);
  457. azx_int_clear(bus);
  458. /* disable CORB/RIRB */
  459. snd_hdac_bus_stop_cmd_io(bus);
  460. /* disable position buffer */
  461. if (bus->posbuf.addr) {
  462. snd_hdac_chip_writel(bus, DPLBASE, 0);
  463. snd_hdac_chip_writel(bus, DPUBASE, 0);
  464. }
  465. bus->chip_init = false;
  466. }
  467. EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_chip);
  468. /**
  469. * snd_hdac_bus_handle_stream_irq - interrupt handler for streams
  470. * @bus: HD-audio core bus
  471. * @status: INTSTS register value
  472. * @ack: callback to be called for woken streams
  473. *
  474. * Returns the bits of handled streams, or zero if no stream is handled.
  475. */
  476. int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
  477. void (*ack)(struct hdac_bus *,
  478. struct hdac_stream *))
  479. {
  480. struct hdac_stream *azx_dev;
  481. u8 sd_status;
  482. int handled = 0;
  483. list_for_each_entry(azx_dev, &bus->stream_list, list) {
  484. if (status & azx_dev->sd_int_sta_mask) {
  485. sd_status = snd_hdac_stream_readb(azx_dev, SD_STS);
  486. snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
  487. handled |= 1 << azx_dev->index;
  488. if (!azx_dev->substream || !azx_dev->running ||
  489. !(sd_status & SD_INT_COMPLETE))
  490. continue;
  491. if (ack)
  492. ack(bus, azx_dev);
  493. }
  494. }
  495. return handled;
  496. }
  497. EXPORT_SYMBOL_GPL(snd_hdac_bus_handle_stream_irq);
  498. /**
  499. * snd_hdac_bus_alloc_stream_pages - allocate BDL and other buffers
  500. * @bus: HD-audio core bus
  501. *
  502. * Call this after assigning the all streams.
  503. * Returns zero for success, or a negative error code.
  504. */
  505. int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus)
  506. {
  507. struct hdac_stream *s;
  508. int num_streams = 0;
  509. int dma_type = bus->dma_type ? bus->dma_type : SNDRV_DMA_TYPE_DEV;
  510. int err;
  511. list_for_each_entry(s, &bus->stream_list, list) {
  512. /* allocate memory for the BDL for each stream */
  513. err = snd_dma_alloc_pages(dma_type, bus->dev,
  514. BDL_SIZE, &s->bdl);
  515. num_streams++;
  516. if (err < 0)
  517. return -ENOMEM;
  518. }
  519. if (WARN_ON(!num_streams))
  520. return -EINVAL;
  521. /* allocate memory for the position buffer */
  522. err = snd_dma_alloc_pages(dma_type, bus->dev,
  523. num_streams * 8, &bus->posbuf);
  524. if (err < 0)
  525. return -ENOMEM;
  526. list_for_each_entry(s, &bus->stream_list, list)
  527. s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8);
  528. /* single page (at least 4096 bytes) must suffice for both ringbuffes */
  529. return snd_dma_alloc_pages(dma_type, bus->dev, PAGE_SIZE, &bus->rb);
  530. }
  531. EXPORT_SYMBOL_GPL(snd_hdac_bus_alloc_stream_pages);
  532. /**
  533. * snd_hdac_bus_free_stream_pages - release BDL and other buffers
  534. * @bus: HD-audio core bus
  535. */
  536. void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus)
  537. {
  538. struct hdac_stream *s;
  539. list_for_each_entry(s, &bus->stream_list, list) {
  540. if (s->bdl.area)
  541. snd_dma_free_pages(&s->bdl);
  542. }
  543. if (bus->rb.area)
  544. snd_dma_free_pages(&bus->rb);
  545. if (bus->posbuf.area)
  546. snd_dma_free_pages(&bus->posbuf);
  547. }
  548. EXPORT_SYMBOL_GPL(snd_hdac_bus_free_stream_pages);