aaci.h 6.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
  4. *
  5. * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
  6. */
  7. #ifndef AACI_H
  8. #define AACI_H
  9. /*
  10. * Control and status register offsets
  11. * P39.
  12. */
  13. #define AACI_CSCH1 0x000
  14. #define AACI_CSCH2 0x014
  15. #define AACI_CSCH3 0x028
  16. #define AACI_CSCH4 0x03c
  17. #define AACI_RXCR 0x000 /* 29 bits Control Rx FIFO */
  18. #define AACI_TXCR 0x004 /* 17 bits Control Tx FIFO */
  19. #define AACI_SR 0x008 /* 12 bits Status */
  20. #define AACI_ISR 0x00c /* 7 bits Int Status */
  21. #define AACI_IE 0x010 /* 7 bits Int Enable */
  22. /*
  23. * Other registers
  24. */
  25. #define AACI_SL1RX 0x050
  26. #define AACI_SL1TX 0x054
  27. #define AACI_SL2RX 0x058
  28. #define AACI_SL2TX 0x05c
  29. #define AACI_SL12RX 0x060
  30. #define AACI_SL12TX 0x064
  31. #define AACI_SLFR 0x068 /* slot flags */
  32. #define AACI_SLISTAT 0x06c /* slot interrupt status */
  33. #define AACI_SLIEN 0x070 /* slot interrupt enable */
  34. #define AACI_INTCLR 0x074 /* interrupt clear */
  35. #define AACI_MAINCR 0x078 /* main control */
  36. #define AACI_RESET 0x07c /* reset control */
  37. #define AACI_SYNC 0x080 /* sync control */
  38. #define AACI_ALLINTS 0x084 /* all fifo interrupt status */
  39. #define AACI_MAINFR 0x088 /* main flag register */
  40. #define AACI_DR1 0x090 /* data read/written fifo 1 */
  41. #define AACI_DR2 0x0b0 /* data read/written fifo 2 */
  42. #define AACI_DR3 0x0d0 /* data read/written fifo 3 */
  43. #define AACI_DR4 0x0f0 /* data read/written fifo 4 */
  44. /*
  45. * TX/RX fifo control register (CR). P48
  46. */
  47. #define CR_FEN (1 << 16) /* fifo enable */
  48. #define CR_COMPACT (1 << 15) /* compact mode */
  49. #define CR_SZ16 (0 << 13) /* 16 bits */
  50. #define CR_SZ18 (1 << 13) /* 18 bits */
  51. #define CR_SZ20 (2 << 13) /* 20 bits */
  52. #define CR_SZ12 (3 << 13) /* 12 bits */
  53. #define CR_SL12 (1 << 12)
  54. #define CR_SL11 (1 << 11)
  55. #define CR_SL10 (1 << 10)
  56. #define CR_SL9 (1 << 9)
  57. #define CR_SL8 (1 << 8)
  58. #define CR_SL7 (1 << 7)
  59. #define CR_SL6 (1 << 6)
  60. #define CR_SL5 (1 << 5)
  61. #define CR_SL4 (1 << 4)
  62. #define CR_SL3 (1 << 3)
  63. #define CR_SL2 (1 << 2)
  64. #define CR_SL1 (1 << 1)
  65. #define CR_EN (1 << 0) /* transmit enable */
  66. /*
  67. * status register bits. P49
  68. */
  69. #define SR_RXTOFE (1 << 11) /* rx timeout fifo empty */
  70. #define SR_TXTO (1 << 10) /* rx timeout fifo nonempty */
  71. #define SR_TXU (1 << 9) /* tx underrun */
  72. #define SR_RXO (1 << 8) /* rx overrun */
  73. #define SR_TXB (1 << 7) /* tx busy */
  74. #define SR_RXB (1 << 6) /* rx busy */
  75. #define SR_TXFF (1 << 5) /* tx fifo full */
  76. #define SR_RXFF (1 << 4) /* rx fifo full */
  77. #define SR_TXHE (1 << 3) /* tx fifo half empty */
  78. #define SR_RXHF (1 << 2) /* rx fifo half full */
  79. #define SR_TXFE (1 << 1) /* tx fifo empty */
  80. #define SR_RXFE (1 << 0) /* rx fifo empty */
  81. /*
  82. * interrupt status register bits.
  83. */
  84. #define ISR_RXTOFEINTR (1 << 6) /* rx fifo empty */
  85. #define ISR_URINTR (1 << 5) /* tx underflow */
  86. #define ISR_ORINTR (1 << 4) /* rx overflow */
  87. #define ISR_RXINTR (1 << 3) /* rx fifo */
  88. #define ISR_TXINTR (1 << 2) /* tx fifo intr */
  89. #define ISR_RXTOINTR (1 << 1) /* tx timeout */
  90. #define ISR_TXCINTR (1 << 0) /* tx complete */
  91. /*
  92. * interrupt enable register bits.
  93. */
  94. #define IE_RXTOIE (1 << 6)
  95. #define IE_URIE (1 << 5)
  96. #define IE_ORIE (1 << 4)
  97. #define IE_RXIE (1 << 3)
  98. #define IE_TXIE (1 << 2)
  99. #define IE_RXTIE (1 << 1)
  100. #define IE_TXCIE (1 << 0)
  101. /*
  102. * interrupt status. P51
  103. */
  104. #define ISR_RXTOFE (1 << 6) /* rx timeout fifo empty */
  105. #define ISR_UR (1 << 5) /* tx fifo underrun */
  106. #define ISR_OR (1 << 4) /* rx fifo overrun */
  107. #define ISR_RX (1 << 3) /* rx interrupt status */
  108. #define ISR_TX (1 << 2) /* tx interrupt status */
  109. #define ISR_RXTO (1 << 1) /* rx timeout */
  110. #define ISR_TXC (1 << 0) /* tx complete */
  111. /*
  112. * interrupt enable. P52
  113. */
  114. #define IE_RXTOFE (1 << 6) /* rx timeout fifo empty */
  115. #define IE_UR (1 << 5) /* tx fifo underrun */
  116. #define IE_OR (1 << 4) /* rx fifo overrun */
  117. #define IE_RX (1 << 3) /* rx interrupt status */
  118. #define IE_TX (1 << 2) /* tx interrupt status */
  119. #define IE_RXTO (1 << 1) /* rx timeout */
  120. #define IE_TXC (1 << 0) /* tx complete */
  121. /*
  122. * slot flag register bits. P56
  123. */
  124. #define SLFR_RWIS (1 << 13) /* raw wake-up interrupt status */
  125. #define SLFR_RGPIOINTR (1 << 12) /* raw gpio interrupt */
  126. #define SLFR_12TXE (1 << 11) /* slot 12 tx empty */
  127. #define SLFR_12RXV (1 << 10) /* slot 12 rx valid */
  128. #define SLFR_2TXE (1 << 9) /* slot 2 tx empty */
  129. #define SLFR_2RXV (1 << 8) /* slot 2 rx valid */
  130. #define SLFR_1TXE (1 << 7) /* slot 1 tx empty */
  131. #define SLFR_1RXV (1 << 6) /* slot 1 rx valid */
  132. #define SLFR_12TXB (1 << 5) /* slot 12 tx busy */
  133. #define SLFR_12RXB (1 << 4) /* slot 12 rx busy */
  134. #define SLFR_2TXB (1 << 3) /* slot 2 tx busy */
  135. #define SLFR_2RXB (1 << 2) /* slot 2 rx busy */
  136. #define SLFR_1TXB (1 << 1) /* slot 1 tx busy */
  137. #define SLFR_1RXB (1 << 0) /* slot 1 rx busy */
  138. /*
  139. * Interrupt clear register.
  140. */
  141. #define ICLR_RXTOFEC4 (1 << 12)
  142. #define ICLR_RXTOFEC3 (1 << 11)
  143. #define ICLR_RXTOFEC2 (1 << 10)
  144. #define ICLR_RXTOFEC1 (1 << 9)
  145. #define ICLR_TXUEC4 (1 << 8)
  146. #define ICLR_TXUEC3 (1 << 7)
  147. #define ICLR_TXUEC2 (1 << 6)
  148. #define ICLR_TXUEC1 (1 << 5)
  149. #define ICLR_RXOEC4 (1 << 4)
  150. #define ICLR_RXOEC3 (1 << 3)
  151. #define ICLR_RXOEC2 (1 << 2)
  152. #define ICLR_RXOEC1 (1 << 1)
  153. #define ICLR_WISC (1 << 0)
  154. /*
  155. * Main control register bits. P62
  156. */
  157. #define MAINCR_SCRA(x) ((x) << 10) /* secondary codec reg access */
  158. #define MAINCR_DMAEN (1 << 9) /* dma enable */
  159. #define MAINCR_SL12TXEN (1 << 8) /* slot 12 transmit enable */
  160. #define MAINCR_SL12RXEN (1 << 7) /* slot 12 receive enable */
  161. #define MAINCR_SL2TXEN (1 << 6) /* slot 2 transmit enable */
  162. #define MAINCR_SL2RXEN (1 << 5) /* slot 2 receive enable */
  163. #define MAINCR_SL1TXEN (1 << 4) /* slot 1 transmit enable */
  164. #define MAINCR_SL1RXEN (1 << 3) /* slot 1 receive enable */
  165. #define MAINCR_LPM (1 << 2) /* low power mode */
  166. #define MAINCR_LOOPBK (1 << 1) /* loopback */
  167. #define MAINCR_IE (1 << 0) /* aaci interface enable */
  168. /*
  169. * Reset register bits. P65
  170. */
  171. #define RESET_NRST (1 << 0)
  172. /*
  173. * Sync register bits. P65
  174. */
  175. #define SYNC_FORCE (1 << 0)
  176. /*
  177. * Main flag register bits. P66
  178. */
  179. #define MAINFR_TXB (1 << 1) /* transmit busy */
  180. #define MAINFR_RXB (1 << 0) /* receive busy */
  181. struct aaci_runtime {
  182. void __iomem *base;
  183. void __iomem *fifo;
  184. spinlock_t lock;
  185. struct ac97_pcm *pcm;
  186. int pcm_open;
  187. u32 cr;
  188. struct snd_pcm_substream *substream;
  189. unsigned int period; /* byte size of a "period" */
  190. /*
  191. * PIO support
  192. */
  193. void *start;
  194. void *end;
  195. void *ptr;
  196. int bytes;
  197. unsigned int fifo_bytes;
  198. };
  199. struct aaci {
  200. struct amba_device *dev;
  201. struct snd_card *card;
  202. void __iomem *base;
  203. unsigned int fifo_depth;
  204. unsigned int users;
  205. struct mutex irq_lock;
  206. /* AC'97 */
  207. struct mutex ac97_sem;
  208. struct snd_ac97_bus *ac97_bus;
  209. struct snd_ac97 *ac97;
  210. u32 maincr;
  211. struct aaci_runtime playback;
  212. struct aaci_runtime capture;
  213. struct snd_pcm *pcm;
  214. };
  215. #define ACSTREAM_FRONT 0
  216. #define ACSTREAM_SURROUND 1
  217. #define ACSTREAM_LFE 2
  218. #endif