aaci.c 24 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
  4. *
  5. * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
  6. *
  7. * Documentation: ARM DDI 0173B
  8. */
  9. #include <linux/module.h>
  10. #include <linux/delay.h>
  11. #include <linux/init.h>
  12. #include <linux/ioport.h>
  13. #include <linux/device.h>
  14. #include <linux/spinlock.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/err.h>
  17. #include <linux/amba/bus.h>
  18. #include <linux/io.h>
  19. #include <sound/core.h>
  20. #include <sound/initval.h>
  21. #include <sound/ac97_codec.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include "aaci.h"
  25. #define DRIVER_NAME "aaci-pl041"
  26. #define FRAME_PERIOD_US 21
  27. /*
  28. * PM support is not complete. Turn it off.
  29. */
  30. #undef CONFIG_PM
  31. static void aaci_ac97_select_codec(struct aaci *aaci, struct snd_ac97 *ac97)
  32. {
  33. u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num);
  34. /*
  35. * Ensure that the slot 1/2 RX registers are empty.
  36. */
  37. v = readl(aaci->base + AACI_SLFR);
  38. if (v & SLFR_2RXV)
  39. readl(aaci->base + AACI_SL2RX);
  40. if (v & SLFR_1RXV)
  41. readl(aaci->base + AACI_SL1RX);
  42. if (maincr != readl(aaci->base + AACI_MAINCR)) {
  43. writel(maincr, aaci->base + AACI_MAINCR);
  44. readl(aaci->base + AACI_MAINCR);
  45. udelay(1);
  46. }
  47. }
  48. /*
  49. * P29:
  50. * The recommended use of programming the external codec through slot 1
  51. * and slot 2 data is to use the channels during setup routines and the
  52. * slot register at any other time. The data written into slot 1, slot 2
  53. * and slot 12 registers is transmitted only when their corresponding
  54. * SI1TxEn, SI2TxEn and SI12TxEn bits are set in the AACI_MAINCR
  55. * register.
  56. */
  57. static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
  58. unsigned short val)
  59. {
  60. struct aaci *aaci = ac97->private_data;
  61. int timeout;
  62. u32 v;
  63. if (ac97->num >= 4)
  64. return;
  65. mutex_lock(&aaci->ac97_sem);
  66. aaci_ac97_select_codec(aaci, ac97);
  67. /*
  68. * P54: You must ensure that AACI_SL2TX is always written
  69. * to, if required, before data is written to AACI_SL1TX.
  70. */
  71. writel(val << 4, aaci->base + AACI_SL2TX);
  72. writel(reg << 12, aaci->base + AACI_SL1TX);
  73. /* Initially, wait one frame period */
  74. udelay(FRAME_PERIOD_US);
  75. /* And then wait an additional eight frame periods for it to be sent */
  76. timeout = FRAME_PERIOD_US * 8;
  77. do {
  78. udelay(1);
  79. v = readl(aaci->base + AACI_SLFR);
  80. } while ((v & (SLFR_1TXB|SLFR_2TXB)) && --timeout);
  81. if (v & (SLFR_1TXB|SLFR_2TXB))
  82. dev_err(&aaci->dev->dev,
  83. "timeout waiting for write to complete\n");
  84. mutex_unlock(&aaci->ac97_sem);
  85. }
  86. /*
  87. * Read an AC'97 register.
  88. */
  89. static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
  90. {
  91. struct aaci *aaci = ac97->private_data;
  92. int timeout, retries = 10;
  93. u32 v;
  94. if (ac97->num >= 4)
  95. return ~0;
  96. mutex_lock(&aaci->ac97_sem);
  97. aaci_ac97_select_codec(aaci, ac97);
  98. /*
  99. * Write the register address to slot 1.
  100. */
  101. writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX);
  102. /* Initially, wait one frame period */
  103. udelay(FRAME_PERIOD_US);
  104. /* And then wait an additional eight frame periods for it to be sent */
  105. timeout = FRAME_PERIOD_US * 8;
  106. do {
  107. udelay(1);
  108. v = readl(aaci->base + AACI_SLFR);
  109. } while ((v & SLFR_1TXB) && --timeout);
  110. if (v & SLFR_1TXB) {
  111. dev_err(&aaci->dev->dev, "timeout on slot 1 TX busy\n");
  112. v = ~0;
  113. goto out;
  114. }
  115. /* Now wait for the response frame */
  116. udelay(FRAME_PERIOD_US);
  117. /* And then wait an additional eight frame periods for data */
  118. timeout = FRAME_PERIOD_US * 8;
  119. do {
  120. udelay(1);
  121. cond_resched();
  122. v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV);
  123. } while ((v != (SLFR_1RXV|SLFR_2RXV)) && --timeout);
  124. if (v != (SLFR_1RXV|SLFR_2RXV)) {
  125. dev_err(&aaci->dev->dev, "timeout on RX valid\n");
  126. v = ~0;
  127. goto out;
  128. }
  129. do {
  130. v = readl(aaci->base + AACI_SL1RX) >> 12;
  131. if (v == reg) {
  132. v = readl(aaci->base + AACI_SL2RX) >> 4;
  133. break;
  134. } else if (--retries) {
  135. dev_warn(&aaci->dev->dev,
  136. "ac97 read back fail. retry\n");
  137. continue;
  138. } else {
  139. dev_warn(&aaci->dev->dev,
  140. "wrong ac97 register read back (%x != %x)\n",
  141. v, reg);
  142. v = ~0;
  143. }
  144. } while (retries);
  145. out:
  146. mutex_unlock(&aaci->ac97_sem);
  147. return v;
  148. }
  149. static inline void
  150. aaci_chan_wait_ready(struct aaci_runtime *aacirun, unsigned long mask)
  151. {
  152. u32 val;
  153. int timeout = 5000;
  154. do {
  155. udelay(1);
  156. val = readl(aacirun->base + AACI_SR);
  157. } while (val & mask && timeout--);
  158. }
  159. /*
  160. * Interrupt support.
  161. */
  162. static void aaci_fifo_irq(struct aaci *aaci, int channel, u32 mask)
  163. {
  164. if (mask & ISR_ORINTR) {
  165. dev_warn(&aaci->dev->dev, "RX overrun on chan %d\n", channel);
  166. writel(ICLR_RXOEC1 << channel, aaci->base + AACI_INTCLR);
  167. }
  168. if (mask & ISR_RXTOINTR) {
  169. dev_warn(&aaci->dev->dev, "RX timeout on chan %d\n", channel);
  170. writel(ICLR_RXTOFEC1 << channel, aaci->base + AACI_INTCLR);
  171. }
  172. if (mask & ISR_RXINTR) {
  173. struct aaci_runtime *aacirun = &aaci->capture;
  174. bool period_elapsed = false;
  175. void *ptr;
  176. if (!aacirun->substream || !aacirun->start) {
  177. dev_warn(&aaci->dev->dev, "RX interrupt???\n");
  178. writel(0, aacirun->base + AACI_IE);
  179. return;
  180. }
  181. spin_lock(&aacirun->lock);
  182. ptr = aacirun->ptr;
  183. do {
  184. unsigned int len = aacirun->fifo_bytes;
  185. u32 val;
  186. if (aacirun->bytes <= 0) {
  187. aacirun->bytes += aacirun->period;
  188. period_elapsed = true;
  189. }
  190. if (!(aacirun->cr & CR_EN))
  191. break;
  192. val = readl(aacirun->base + AACI_SR);
  193. if (!(val & SR_RXHF))
  194. break;
  195. if (!(val & SR_RXFF))
  196. len >>= 1;
  197. aacirun->bytes -= len;
  198. /* reading 16 bytes at a time */
  199. for( ; len > 0; len -= 16) {
  200. asm(
  201. "ldmia %1, {r0, r1, r2, r3}\n\t"
  202. "stmia %0!, {r0, r1, r2, r3}"
  203. : "+r" (ptr)
  204. : "r" (aacirun->fifo)
  205. : "r0", "r1", "r2", "r3", "cc");
  206. if (ptr >= aacirun->end)
  207. ptr = aacirun->start;
  208. }
  209. } while(1);
  210. aacirun->ptr = ptr;
  211. spin_unlock(&aacirun->lock);
  212. if (period_elapsed)
  213. snd_pcm_period_elapsed(aacirun->substream);
  214. }
  215. if (mask & ISR_URINTR) {
  216. dev_dbg(&aaci->dev->dev, "TX underrun on chan %d\n", channel);
  217. writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR);
  218. }
  219. if (mask & ISR_TXINTR) {
  220. struct aaci_runtime *aacirun = &aaci->playback;
  221. bool period_elapsed = false;
  222. void *ptr;
  223. if (!aacirun->substream || !aacirun->start) {
  224. dev_warn(&aaci->dev->dev, "TX interrupt???\n");
  225. writel(0, aacirun->base + AACI_IE);
  226. return;
  227. }
  228. spin_lock(&aacirun->lock);
  229. ptr = aacirun->ptr;
  230. do {
  231. unsigned int len = aacirun->fifo_bytes;
  232. u32 val;
  233. if (aacirun->bytes <= 0) {
  234. aacirun->bytes += aacirun->period;
  235. period_elapsed = true;
  236. }
  237. if (!(aacirun->cr & CR_EN))
  238. break;
  239. val = readl(aacirun->base + AACI_SR);
  240. if (!(val & SR_TXHE))
  241. break;
  242. if (!(val & SR_TXFE))
  243. len >>= 1;
  244. aacirun->bytes -= len;
  245. /* writing 16 bytes at a time */
  246. for ( ; len > 0; len -= 16) {
  247. asm(
  248. "ldmia %0!, {r0, r1, r2, r3}\n\t"
  249. "stmia %1, {r0, r1, r2, r3}"
  250. : "+r" (ptr)
  251. : "r" (aacirun->fifo)
  252. : "r0", "r1", "r2", "r3", "cc");
  253. if (ptr >= aacirun->end)
  254. ptr = aacirun->start;
  255. }
  256. } while (1);
  257. aacirun->ptr = ptr;
  258. spin_unlock(&aacirun->lock);
  259. if (period_elapsed)
  260. snd_pcm_period_elapsed(aacirun->substream);
  261. }
  262. }
  263. static irqreturn_t aaci_irq(int irq, void *devid)
  264. {
  265. struct aaci *aaci = devid;
  266. u32 mask;
  267. int i;
  268. mask = readl(aaci->base + AACI_ALLINTS);
  269. if (mask) {
  270. u32 m = mask;
  271. for (i = 0; i < 4; i++, m >>= 7) {
  272. if (m & 0x7f) {
  273. aaci_fifo_irq(aaci, i, m);
  274. }
  275. }
  276. }
  277. return mask ? IRQ_HANDLED : IRQ_NONE;
  278. }
  279. /*
  280. * ALSA support.
  281. */
  282. static const struct snd_pcm_hardware aaci_hw_info = {
  283. .info = SNDRV_PCM_INFO_MMAP |
  284. SNDRV_PCM_INFO_MMAP_VALID |
  285. SNDRV_PCM_INFO_INTERLEAVED |
  286. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  287. SNDRV_PCM_INFO_RESUME,
  288. /*
  289. * ALSA doesn't support 18-bit or 20-bit packed into 32-bit
  290. * words. It also doesn't support 12-bit at all.
  291. */
  292. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  293. /* rates are setup from the AC'97 codec */
  294. .channels_min = 2,
  295. .channels_max = 2,
  296. .buffer_bytes_max = 64 * 1024,
  297. .period_bytes_min = 256,
  298. .period_bytes_max = PAGE_SIZE,
  299. .periods_min = 4,
  300. .periods_max = PAGE_SIZE / 16,
  301. };
  302. /*
  303. * We can support two and four channel audio. Unfortunately
  304. * six channel audio requires a non-standard channel ordering:
  305. * 2 -> FL(3), FR(4)
  306. * 4 -> FL(3), FR(4), SL(7), SR(8)
  307. * 6 -> FL(3), FR(4), SL(7), SR(8), C(6), LFE(9) (required)
  308. * FL(3), FR(4), C(6), SL(7), SR(8), LFE(9) (actual)
  309. * This requires an ALSA configuration file to correct.
  310. */
  311. static int aaci_rule_channels(struct snd_pcm_hw_params *p,
  312. struct snd_pcm_hw_rule *rule)
  313. {
  314. static const unsigned int channel_list[] = { 2, 4, 6 };
  315. struct aaci *aaci = rule->private;
  316. unsigned int mask = 1 << 0, slots;
  317. /* pcms[0] is the our 5.1 PCM instance. */
  318. slots = aaci->ac97_bus->pcms[0].r[0].slots;
  319. if (slots & (1 << AC97_SLOT_PCM_SLEFT)) {
  320. mask |= 1 << 1;
  321. if (slots & (1 << AC97_SLOT_LFE))
  322. mask |= 1 << 2;
  323. }
  324. return snd_interval_list(hw_param_interval(p, rule->var),
  325. ARRAY_SIZE(channel_list), channel_list, mask);
  326. }
  327. static int aaci_pcm_open(struct snd_pcm_substream *substream)
  328. {
  329. struct snd_pcm_runtime *runtime = substream->runtime;
  330. struct aaci *aaci = substream->private_data;
  331. struct aaci_runtime *aacirun;
  332. int ret = 0;
  333. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  334. aacirun = &aaci->playback;
  335. } else {
  336. aacirun = &aaci->capture;
  337. }
  338. aacirun->substream = substream;
  339. runtime->private_data = aacirun;
  340. runtime->hw = aaci_hw_info;
  341. runtime->hw.rates = aacirun->pcm->rates;
  342. snd_pcm_limit_hw_rates(runtime);
  343. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  344. runtime->hw.channels_max = 6;
  345. /* Add rule describing channel dependency. */
  346. ret = snd_pcm_hw_rule_add(substream->runtime, 0,
  347. SNDRV_PCM_HW_PARAM_CHANNELS,
  348. aaci_rule_channels, aaci,
  349. SNDRV_PCM_HW_PARAM_CHANNELS, -1);
  350. if (ret)
  351. return ret;
  352. if (aacirun->pcm->r[1].slots)
  353. snd_ac97_pcm_double_rate_rules(runtime);
  354. }
  355. /*
  356. * ALSA wants the byte-size of the FIFOs. As we only support
  357. * 16-bit samples, this is twice the FIFO depth irrespective
  358. * of whether it's in compact mode or not.
  359. */
  360. runtime->hw.fifo_size = aaci->fifo_depth * 2;
  361. mutex_lock(&aaci->irq_lock);
  362. if (!aaci->users++) {
  363. ret = request_irq(aaci->dev->irq[0], aaci_irq,
  364. IRQF_SHARED, DRIVER_NAME, aaci);
  365. if (ret != 0)
  366. aaci->users--;
  367. }
  368. mutex_unlock(&aaci->irq_lock);
  369. return ret;
  370. }
  371. /*
  372. * Common ALSA stuff
  373. */
  374. static int aaci_pcm_close(struct snd_pcm_substream *substream)
  375. {
  376. struct aaci *aaci = substream->private_data;
  377. struct aaci_runtime *aacirun = substream->runtime->private_data;
  378. WARN_ON(aacirun->cr & CR_EN);
  379. aacirun->substream = NULL;
  380. mutex_lock(&aaci->irq_lock);
  381. if (!--aaci->users)
  382. free_irq(aaci->dev->irq[0], aaci);
  383. mutex_unlock(&aaci->irq_lock);
  384. return 0;
  385. }
  386. static int aaci_pcm_hw_free(struct snd_pcm_substream *substream)
  387. {
  388. struct aaci_runtime *aacirun = substream->runtime->private_data;
  389. /*
  390. * This must not be called with the device enabled.
  391. */
  392. WARN_ON(aacirun->cr & CR_EN);
  393. if (aacirun->pcm_open)
  394. snd_ac97_pcm_close(aacirun->pcm);
  395. aacirun->pcm_open = 0;
  396. return 0;
  397. }
  398. /* Channel to slot mask */
  399. static const u32 channels_to_slotmask[] = {
  400. [2] = CR_SL3 | CR_SL4,
  401. [4] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8,
  402. [6] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8 | CR_SL6 | CR_SL9,
  403. };
  404. static int aaci_pcm_hw_params(struct snd_pcm_substream *substream,
  405. struct snd_pcm_hw_params *params)
  406. {
  407. struct aaci_runtime *aacirun = substream->runtime->private_data;
  408. struct aaci *aaci = substream->private_data;
  409. unsigned int channels = params_channels(params);
  410. unsigned int rate = params_rate(params);
  411. int dbl = rate > 48000;
  412. int err;
  413. aaci_pcm_hw_free(substream);
  414. if (aacirun->pcm_open) {
  415. snd_ac97_pcm_close(aacirun->pcm);
  416. aacirun->pcm_open = 0;
  417. }
  418. /* channels is already limited to 2, 4, or 6 by aaci_rule_channels */
  419. if (dbl && channels != 2)
  420. return -EINVAL;
  421. err = snd_ac97_pcm_open(aacirun->pcm, rate, channels,
  422. aacirun->pcm->r[dbl].slots);
  423. aacirun->pcm_open = err == 0;
  424. aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16;
  425. aacirun->cr |= channels_to_slotmask[channels + dbl * 2];
  426. /*
  427. * fifo_bytes is the number of bytes we transfer to/from
  428. * the FIFO, including padding. So that's x4. As we're
  429. * in compact mode, the FIFO is half the size.
  430. */
  431. aacirun->fifo_bytes = aaci->fifo_depth * 4 / 2;
  432. return err;
  433. }
  434. static int aaci_pcm_prepare(struct snd_pcm_substream *substream)
  435. {
  436. struct snd_pcm_runtime *runtime = substream->runtime;
  437. struct aaci_runtime *aacirun = runtime->private_data;
  438. aacirun->period = snd_pcm_lib_period_bytes(substream);
  439. aacirun->start = runtime->dma_area;
  440. aacirun->end = aacirun->start + snd_pcm_lib_buffer_bytes(substream);
  441. aacirun->ptr = aacirun->start;
  442. aacirun->bytes = aacirun->period;
  443. return 0;
  444. }
  445. static snd_pcm_uframes_t aaci_pcm_pointer(struct snd_pcm_substream *substream)
  446. {
  447. struct snd_pcm_runtime *runtime = substream->runtime;
  448. struct aaci_runtime *aacirun = runtime->private_data;
  449. ssize_t bytes = aacirun->ptr - aacirun->start;
  450. return bytes_to_frames(runtime, bytes);
  451. }
  452. /*
  453. * Playback specific ALSA stuff
  454. */
  455. static void aaci_pcm_playback_stop(struct aaci_runtime *aacirun)
  456. {
  457. u32 ie;
  458. ie = readl(aacirun->base + AACI_IE);
  459. ie &= ~(IE_URIE|IE_TXIE);
  460. writel(ie, aacirun->base + AACI_IE);
  461. aacirun->cr &= ~CR_EN;
  462. aaci_chan_wait_ready(aacirun, SR_TXB);
  463. writel(aacirun->cr, aacirun->base + AACI_TXCR);
  464. }
  465. static void aaci_pcm_playback_start(struct aaci_runtime *aacirun)
  466. {
  467. u32 ie;
  468. aaci_chan_wait_ready(aacirun, SR_TXB);
  469. aacirun->cr |= CR_EN;
  470. ie = readl(aacirun->base + AACI_IE);
  471. ie |= IE_URIE | IE_TXIE;
  472. writel(ie, aacirun->base + AACI_IE);
  473. writel(aacirun->cr, aacirun->base + AACI_TXCR);
  474. }
  475. static int aaci_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd)
  476. {
  477. struct aaci_runtime *aacirun = substream->runtime->private_data;
  478. unsigned long flags;
  479. int ret = 0;
  480. spin_lock_irqsave(&aacirun->lock, flags);
  481. switch (cmd) {
  482. case SNDRV_PCM_TRIGGER_START:
  483. aaci_pcm_playback_start(aacirun);
  484. break;
  485. case SNDRV_PCM_TRIGGER_RESUME:
  486. aaci_pcm_playback_start(aacirun);
  487. break;
  488. case SNDRV_PCM_TRIGGER_STOP:
  489. aaci_pcm_playback_stop(aacirun);
  490. break;
  491. case SNDRV_PCM_TRIGGER_SUSPEND:
  492. aaci_pcm_playback_stop(aacirun);
  493. break;
  494. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  495. break;
  496. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  497. break;
  498. default:
  499. ret = -EINVAL;
  500. }
  501. spin_unlock_irqrestore(&aacirun->lock, flags);
  502. return ret;
  503. }
  504. static const struct snd_pcm_ops aaci_playback_ops = {
  505. .open = aaci_pcm_open,
  506. .close = aaci_pcm_close,
  507. .hw_params = aaci_pcm_hw_params,
  508. .hw_free = aaci_pcm_hw_free,
  509. .prepare = aaci_pcm_prepare,
  510. .trigger = aaci_pcm_playback_trigger,
  511. .pointer = aaci_pcm_pointer,
  512. };
  513. static void aaci_pcm_capture_stop(struct aaci_runtime *aacirun)
  514. {
  515. u32 ie;
  516. aaci_chan_wait_ready(aacirun, SR_RXB);
  517. ie = readl(aacirun->base + AACI_IE);
  518. ie &= ~(IE_ORIE | IE_RXIE);
  519. writel(ie, aacirun->base+AACI_IE);
  520. aacirun->cr &= ~CR_EN;
  521. writel(aacirun->cr, aacirun->base + AACI_RXCR);
  522. }
  523. static void aaci_pcm_capture_start(struct aaci_runtime *aacirun)
  524. {
  525. u32 ie;
  526. aaci_chan_wait_ready(aacirun, SR_RXB);
  527. #ifdef DEBUG
  528. /* RX Timeout value: bits 28:17 in RXCR */
  529. aacirun->cr |= 0xf << 17;
  530. #endif
  531. aacirun->cr |= CR_EN;
  532. writel(aacirun->cr, aacirun->base + AACI_RXCR);
  533. ie = readl(aacirun->base + AACI_IE);
  534. ie |= IE_ORIE |IE_RXIE; // overrun and rx interrupt -- half full
  535. writel(ie, aacirun->base + AACI_IE);
  536. }
  537. static int aaci_pcm_capture_trigger(struct snd_pcm_substream *substream, int cmd)
  538. {
  539. struct aaci_runtime *aacirun = substream->runtime->private_data;
  540. unsigned long flags;
  541. int ret = 0;
  542. spin_lock_irqsave(&aacirun->lock, flags);
  543. switch (cmd) {
  544. case SNDRV_PCM_TRIGGER_START:
  545. aaci_pcm_capture_start(aacirun);
  546. break;
  547. case SNDRV_PCM_TRIGGER_RESUME:
  548. aaci_pcm_capture_start(aacirun);
  549. break;
  550. case SNDRV_PCM_TRIGGER_STOP:
  551. aaci_pcm_capture_stop(aacirun);
  552. break;
  553. case SNDRV_PCM_TRIGGER_SUSPEND:
  554. aaci_pcm_capture_stop(aacirun);
  555. break;
  556. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  557. break;
  558. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  559. break;
  560. default:
  561. ret = -EINVAL;
  562. }
  563. spin_unlock_irqrestore(&aacirun->lock, flags);
  564. return ret;
  565. }
  566. static int aaci_pcm_capture_prepare(struct snd_pcm_substream *substream)
  567. {
  568. struct snd_pcm_runtime *runtime = substream->runtime;
  569. struct aaci *aaci = substream->private_data;
  570. aaci_pcm_prepare(substream);
  571. /* allow changing of sample rate */
  572. aaci_ac97_write(aaci->ac97, AC97_EXTENDED_STATUS, 0x0001); /* VRA */
  573. aaci_ac97_write(aaci->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
  574. aaci_ac97_write(aaci->ac97, AC97_PCM_MIC_ADC_RATE, runtime->rate);
  575. /* Record select: Mic: 0, Aux: 3, Line: 4 */
  576. aaci_ac97_write(aaci->ac97, AC97_REC_SEL, 0x0404);
  577. return 0;
  578. }
  579. static const struct snd_pcm_ops aaci_capture_ops = {
  580. .open = aaci_pcm_open,
  581. .close = aaci_pcm_close,
  582. .hw_params = aaci_pcm_hw_params,
  583. .hw_free = aaci_pcm_hw_free,
  584. .prepare = aaci_pcm_capture_prepare,
  585. .trigger = aaci_pcm_capture_trigger,
  586. .pointer = aaci_pcm_pointer,
  587. };
  588. /*
  589. * Power Management.
  590. */
  591. #ifdef CONFIG_PM
  592. static int aaci_do_suspend(struct snd_card *card)
  593. {
  594. struct aaci *aaci = card->private_data;
  595. snd_power_change_state(card, SNDRV_CTL_POWER_D3cold);
  596. return 0;
  597. }
  598. static int aaci_do_resume(struct snd_card *card)
  599. {
  600. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  601. return 0;
  602. }
  603. static int aaci_suspend(struct device *dev)
  604. {
  605. struct snd_card *card = dev_get_drvdata(dev);
  606. return card ? aaci_do_suspend(card) : 0;
  607. }
  608. static int aaci_resume(struct device *dev)
  609. {
  610. struct snd_card *card = dev_get_drvdata(dev);
  611. return card ? aaci_do_resume(card) : 0;
  612. }
  613. static SIMPLE_DEV_PM_OPS(aaci_dev_pm_ops, aaci_suspend, aaci_resume);
  614. #define AACI_DEV_PM_OPS (&aaci_dev_pm_ops)
  615. #else
  616. #define AACI_DEV_PM_OPS NULL
  617. #endif
  618. static const struct ac97_pcm ac97_defs[] = {
  619. [0] = { /* Front PCM */
  620. .exclusive = 1,
  621. .r = {
  622. [0] = {
  623. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  624. (1 << AC97_SLOT_PCM_RIGHT) |
  625. (1 << AC97_SLOT_PCM_CENTER) |
  626. (1 << AC97_SLOT_PCM_SLEFT) |
  627. (1 << AC97_SLOT_PCM_SRIGHT) |
  628. (1 << AC97_SLOT_LFE),
  629. },
  630. [1] = {
  631. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  632. (1 << AC97_SLOT_PCM_RIGHT) |
  633. (1 << AC97_SLOT_PCM_LEFT_0) |
  634. (1 << AC97_SLOT_PCM_RIGHT_0),
  635. },
  636. },
  637. },
  638. [1] = { /* PCM in */
  639. .stream = 1,
  640. .exclusive = 1,
  641. .r = {
  642. [0] = {
  643. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  644. (1 << AC97_SLOT_PCM_RIGHT),
  645. },
  646. },
  647. },
  648. [2] = { /* Mic in */
  649. .stream = 1,
  650. .exclusive = 1,
  651. .r = {
  652. [0] = {
  653. .slots = (1 << AC97_SLOT_MIC),
  654. },
  655. },
  656. }
  657. };
  658. static const struct snd_ac97_bus_ops aaci_bus_ops = {
  659. .write = aaci_ac97_write,
  660. .read = aaci_ac97_read,
  661. };
  662. static int aaci_probe_ac97(struct aaci *aaci)
  663. {
  664. struct snd_ac97_template ac97_template;
  665. struct snd_ac97_bus *ac97_bus;
  666. struct snd_ac97 *ac97;
  667. int ret;
  668. /*
  669. * Assert AACIRESET for 2us
  670. */
  671. writel(0, aaci->base + AACI_RESET);
  672. udelay(2);
  673. writel(RESET_NRST, aaci->base + AACI_RESET);
  674. /*
  675. * Give the AC'97 codec more than enough time
  676. * to wake up. (42us = ~2 frames at 48kHz.)
  677. */
  678. udelay(FRAME_PERIOD_US * 2);
  679. ret = snd_ac97_bus(aaci->card, 0, &aaci_bus_ops, aaci, &ac97_bus);
  680. if (ret)
  681. goto out;
  682. ac97_bus->clock = 48000;
  683. aaci->ac97_bus = ac97_bus;
  684. memset(&ac97_template, 0, sizeof(struct snd_ac97_template));
  685. ac97_template.private_data = aaci;
  686. ac97_template.num = 0;
  687. ac97_template.scaps = AC97_SCAP_SKIP_MODEM;
  688. ret = snd_ac97_mixer(ac97_bus, &ac97_template, &ac97);
  689. if (ret)
  690. goto out;
  691. aaci->ac97 = ac97;
  692. /*
  693. * Disable AC97 PC Beep input on audio codecs.
  694. */
  695. if (ac97_is_audio(ac97))
  696. snd_ac97_write_cache(ac97, AC97_PC_BEEP, 0x801e);
  697. ret = snd_ac97_pcm_assign(ac97_bus, ARRAY_SIZE(ac97_defs), ac97_defs);
  698. if (ret)
  699. goto out;
  700. aaci->playback.pcm = &ac97_bus->pcms[0];
  701. aaci->capture.pcm = &ac97_bus->pcms[1];
  702. out:
  703. return ret;
  704. }
  705. static void aaci_free_card(struct snd_card *card)
  706. {
  707. struct aaci *aaci = card->private_data;
  708. iounmap(aaci->base);
  709. }
  710. static struct aaci *aaci_init_card(struct amba_device *dev)
  711. {
  712. struct aaci *aaci;
  713. struct snd_card *card;
  714. int err;
  715. err = snd_card_new(&dev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
  716. THIS_MODULE, sizeof(struct aaci), &card);
  717. if (err < 0)
  718. return NULL;
  719. card->private_free = aaci_free_card;
  720. strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver));
  721. strlcpy(card->shortname, "ARM AC'97 Interface", sizeof(card->shortname));
  722. snprintf(card->longname, sizeof(card->longname),
  723. "%s PL%03x rev%u at 0x%08llx, irq %d",
  724. card->shortname, amba_part(dev), amba_rev(dev),
  725. (unsigned long long)dev->res.start, dev->irq[0]);
  726. aaci = card->private_data;
  727. mutex_init(&aaci->ac97_sem);
  728. mutex_init(&aaci->irq_lock);
  729. aaci->card = card;
  730. aaci->dev = dev;
  731. /* Set MAINCR to allow slot 1 and 2 data IO */
  732. aaci->maincr = MAINCR_IE | MAINCR_SL1RXEN | MAINCR_SL1TXEN |
  733. MAINCR_SL2RXEN | MAINCR_SL2TXEN;
  734. return aaci;
  735. }
  736. static int aaci_init_pcm(struct aaci *aaci)
  737. {
  738. struct snd_pcm *pcm;
  739. int ret;
  740. ret = snd_pcm_new(aaci->card, "AACI AC'97", 0, 1, 1, &pcm);
  741. if (ret == 0) {
  742. aaci->pcm = pcm;
  743. pcm->private_data = aaci;
  744. pcm->info_flags = 0;
  745. strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name));
  746. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &aaci_playback_ops);
  747. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &aaci_capture_ops);
  748. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  749. aaci->card->dev,
  750. 0, 64 * 1024);
  751. }
  752. return ret;
  753. }
  754. static unsigned int aaci_size_fifo(struct aaci *aaci)
  755. {
  756. struct aaci_runtime *aacirun = &aaci->playback;
  757. int i;
  758. /*
  759. * Enable the channel, but don't assign it to any slots, so
  760. * it won't empty onto the AC'97 link.
  761. */
  762. writel(CR_FEN | CR_SZ16 | CR_EN, aacirun->base + AACI_TXCR);
  763. for (i = 0; !(readl(aacirun->base + AACI_SR) & SR_TXFF) && i < 4096; i++)
  764. writel(0, aacirun->fifo);
  765. writel(0, aacirun->base + AACI_TXCR);
  766. /*
  767. * Re-initialise the AACI after the FIFO depth test, to
  768. * ensure that the FIFOs are empty. Unfortunately, merely
  769. * disabling the channel doesn't clear the FIFO.
  770. */
  771. writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR);
  772. readl(aaci->base + AACI_MAINCR);
  773. udelay(1);
  774. writel(aaci->maincr, aaci->base + AACI_MAINCR);
  775. /*
  776. * If we hit 4096 entries, we failed. Go back to the specified
  777. * fifo depth.
  778. */
  779. if (i == 4096)
  780. i = 8;
  781. return i;
  782. }
  783. static int aaci_probe(struct amba_device *dev,
  784. const struct amba_id *id)
  785. {
  786. struct aaci *aaci;
  787. int ret, i;
  788. ret = amba_request_regions(dev, NULL);
  789. if (ret)
  790. return ret;
  791. aaci = aaci_init_card(dev);
  792. if (!aaci) {
  793. ret = -ENOMEM;
  794. goto out;
  795. }
  796. aaci->base = ioremap(dev->res.start, resource_size(&dev->res));
  797. if (!aaci->base) {
  798. ret = -ENOMEM;
  799. goto out;
  800. }
  801. /*
  802. * Playback uses AACI channel 0
  803. */
  804. spin_lock_init(&aaci->playback.lock);
  805. aaci->playback.base = aaci->base + AACI_CSCH1;
  806. aaci->playback.fifo = aaci->base + AACI_DR1;
  807. /*
  808. * Capture uses AACI channel 0
  809. */
  810. spin_lock_init(&aaci->capture.lock);
  811. aaci->capture.base = aaci->base + AACI_CSCH1;
  812. aaci->capture.fifo = aaci->base + AACI_DR1;
  813. for (i = 0; i < 4; i++) {
  814. void __iomem *base = aaci->base + i * 0x14;
  815. writel(0, base + AACI_IE);
  816. writel(0, base + AACI_TXCR);
  817. writel(0, base + AACI_RXCR);
  818. }
  819. writel(0x1fff, aaci->base + AACI_INTCLR);
  820. writel(aaci->maincr, aaci->base + AACI_MAINCR);
  821. /*
  822. * Fix: ac97 read back fail errors by reading
  823. * from any arbitrary aaci register.
  824. */
  825. readl(aaci->base + AACI_CSCH1);
  826. ret = aaci_probe_ac97(aaci);
  827. if (ret)
  828. goto out;
  829. /*
  830. * Size the FIFOs (must be multiple of 16).
  831. * This is the number of entries in the FIFO.
  832. */
  833. aaci->fifo_depth = aaci_size_fifo(aaci);
  834. if (aaci->fifo_depth & 15) {
  835. printk(KERN_WARNING "AACI: FIFO depth %d not supported\n",
  836. aaci->fifo_depth);
  837. ret = -ENODEV;
  838. goto out;
  839. }
  840. ret = aaci_init_pcm(aaci);
  841. if (ret)
  842. goto out;
  843. ret = snd_card_register(aaci->card);
  844. if (ret == 0) {
  845. dev_info(&dev->dev, "%s\n", aaci->card->longname);
  846. dev_info(&dev->dev, "FIFO %u entries\n", aaci->fifo_depth);
  847. amba_set_drvdata(dev, aaci->card);
  848. return ret;
  849. }
  850. out:
  851. if (aaci)
  852. snd_card_free(aaci->card);
  853. amba_release_regions(dev);
  854. return ret;
  855. }
  856. static void aaci_remove(struct amba_device *dev)
  857. {
  858. struct snd_card *card = amba_get_drvdata(dev);
  859. if (card) {
  860. struct aaci *aaci = card->private_data;
  861. writel(0, aaci->base + AACI_MAINCR);
  862. snd_card_free(card);
  863. amba_release_regions(dev);
  864. }
  865. }
  866. static struct amba_id aaci_ids[] = {
  867. {
  868. .id = 0x00041041,
  869. .mask = 0x000fffff,
  870. },
  871. { 0, 0 },
  872. };
  873. MODULE_DEVICE_TABLE(amba, aaci_ids);
  874. static struct amba_driver aaci_driver = {
  875. .drv = {
  876. .name = DRIVER_NAME,
  877. .pm = AACI_DEV_PM_OPS,
  878. },
  879. .probe = aaci_probe,
  880. .remove = aaci_remove,
  881. .id_table = aaci_ids,
  882. };
  883. module_amba_driver(aaci_driver);
  884. MODULE_LICENSE("GPL");
  885. MODULE_DESCRIPTION("ARM PrimeCell PL041 Advanced Audio CODEC Interface driver");