imx-ipu-v3.h 16 KB

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  1. /*
  2. * Copyright 2005-2009 Freescale Semiconductor, Inc.
  3. *
  4. * The code contained herein is licensed under the GNU Lesser General
  5. * Public License. You may obtain a copy of the GNU Lesser General
  6. * Public License Version 2.1 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/lgpl-license.html
  9. * http://www.gnu.org/copyleft/lgpl.html
  10. */
  11. #ifndef __DRM_IPU_H__
  12. #define __DRM_IPU_H__
  13. #include <linux/types.h>
  14. #include <linux/videodev2.h>
  15. #include <linux/bitmap.h>
  16. #include <linux/fb.h>
  17. #include <linux/of.h>
  18. #include <media/v4l2-mediabus.h>
  19. #include <video/videomode.h>
  20. struct ipu_soc;
  21. enum ipuv3_type {
  22. IPUV3EX,
  23. IPUV3M,
  24. IPUV3H,
  25. };
  26. #define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
  27. /*
  28. * Bitfield of Display Interface signal polarities.
  29. */
  30. struct ipu_di_signal_cfg {
  31. unsigned data_pol:1; /* true = inverted */
  32. unsigned clk_pol:1; /* true = rising edge */
  33. unsigned enable_pol:1;
  34. struct videomode mode;
  35. u32 bus_format;
  36. u32 v_to_h_sync;
  37. #define IPU_DI_CLKMODE_SYNC (1 << 0)
  38. #define IPU_DI_CLKMODE_EXT (1 << 1)
  39. unsigned long clkflags;
  40. u8 hsync_pin;
  41. u8 vsync_pin;
  42. };
  43. /*
  44. * Enumeration of CSI destinations
  45. */
  46. enum ipu_csi_dest {
  47. IPU_CSI_DEST_IDMAC, /* to memory via SMFC */
  48. IPU_CSI_DEST_IC, /* to Image Converter */
  49. IPU_CSI_DEST_VDIC, /* to VDIC */
  50. };
  51. /*
  52. * Enumeration of IPU rotation modes
  53. */
  54. #define IPU_ROT_BIT_VFLIP (1 << 0)
  55. #define IPU_ROT_BIT_HFLIP (1 << 1)
  56. #define IPU_ROT_BIT_90 (1 << 2)
  57. enum ipu_rotate_mode {
  58. IPU_ROTATE_NONE = 0,
  59. IPU_ROTATE_VERT_FLIP = IPU_ROT_BIT_VFLIP,
  60. IPU_ROTATE_HORIZ_FLIP = IPU_ROT_BIT_HFLIP,
  61. IPU_ROTATE_180 = (IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP),
  62. IPU_ROTATE_90_RIGHT = IPU_ROT_BIT_90,
  63. IPU_ROTATE_90_RIGHT_VFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_VFLIP),
  64. IPU_ROTATE_90_RIGHT_HFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_HFLIP),
  65. IPU_ROTATE_90_LEFT = (IPU_ROT_BIT_90 |
  66. IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP),
  67. };
  68. /* 90-degree rotations require the IRT unit */
  69. #define ipu_rot_mode_is_irt(m) (((m) & IPU_ROT_BIT_90) != 0)
  70. enum ipu_color_space {
  71. IPUV3_COLORSPACE_RGB,
  72. IPUV3_COLORSPACE_YUV,
  73. IPUV3_COLORSPACE_UNKNOWN,
  74. };
  75. /*
  76. * Enumeration of VDI MOTION select
  77. */
  78. enum ipu_motion_sel {
  79. MOTION_NONE = 0,
  80. LOW_MOTION,
  81. MED_MOTION,
  82. HIGH_MOTION,
  83. };
  84. struct ipuv3_channel;
  85. enum ipu_channel_irq {
  86. IPU_IRQ_EOF = 0,
  87. IPU_IRQ_NFACK = 64,
  88. IPU_IRQ_NFB4EOF = 128,
  89. IPU_IRQ_EOS = 192,
  90. };
  91. /*
  92. * Enumeration of IDMAC channels
  93. */
  94. #define IPUV3_CHANNEL_CSI0 0
  95. #define IPUV3_CHANNEL_CSI1 1
  96. #define IPUV3_CHANNEL_CSI2 2
  97. #define IPUV3_CHANNEL_CSI3 3
  98. #define IPUV3_CHANNEL_VDI_MEM_IC_VF 5
  99. /*
  100. * NOTE: channels 6,7 are unused in the IPU and are not IDMAC channels,
  101. * but the direct CSI->VDI linking is handled the same way as IDMAC
  102. * channel linking in the FSU via the IPU_FS_PROC_FLOW registers, so
  103. * these channel names are used to support the direct CSI->VDI link.
  104. */
  105. #define IPUV3_CHANNEL_CSI_DIRECT 6
  106. #define IPUV3_CHANNEL_CSI_VDI_PREV 7
  107. #define IPUV3_CHANNEL_MEM_VDI_PREV 8
  108. #define IPUV3_CHANNEL_MEM_VDI_CUR 9
  109. #define IPUV3_CHANNEL_MEM_VDI_NEXT 10
  110. #define IPUV3_CHANNEL_MEM_IC_PP 11
  111. #define IPUV3_CHANNEL_MEM_IC_PRP_VF 12
  112. #define IPUV3_CHANNEL_VDI_MEM_RECENT 13
  113. #define IPUV3_CHANNEL_G_MEM_IC_PRP_VF 14
  114. #define IPUV3_CHANNEL_G_MEM_IC_PP 15
  115. #define IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA 17
  116. #define IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA 18
  117. #define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA 19
  118. #define IPUV3_CHANNEL_IC_PRP_ENC_MEM 20
  119. #define IPUV3_CHANNEL_IC_PRP_VF_MEM 21
  120. #define IPUV3_CHANNEL_IC_PP_MEM 22
  121. #define IPUV3_CHANNEL_MEM_BG_SYNC 23
  122. #define IPUV3_CHANNEL_MEM_BG_ASYNC 24
  123. #define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB 25
  124. #define IPUV3_CHANNEL_MEM_VDI_PLANE3_COMB 26
  125. #define IPUV3_CHANNEL_MEM_FG_SYNC 27
  126. #define IPUV3_CHANNEL_MEM_DC_SYNC 28
  127. #define IPUV3_CHANNEL_MEM_FG_ASYNC 29
  128. #define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA 31
  129. #define IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA 33
  130. #define IPUV3_CHANNEL_DC_MEM_READ 40
  131. #define IPUV3_CHANNEL_MEM_DC_ASYNC 41
  132. #define IPUV3_CHANNEL_MEM_DC_COMMAND 42
  133. #define IPUV3_CHANNEL_MEM_DC_COMMAND2 43
  134. #define IPUV3_CHANNEL_MEM_DC_OUTPUT_MASK 44
  135. #define IPUV3_CHANNEL_MEM_ROT_ENC 45
  136. #define IPUV3_CHANNEL_MEM_ROT_VF 46
  137. #define IPUV3_CHANNEL_MEM_ROT_PP 47
  138. #define IPUV3_CHANNEL_ROT_ENC_MEM 48
  139. #define IPUV3_CHANNEL_ROT_VF_MEM 49
  140. #define IPUV3_CHANNEL_ROT_PP_MEM 50
  141. #define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA 51
  142. #define IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA 52
  143. #define IPUV3_NUM_CHANNELS 64
  144. static inline int ipu_channel_alpha_channel(int ch_num)
  145. {
  146. switch (ch_num) {
  147. case IPUV3_CHANNEL_G_MEM_IC_PRP_VF:
  148. return IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA;
  149. case IPUV3_CHANNEL_G_MEM_IC_PP:
  150. return IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA;
  151. case IPUV3_CHANNEL_MEM_FG_SYNC:
  152. return IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA;
  153. case IPUV3_CHANNEL_MEM_FG_ASYNC:
  154. return IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA;
  155. case IPUV3_CHANNEL_MEM_BG_SYNC:
  156. return IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA;
  157. case IPUV3_CHANNEL_MEM_BG_ASYNC:
  158. return IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA;
  159. case IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB:
  160. return IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA;
  161. default:
  162. return -EINVAL;
  163. }
  164. }
  165. int ipu_map_irq(struct ipu_soc *ipu, int irq);
  166. int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
  167. enum ipu_channel_irq irq);
  168. #define IPU_IRQ_DP_SF_START (448 + 2)
  169. #define IPU_IRQ_DP_SF_END (448 + 3)
  170. #define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END,
  171. #define IPU_IRQ_DC_FC_0 (448 + 8)
  172. #define IPU_IRQ_DC_FC_1 (448 + 9)
  173. #define IPU_IRQ_DC_FC_2 (448 + 10)
  174. #define IPU_IRQ_DC_FC_3 (448 + 11)
  175. #define IPU_IRQ_DC_FC_4 (448 + 12)
  176. #define IPU_IRQ_DC_FC_6 (448 + 13)
  177. #define IPU_IRQ_VSYNC_PRE_0 (448 + 14)
  178. #define IPU_IRQ_VSYNC_PRE_1 (448 + 15)
  179. /*
  180. * IPU Common functions
  181. */
  182. int ipu_get_num(struct ipu_soc *ipu);
  183. void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2);
  184. void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi);
  185. void ipu_dump(struct ipu_soc *ipu);
  186. /*
  187. * IPU Image DMA Controller (idmac) functions
  188. */
  189. struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
  190. void ipu_idmac_put(struct ipuv3_channel *);
  191. int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
  192. int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
  193. void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable);
  194. int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts);
  195. int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
  196. void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
  197. bool doublebuffer);
  198. int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
  199. bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num);
  200. void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
  201. void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num);
  202. int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch);
  203. int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch);
  204. int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink);
  205. int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink);
  206. /*
  207. * IPU Channel Parameter Memory (cpmem) functions
  208. */
  209. struct ipu_rgb {
  210. struct fb_bitfield red;
  211. struct fb_bitfield green;
  212. struct fb_bitfield blue;
  213. struct fb_bitfield transp;
  214. int bits_per_pixel;
  215. };
  216. struct ipu_image {
  217. struct v4l2_pix_format pix;
  218. struct v4l2_rect rect;
  219. dma_addr_t phys0;
  220. dma_addr_t phys1;
  221. /* chroma plane offset overrides */
  222. u32 u_offset;
  223. u32 v_offset;
  224. };
  225. void ipu_cpmem_zero(struct ipuv3_channel *ch);
  226. void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
  227. void ipu_cpmem_skip_odd_chroma_rows(struct ipuv3_channel *ch);
  228. void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
  229. void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
  230. void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
  231. void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off);
  232. void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride,
  233. u32 pixelformat);
  234. void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
  235. int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch);
  236. void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
  237. void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch);
  238. void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
  239. enum ipu_rotate_mode rot);
  240. int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
  241. const struct ipu_rgb *rgb);
  242. int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
  243. void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
  244. void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
  245. unsigned int uv_stride,
  246. unsigned int u_offset,
  247. unsigned int v_offset);
  248. int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
  249. int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image);
  250. void ipu_cpmem_dump(struct ipuv3_channel *ch);
  251. /*
  252. * IPU Display Controller (dc) functions
  253. */
  254. struct ipu_dc;
  255. struct ipu_di;
  256. struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
  257. void ipu_dc_put(struct ipu_dc *dc);
  258. int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
  259. u32 pixel_fmt, u32 width);
  260. void ipu_dc_enable(struct ipu_soc *ipu);
  261. void ipu_dc_enable_channel(struct ipu_dc *dc);
  262. void ipu_dc_disable_channel(struct ipu_dc *dc);
  263. void ipu_dc_disable(struct ipu_soc *ipu);
  264. /*
  265. * IPU Display Interface (di) functions
  266. */
  267. struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
  268. void ipu_di_put(struct ipu_di *);
  269. int ipu_di_disable(struct ipu_di *);
  270. int ipu_di_enable(struct ipu_di *);
  271. int ipu_di_get_num(struct ipu_di *);
  272. int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode);
  273. int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
  274. /*
  275. * IPU Display Multi FIFO Controller (dmfc) functions
  276. */
  277. struct dmfc_channel;
  278. int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
  279. void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
  280. void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width);
  281. struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
  282. void ipu_dmfc_put(struct dmfc_channel *dmfc);
  283. /*
  284. * IPU Display Processor (dp) functions
  285. */
  286. #define IPU_DP_FLOW_SYNC_BG 0
  287. #define IPU_DP_FLOW_SYNC_FG 1
  288. #define IPU_DP_FLOW_ASYNC0_BG 2
  289. #define IPU_DP_FLOW_ASYNC0_FG 3
  290. #define IPU_DP_FLOW_ASYNC1_BG 4
  291. #define IPU_DP_FLOW_ASYNC1_FG 5
  292. struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
  293. void ipu_dp_put(struct ipu_dp *);
  294. int ipu_dp_enable(struct ipu_soc *ipu);
  295. int ipu_dp_enable_channel(struct ipu_dp *dp);
  296. void ipu_dp_disable_channel(struct ipu_dp *dp, bool sync);
  297. void ipu_dp_disable(struct ipu_soc *ipu);
  298. int ipu_dp_setup_channel(struct ipu_dp *dp,
  299. enum ipu_color_space in, enum ipu_color_space out);
  300. int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
  301. int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
  302. bool bg_chan);
  303. /*
  304. * IPU Prefetch Resolve Gasket (prg) functions
  305. */
  306. int ipu_prg_max_active_channels(void);
  307. bool ipu_prg_present(struct ipu_soc *ipu);
  308. bool ipu_prg_format_supported(struct ipu_soc *ipu, uint32_t format,
  309. uint64_t modifier);
  310. int ipu_prg_enable(struct ipu_soc *ipu);
  311. void ipu_prg_disable(struct ipu_soc *ipu);
  312. void ipu_prg_channel_disable(struct ipuv3_channel *ipu_chan);
  313. int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan,
  314. unsigned int axi_id, unsigned int width,
  315. unsigned int height, unsigned int stride,
  316. u32 format, uint64_t modifier, unsigned long *eba);
  317. bool ipu_prg_channel_configure_pending(struct ipuv3_channel *ipu_chan);
  318. /*
  319. * IPU CMOS Sensor Interface (csi) functions
  320. */
  321. struct ipu_csi;
  322. int ipu_csi_init_interface(struct ipu_csi *csi,
  323. const struct v4l2_mbus_config *mbus_cfg,
  324. const struct v4l2_mbus_framefmt *infmt,
  325. const struct v4l2_mbus_framefmt *outfmt);
  326. bool ipu_csi_is_interlaced(struct ipu_csi *csi);
  327. void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w);
  328. void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w);
  329. void ipu_csi_set_downsize(struct ipu_csi *csi, bool horiz, bool vert);
  330. void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
  331. u32 r_value, u32 g_value, u32 b_value,
  332. u32 pix_clk);
  333. int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
  334. struct v4l2_mbus_framefmt *mbus_fmt);
  335. int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
  336. u32 max_ratio, u32 id);
  337. int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest);
  338. int ipu_csi_enable(struct ipu_csi *csi);
  339. int ipu_csi_disable(struct ipu_csi *csi);
  340. struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id);
  341. void ipu_csi_put(struct ipu_csi *csi);
  342. void ipu_csi_dump(struct ipu_csi *csi);
  343. /*
  344. * IPU Image Converter (ic) functions
  345. */
  346. enum ipu_ic_task {
  347. IC_TASK_ENCODER,
  348. IC_TASK_VIEWFINDER,
  349. IC_TASK_POST_PROCESSOR,
  350. IC_NUM_TASKS,
  351. };
  352. /*
  353. * The parameters that describe a colorspace according to the
  354. * Image Converter:
  355. * - Y'CbCr encoding
  356. * - quantization
  357. * - "colorspace" (RGB or YUV).
  358. */
  359. struct ipu_ic_colorspace {
  360. enum v4l2_ycbcr_encoding enc;
  361. enum v4l2_quantization quant;
  362. enum ipu_color_space cs;
  363. };
  364. static inline void
  365. ipu_ic_fill_colorspace(struct ipu_ic_colorspace *ic_cs,
  366. enum v4l2_ycbcr_encoding enc,
  367. enum v4l2_quantization quant,
  368. enum ipu_color_space cs)
  369. {
  370. ic_cs->enc = enc;
  371. ic_cs->quant = quant;
  372. ic_cs->cs = cs;
  373. }
  374. struct ipu_ic_csc_params {
  375. s16 coeff[3][3]; /* signed 9-bit integer coefficients */
  376. s16 offset[3]; /* signed 11+2-bit fixed point offset */
  377. u8 scale:2; /* scale coefficients * 2^(scale-1) */
  378. bool sat:1; /* saturate to (16, 235(Y) / 240(U, V)) */
  379. };
  380. struct ipu_ic_csc {
  381. struct ipu_ic_colorspace in_cs;
  382. struct ipu_ic_colorspace out_cs;
  383. struct ipu_ic_csc_params params;
  384. };
  385. struct ipu_ic;
  386. int __ipu_ic_calc_csc(struct ipu_ic_csc *csc);
  387. int ipu_ic_calc_csc(struct ipu_ic_csc *csc,
  388. enum v4l2_ycbcr_encoding in_enc,
  389. enum v4l2_quantization in_quant,
  390. enum ipu_color_space in_cs,
  391. enum v4l2_ycbcr_encoding out_enc,
  392. enum v4l2_quantization out_quant,
  393. enum ipu_color_space out_cs);
  394. int ipu_ic_task_init(struct ipu_ic *ic,
  395. const struct ipu_ic_csc *csc,
  396. int in_width, int in_height,
  397. int out_width, int out_height);
  398. int ipu_ic_task_init_rsc(struct ipu_ic *ic,
  399. const struct ipu_ic_csc *csc,
  400. int in_width, int in_height,
  401. int out_width, int out_height,
  402. u32 rsc);
  403. int ipu_ic_task_graphics_init(struct ipu_ic *ic,
  404. const struct ipu_ic_colorspace *g_in_cs,
  405. bool galpha_en, u32 galpha,
  406. bool colorkey_en, u32 colorkey);
  407. void ipu_ic_task_enable(struct ipu_ic *ic);
  408. void ipu_ic_task_disable(struct ipu_ic *ic);
  409. int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel,
  410. u32 width, u32 height, int burst_size,
  411. enum ipu_rotate_mode rot);
  412. int ipu_ic_enable(struct ipu_ic *ic);
  413. int ipu_ic_disable(struct ipu_ic *ic);
  414. struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task);
  415. void ipu_ic_put(struct ipu_ic *ic);
  416. void ipu_ic_dump(struct ipu_ic *ic);
  417. /*
  418. * IPU Video De-Interlacer (vdi) functions
  419. */
  420. struct ipu_vdi;
  421. void ipu_vdi_set_field_order(struct ipu_vdi *vdi, v4l2_std_id std, u32 field);
  422. void ipu_vdi_set_motion(struct ipu_vdi *vdi, enum ipu_motion_sel motion_sel);
  423. void ipu_vdi_setup(struct ipu_vdi *vdi, u32 code, int xres, int yres);
  424. void ipu_vdi_unsetup(struct ipu_vdi *vdi);
  425. int ipu_vdi_enable(struct ipu_vdi *vdi);
  426. int ipu_vdi_disable(struct ipu_vdi *vdi);
  427. struct ipu_vdi *ipu_vdi_get(struct ipu_soc *ipu);
  428. void ipu_vdi_put(struct ipu_vdi *vdi);
  429. /*
  430. * IPU Sensor Multiple FIFO Controller (SMFC) functions
  431. */
  432. struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno);
  433. void ipu_smfc_put(struct ipu_smfc *smfc);
  434. int ipu_smfc_enable(struct ipu_smfc *smfc);
  435. int ipu_smfc_disable(struct ipu_smfc *smfc);
  436. int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id);
  437. int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize);
  438. int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level);
  439. enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
  440. enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
  441. int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
  442. bool hflip, bool vflip);
  443. int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
  444. bool hflip, bool vflip);
  445. struct ipu_client_platformdata {
  446. int csi;
  447. int di;
  448. int dc;
  449. int dp;
  450. int dma[2];
  451. struct device_node *of_node;
  452. };
  453. #endif /* __DRM_IPU_H__ */