aty128.h 13 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /* $Id: aty128.h,v 1.1 1999/10/12 11:00:40 geert Exp $
  3. * linux/drivers/video/aty128.h
  4. * Register definitions for ATI Rage128 boards
  5. *
  6. * Anthony Tong <atong@uiuc.edu>, 1999
  7. * Brad Douglas <brad@neruo.com>, 2000
  8. */
  9. #ifndef REG_RAGE128_H
  10. #define REG_RAGE128_H
  11. #define CLOCK_CNTL_INDEX 0x0008
  12. #define CLOCK_CNTL_DATA 0x000c
  13. #define BIOS_0_SCRATCH 0x0010
  14. #define BUS_CNTL 0x0030
  15. #define BUS_CNTL1 0x0034
  16. #define GEN_INT_CNTL 0x0040
  17. #define CRTC_GEN_CNTL 0x0050
  18. #define CRTC_EXT_CNTL 0x0054
  19. #define DAC_CNTL 0x0058
  20. #define I2C_CNTL_1 0x0094
  21. #define PALETTE_INDEX 0x00b0
  22. #define PALETTE_DATA 0x00b4
  23. #define CNFG_CNTL 0x00e0
  24. #define GEN_RESET_CNTL 0x00f0
  25. #define CNFG_MEMSIZE 0x00f8
  26. #define MEM_CNTL 0x0140
  27. #define MEM_POWER_MISC 0x015c
  28. #define AGP_BASE 0x0170
  29. #define AGP_CNTL 0x0174
  30. #define AGP_APER_OFFSET 0x0178
  31. #define PCI_GART_PAGE 0x017c
  32. #define PC_NGUI_MODE 0x0180
  33. #define PC_NGUI_CTLSTAT 0x0184
  34. #define MPP_TB_CONFIG 0x01C0
  35. #define MPP_GP_CONFIG 0x01C8
  36. #define VIPH_CONTROL 0x01D0
  37. #define CRTC_H_TOTAL_DISP 0x0200
  38. #define CRTC_H_SYNC_STRT_WID 0x0204
  39. #define CRTC_V_TOTAL_DISP 0x0208
  40. #define CRTC_V_SYNC_STRT_WID 0x020c
  41. #define CRTC_VLINE_CRNT_VLINE 0x0210
  42. #define CRTC_CRNT_FRAME 0x0214
  43. #define CRTC_GUI_TRIG_VLINE 0x0218
  44. #define CRTC_OFFSET 0x0224
  45. #define CRTC_OFFSET_CNTL 0x0228
  46. #define CRTC_PITCH 0x022c
  47. #define OVR_CLR 0x0230
  48. #define OVR_WID_LEFT_RIGHT 0x0234
  49. #define OVR_WID_TOP_BOTTOM 0x0238
  50. #define LVDS_GEN_CNTL 0x02d0
  51. #define DDA_CONFIG 0x02e0
  52. #define DDA_ON_OFF 0x02e4
  53. #define VGA_DDA_CONFIG 0x02e8
  54. #define VGA_DDA_ON_OFF 0x02ec
  55. #define CRTC2_H_TOTAL_DISP 0x0300
  56. #define CRTC2_H_SYNC_STRT_WID 0x0304
  57. #define CRTC2_V_TOTAL_DISP 0x0308
  58. #define CRTC2_V_SYNC_STRT_WID 0x030c
  59. #define CRTC2_VLINE_CRNT_VLINE 0x0310
  60. #define CRTC2_CRNT_FRAME 0x0314
  61. #define CRTC2_GUI_TRIG_VLINE 0x0318
  62. #define CRTC2_OFFSET 0x0324
  63. #define CRTC2_OFFSET_CNTL 0x0328
  64. #define CRTC2_PITCH 0x032c
  65. #define DDA2_CONFIG 0x03e0
  66. #define DDA2_ON_OFF 0x03e4
  67. #define CRTC2_GEN_CNTL 0x03f8
  68. #define CRTC2_STATUS 0x03fc
  69. #define OV0_SCALE_CNTL 0x0420
  70. #define SUBPIC_CNTL 0x0540
  71. #define PM4_BUFFER_OFFSET 0x0700
  72. #define PM4_BUFFER_CNTL 0x0704
  73. #define PM4_BUFFER_WM_CNTL 0x0708
  74. #define PM4_BUFFER_DL_RPTR_ADDR 0x070c
  75. #define PM4_BUFFER_DL_RPTR 0x0710
  76. #define PM4_BUFFER_DL_WPTR 0x0714
  77. #define PM4_VC_FPU_SETUP 0x071c
  78. #define PM4_FPU_CNTL 0x0720
  79. #define PM4_VC_FORMAT 0x0724
  80. #define PM4_VC_CNTL 0x0728
  81. #define PM4_VC_I01 0x072c
  82. #define PM4_VC_VLOFF 0x0730
  83. #define PM4_VC_VLSIZE 0x0734
  84. #define PM4_IW_INDOFF 0x0738
  85. #define PM4_IW_INDSIZE 0x073c
  86. #define PM4_FPU_FPX0 0x0740
  87. #define PM4_FPU_FPY0 0x0744
  88. #define PM4_FPU_FPX1 0x0748
  89. #define PM4_FPU_FPY1 0x074c
  90. #define PM4_FPU_FPX2 0x0750
  91. #define PM4_FPU_FPY2 0x0754
  92. #define PM4_FPU_FPY3 0x0758
  93. #define PM4_FPU_FPY4 0x075c
  94. #define PM4_FPU_FPY5 0x0760
  95. #define PM4_FPU_FPY6 0x0764
  96. #define PM4_FPU_FPR 0x0768
  97. #define PM4_FPU_FPG 0x076c
  98. #define PM4_FPU_FPB 0x0770
  99. #define PM4_FPU_FPA 0x0774
  100. #define PM4_FPU_INTXY0 0x0780
  101. #define PM4_FPU_INTXY1 0x0784
  102. #define PM4_FPU_INTXY2 0x0788
  103. #define PM4_FPU_INTARGB 0x078c
  104. #define PM4_FPU_FPTWICEAREA 0x0790
  105. #define PM4_FPU_DMAJOR01 0x0794
  106. #define PM4_FPU_DMAJOR12 0x0798
  107. #define PM4_FPU_DMAJOR02 0x079c
  108. #define PM4_FPU_STAT 0x07a0
  109. #define PM4_STAT 0x07b8
  110. #define PM4_TEST_CNTL 0x07d0
  111. #define PM4_MICROCODE_ADDR 0x07d4
  112. #define PM4_MICROCODE_RADDR 0x07d8
  113. #define PM4_MICROCODE_DATAH 0x07dc
  114. #define PM4_MICROCODE_DATAL 0x07e0
  115. #define PM4_CMDFIFO_ADDR 0x07e4
  116. #define PM4_CMDFIFO_DATAH 0x07e8
  117. #define PM4_CMDFIFO_DATAL 0x07ec
  118. #define PM4_BUFFER_ADDR 0x07f0
  119. #define PM4_BUFFER_DATAH 0x07f4
  120. #define PM4_BUFFER_DATAL 0x07f8
  121. #define PM4_MICRO_CNTL 0x07fc
  122. #define CAP0_TRIG_CNTL 0x0950
  123. #define CAP1_TRIG_CNTL 0x09c0
  124. /******************************************************************************
  125. * GUI Block Memory Mapped Registers *
  126. * These registers are FIFOed. *
  127. *****************************************************************************/
  128. #define PM4_FIFO_DATA_EVEN 0x1000
  129. #define PM4_FIFO_DATA_ODD 0x1004
  130. #define DST_OFFSET 0x1404
  131. #define DST_PITCH 0x1408
  132. #define DST_WIDTH 0x140c
  133. #define DST_HEIGHT 0x1410
  134. #define SRC_X 0x1414
  135. #define SRC_Y 0x1418
  136. #define DST_X 0x141c
  137. #define DST_Y 0x1420
  138. #define SRC_PITCH_OFFSET 0x1428
  139. #define DST_PITCH_OFFSET 0x142c
  140. #define SRC_Y_X 0x1434
  141. #define DST_Y_X 0x1438
  142. #define DST_HEIGHT_WIDTH 0x143c
  143. #define DP_GUI_MASTER_CNTL 0x146c
  144. #define BRUSH_SCALE 0x1470
  145. #define BRUSH_Y_X 0x1474
  146. #define DP_BRUSH_BKGD_CLR 0x1478
  147. #define DP_BRUSH_FRGD_CLR 0x147c
  148. #define DST_WIDTH_X 0x1588
  149. #define DST_HEIGHT_WIDTH_8 0x158c
  150. #define SRC_X_Y 0x1590
  151. #define DST_X_Y 0x1594
  152. #define DST_WIDTH_HEIGHT 0x1598
  153. #define DST_WIDTH_X_INCY 0x159c
  154. #define DST_HEIGHT_Y 0x15a0
  155. #define DST_X_SUB 0x15a4
  156. #define DST_Y_SUB 0x15a8
  157. #define SRC_OFFSET 0x15ac
  158. #define SRC_PITCH 0x15b0
  159. #define DST_HEIGHT_WIDTH_BW 0x15b4
  160. #define CLR_CMP_CNTL 0x15c0
  161. #define CLR_CMP_CLR_SRC 0x15c4
  162. #define CLR_CMP_CLR_DST 0x15c8
  163. #define CLR_CMP_MASK 0x15cc
  164. #define DP_SRC_FRGD_CLR 0x15d8
  165. #define DP_SRC_BKGD_CLR 0x15dc
  166. #define DST_BRES_ERR 0x1628
  167. #define DST_BRES_INC 0x162c
  168. #define DST_BRES_DEC 0x1630
  169. #define DST_BRES_LNTH 0x1634
  170. #define DST_BRES_LNTH_SUB 0x1638
  171. #define SC_LEFT 0x1640
  172. #define SC_RIGHT 0x1644
  173. #define SC_TOP 0x1648
  174. #define SC_BOTTOM 0x164c
  175. #define SRC_SC_RIGHT 0x1654
  176. #define SRC_SC_BOTTOM 0x165c
  177. #define GUI_DEBUG0 0x16a0
  178. #define GUI_DEBUG1 0x16a4
  179. #define GUI_TIMEOUT 0x16b0
  180. #define GUI_TIMEOUT0 0x16b4
  181. #define GUI_TIMEOUT1 0x16b8
  182. #define GUI_PROBE 0x16bc
  183. #define DP_CNTL 0x16c0
  184. #define DP_DATATYPE 0x16c4
  185. #define DP_MIX 0x16c8
  186. #define DP_WRITE_MASK 0x16cc
  187. #define DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0
  188. #define DEFAULT_OFFSET 0x16e0
  189. #define DEFAULT_PITCH 0x16e4
  190. #define DEFAULT_SC_BOTTOM_RIGHT 0x16e8
  191. #define SC_TOP_LEFT 0x16ec
  192. #define SC_BOTTOM_RIGHT 0x16f0
  193. #define SRC_SC_BOTTOM_RIGHT 0x16f4
  194. #define WAIT_UNTIL 0x1720
  195. #define CACHE_CNTL 0x1724
  196. #define GUI_STAT 0x1740
  197. #define PC_GUI_MODE 0x1744
  198. #define PC_GUI_CTLSTAT 0x1748
  199. #define PC_DEBUG_MODE 0x1760
  200. #define BRES_DST_ERR_DEC 0x1780
  201. #define TRAIL_BRES_T12_ERR_DEC 0x1784
  202. #define TRAIL_BRES_T12_INC 0x1788
  203. #define DP_T12_CNTL 0x178c
  204. #define DST_BRES_T1_LNTH 0x1790
  205. #define DST_BRES_T2_LNTH 0x1794
  206. #define SCALE_SRC_HEIGHT_WIDTH 0x1994
  207. #define SCALE_OFFSET_0 0x1998
  208. #define SCALE_PITCH 0x199c
  209. #define SCALE_X_INC 0x19a0
  210. #define SCALE_Y_INC 0x19a4
  211. #define SCALE_HACC 0x19a8
  212. #define SCALE_VACC 0x19ac
  213. #define SCALE_DST_X_Y 0x19b0
  214. #define SCALE_DST_HEIGHT_WIDTH 0x19b4
  215. #define SCALE_3D_CNTL 0x1a00
  216. #define SCALE_3D_DATATYPE 0x1a20
  217. #define SETUP_CNTL 0x1bc4
  218. #define SOLID_COLOR 0x1bc8
  219. #define WINDOW_XY_OFFSET 0x1bcc
  220. #define DRAW_LINE_POINT 0x1bd0
  221. #define SETUP_CNTL_PM4 0x1bd4
  222. #define DST_PITCH_OFFSET_C 0x1c80
  223. #define DP_GUI_MASTER_CNTL_C 0x1c84
  224. #define SC_TOP_LEFT_C 0x1c88
  225. #define SC_BOTTOM_RIGHT_C 0x1c8c
  226. #define CLR_CMP_MASK_3D 0x1A28
  227. #define MISC_3D_STATE_CNTL_REG 0x1CA0
  228. #define MC_SRC1_CNTL 0x19D8
  229. #define TEX_CNTL 0x1800
  230. /* CONSTANTS */
  231. #define GUI_ACTIVE 0x80000000
  232. #define ENGINE_IDLE 0x0
  233. #define PLL_WR_EN 0x00000080
  234. #define CLK_PIN_CNTL 0x0001
  235. #define PPLL_CNTL 0x0002
  236. #define PPLL_REF_DIV 0x0003
  237. #define PPLL_DIV_0 0x0004
  238. #define PPLL_DIV_1 0x0005
  239. #define PPLL_DIV_2 0x0006
  240. #define PPLL_DIV_3 0x0007
  241. #define VCLK_ECP_CNTL 0x0008
  242. #define HTOTAL_CNTL 0x0009
  243. #define X_MPLL_REF_FB_DIV 0x000a
  244. #define XPLL_CNTL 0x000b
  245. #define XDLL_CNTL 0x000c
  246. #define XCLK_CNTL 0x000d
  247. #define MPLL_CNTL 0x000e
  248. #define MCLK_CNTL 0x000f
  249. #define AGP_PLL_CNTL 0x0010
  250. #define FCP_CNTL 0x0012
  251. #define PLL_TEST_CNTL 0x0013
  252. #define P2PLL_CNTL 0x002a
  253. #define P2PLL_REF_DIV 0x002b
  254. #define P2PLL_DIV_0 0x002b
  255. #define POWER_MANAGEMENT 0x002f
  256. #define PPLL_RESET 0x01
  257. #define PPLL_ATOMIC_UPDATE_EN 0x10000
  258. #define PPLL_VGA_ATOMIC_UPDATE_EN 0x20000
  259. #define PPLL_REF_DIV_MASK 0x3FF
  260. #define PPLL_FB3_DIV_MASK 0x7FF
  261. #define PPLL_POST3_DIV_MASK 0x70000
  262. #define PPLL_ATOMIC_UPDATE_R 0x8000
  263. #define PPLL_ATOMIC_UPDATE_W 0x8000
  264. #define MEM_CFG_TYPE_MASK 0x3
  265. #define XCLK_SRC_SEL_MASK 0x7
  266. #define XPLL_FB_DIV_MASK 0xFF00
  267. #define X_MPLL_REF_DIV_MASK 0xFF
  268. /* CRTC control values (CRTC_GEN_CNTL) */
  269. #define CRTC_CSYNC_EN 0x00000010
  270. #define CRTC2_DBL_SCAN_EN 0x00000001
  271. #define CRTC2_DISPLAY_DIS 0x00800000
  272. #define CRTC2_FIFO_EXTSENSE 0x00200000
  273. #define CRTC2_ICON_EN 0x00100000
  274. #define CRTC2_CUR_EN 0x00010000
  275. #define CRTC2_EN 0x02000000
  276. #define CRTC2_DISP_REQ_EN_B 0x04000000
  277. #define CRTC_PIX_WIDTH_MASK 0x00000700
  278. #define CRTC_PIX_WIDTH_4BPP 0x00000100
  279. #define CRTC_PIX_WIDTH_8BPP 0x00000200
  280. #define CRTC_PIX_WIDTH_15BPP 0x00000300
  281. #define CRTC_PIX_WIDTH_16BPP 0x00000400
  282. #define CRTC_PIX_WIDTH_24BPP 0x00000500
  283. #define CRTC_PIX_WIDTH_32BPP 0x00000600
  284. /* DAC_CNTL bit constants */
  285. #define DAC_8BIT_EN 0x00000100
  286. #define DAC_MASK 0xFF000000
  287. #define DAC_BLANKING 0x00000004
  288. #define DAC_RANGE_CNTL 0x00000003
  289. #define DAC_CLK_SEL 0x00000010
  290. #define DAC_PALETTE_ACCESS_CNTL 0x00000020
  291. #define DAC_PALETTE2_SNOOP_EN 0x00000040
  292. #define DAC_PDWN 0x00008000
  293. /* CRTC_EXT_CNTL */
  294. #define CRT_CRTC_ON 0x00008000
  295. /* GEN_RESET_CNTL bit constants */
  296. #define SOFT_RESET_GUI 0x00000001
  297. #define SOFT_RESET_VCLK 0x00000100
  298. #define SOFT_RESET_PCLK 0x00000200
  299. #define SOFT_RESET_ECP 0x00000400
  300. #define SOFT_RESET_DISPENG_XCLK 0x00000800
  301. /* PC_GUI_CTLSTAT bit constants */
  302. #define PC_BUSY_INIT 0x10000000
  303. #define PC_BUSY_GUI 0x20000000
  304. #define PC_BUSY_NGUI 0x40000000
  305. #define PC_BUSY 0x80000000
  306. #define BUS_MASTER_DIS 0x00000040
  307. #define PM4_BUFFER_CNTL_NONPM4 0x00000000
  308. /* DP_DATATYPE bit constants */
  309. #define DST_8BPP 0x00000002
  310. #define DST_15BPP 0x00000003
  311. #define DST_16BPP 0x00000004
  312. #define DST_24BPP 0x00000005
  313. #define DST_32BPP 0x00000006
  314. #define BRUSH_SOLIDCOLOR 0x00000d00
  315. /* DP_GUI_MASTER_CNTL bit constants */
  316. #define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000
  317. #define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000
  318. #define GMC_SRC_CLIP_DEFAULT 0x00000000
  319. #define GMC_DST_CLIP_DEFAULT 0x00000000
  320. #define GMC_BRUSH_SOLIDCOLOR 0x000000d0
  321. #define GMC_SRC_DSTCOLOR 0x00003000
  322. #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000
  323. #define GMC_DP_SRC_RECT 0x02000000
  324. #define GMC_3D_FCN_EN_CLR 0x00000000
  325. #define GMC_AUX_CLIP_CLEAR 0x20000000
  326. #define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000
  327. #define GMC_WRITE_MASK_SET 0x40000000
  328. #define GMC_DP_CONVERSION_TEMP_6500 0x00000000
  329. /* DP_GUI_MASTER_CNTL ROP3 named constants */
  330. #define ROP3_PATCOPY 0x00f00000
  331. #define ROP3_SRCCOPY 0x00cc0000
  332. #define SRC_DSTCOLOR 0x00030000
  333. /* DP_CNTL bit constants */
  334. #define DST_X_RIGHT_TO_LEFT 0x00000000
  335. #define DST_X_LEFT_TO_RIGHT 0x00000001
  336. #define DST_Y_BOTTOM_TO_TOP 0x00000000
  337. #define DST_Y_TOP_TO_BOTTOM 0x00000002
  338. #define DST_X_MAJOR 0x00000000
  339. #define DST_Y_MAJOR 0x00000004
  340. #define DST_X_TILE 0x00000008
  341. #define DST_Y_TILE 0x00000010
  342. #define DST_LAST_PEL 0x00000020
  343. #define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000
  344. #define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040
  345. #define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000
  346. #define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080
  347. #define DST_BRES_SIGN 0x00000100
  348. #define DST_HOST_BIG_ENDIAN_EN 0x00000200
  349. #define DST_POLYLINE_NONLAST 0x00008000
  350. #define DST_RASTER_STALL 0x00010000
  351. #define DST_POLY_EDGE 0x00040000
  352. /* DP_MIX bit constants */
  353. #define DP_SRC_RECT 0x00000200
  354. #define DP_SRC_HOST 0x00000300
  355. #define DP_SRC_HOST_BYTEALIGN 0x00000400
  356. /* LVDS_GEN_CNTL constants */
  357. #define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00
  358. #define LVDS_BL_MOD_LEVEL_SHIFT 8
  359. #define LVDS_BL_MOD_EN 0x00010000
  360. #define LVDS_DIGION 0x00040000
  361. #define LVDS_BLON 0x00080000
  362. #define LVDS_ON 0x00000001
  363. #define LVDS_DISPLAY_DIS 0x00000002
  364. #define LVDS_PANEL_TYPE_2PIX_PER_CLK 0x00000004
  365. #define LVDS_PANEL_24BITS_TFT 0x00000008
  366. #define LVDS_FRAME_MOD_NO 0x00000000
  367. #define LVDS_FRAME_MOD_2_LEVELS 0x00000010
  368. #define LVDS_FRAME_MOD_4_LEVELS 0x00000020
  369. #define LVDS_RST_FM 0x00000040
  370. #define LVDS_EN 0x00000080
  371. /* CRTC2_GEN_CNTL constants */
  372. #define CRTC2_EN 0x02000000
  373. /* POWER_MANAGEMENT constants */
  374. #define PWR_MGT_ON 0x00000001
  375. #define PWR_MGT_MODE_MASK 0x00000006
  376. #define PWR_MGT_MODE_PIN 0x00000000
  377. #define PWR_MGT_MODE_REGISTER 0x00000002
  378. #define PWR_MGT_MODE_TIMER 0x00000004
  379. #define PWR_MGT_MODE_PCI 0x00000006
  380. #define PWR_MGT_AUTO_PWR_UP_EN 0x00000008
  381. #define PWR_MGT_ACTIVITY_PIN_ON 0x00000010
  382. #define PWR_MGT_STANDBY_POL 0x00000020
  383. #define PWR_MGT_SUSPEND_POL 0x00000040
  384. #define PWR_MGT_SELF_REFRESH 0x00000080
  385. #define PWR_MGT_ACTIVITY_PIN_EN 0x00000100
  386. #define PWR_MGT_KEYBD_SNOOP 0x00000200
  387. #define PWR_MGT_TRISTATE_MEM_EN 0x00000800
  388. #define PWR_MGT_SELW4MS 0x00001000
  389. #define PWR_MGT_SLOWDOWN_MCLK 0x00002000
  390. #define PMI_PMSCR_REG 0x60
  391. /* used by ATI bug fix for hardware ROM */
  392. #define RAGE128_MPP_TB_CONFIG 0x01c0
  393. #endif /* REG_RAGE128_H */