opa_port_info.h 13 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
  2. /*
  3. * Copyright (c) 2014-2020 Intel Corporation. All rights reserved.
  4. */
  5. #ifndef OPA_PORT_INFO_H
  6. #define OPA_PORT_INFO_H
  7. #include <rdma/opa_smi.h>
  8. #define OPA_PORT_LINK_MODE_NOP 0 /* No change */
  9. #define OPA_PORT_LINK_MODE_OPA 4 /* Port mode is OPA */
  10. #define OPA_PORT_PACKET_FORMAT_NOP 0 /* No change */
  11. #define OPA_PORT_PACKET_FORMAT_8B 1 /* Format 8B */
  12. #define OPA_PORT_PACKET_FORMAT_9B 2 /* Format 9B */
  13. #define OPA_PORT_PACKET_FORMAT_10B 4 /* Format 10B */
  14. #define OPA_PORT_PACKET_FORMAT_16B 8 /* Format 16B */
  15. #define OPA_PORT_LTP_CRC_MODE_NONE 0 /* No change */
  16. #define OPA_PORT_LTP_CRC_MODE_14 1 /* 14-bit LTP CRC mode (optional) */
  17. #define OPA_PORT_LTP_CRC_MODE_16 2 /* 16-bit LTP CRC mode */
  18. #define OPA_PORT_LTP_CRC_MODE_48 4 /* 48-bit LTP CRC mode (optional) */
  19. #define OPA_PORT_LTP_CRC_MODE_PER_LANE 8 /* 12/16-bit per lane LTP CRC mode */
  20. /* Link Down / Neighbor Link Down Reason; indicated as follows: */
  21. #define OPA_LINKDOWN_REASON_NONE 0 /* No specified reason */
  22. #define OPA_LINKDOWN_REASON_RCV_ERROR_0 1
  23. #define OPA_LINKDOWN_REASON_BAD_PKT_LEN 2
  24. #define OPA_LINKDOWN_REASON_PKT_TOO_LONG 3
  25. #define OPA_LINKDOWN_REASON_PKT_TOO_SHORT 4
  26. #define OPA_LINKDOWN_REASON_BAD_SLID 5
  27. #define OPA_LINKDOWN_REASON_BAD_DLID 6
  28. #define OPA_LINKDOWN_REASON_BAD_L2 7
  29. #define OPA_LINKDOWN_REASON_BAD_SC 8
  30. #define OPA_LINKDOWN_REASON_RCV_ERROR_8 9
  31. #define OPA_LINKDOWN_REASON_BAD_MID_TAIL 10
  32. #define OPA_LINKDOWN_REASON_RCV_ERROR_10 11
  33. #define OPA_LINKDOWN_REASON_PREEMPT_ERROR 12
  34. #define OPA_LINKDOWN_REASON_PREEMPT_VL15 13
  35. #define OPA_LINKDOWN_REASON_BAD_VL_MARKER 14
  36. #define OPA_LINKDOWN_REASON_RCV_ERROR_14 15
  37. #define OPA_LINKDOWN_REASON_RCV_ERROR_15 16
  38. #define OPA_LINKDOWN_REASON_BAD_HEAD_DIST 17
  39. #define OPA_LINKDOWN_REASON_BAD_TAIL_DIST 18
  40. #define OPA_LINKDOWN_REASON_BAD_CTRL_DIST 19
  41. #define OPA_LINKDOWN_REASON_BAD_CREDIT_ACK 20
  42. #define OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER 21
  43. #define OPA_LINKDOWN_REASON_BAD_PREEMPT 22
  44. #define OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT 23
  45. #define OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT 24
  46. #define OPA_LINKDOWN_REASON_RCV_ERROR_24 25
  47. #define OPA_LINKDOWN_REASON_RCV_ERROR_25 26
  48. #define OPA_LINKDOWN_REASON_RCV_ERROR_26 27
  49. #define OPA_LINKDOWN_REASON_RCV_ERROR_27 28
  50. #define OPA_LINKDOWN_REASON_RCV_ERROR_28 29
  51. #define OPA_LINKDOWN_REASON_RCV_ERROR_29 30
  52. #define OPA_LINKDOWN_REASON_RCV_ERROR_30 31
  53. #define OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN 32
  54. #define OPA_LINKDOWN_REASON_UNKNOWN 33
  55. /* 34 -reserved */
  56. #define OPA_LINKDOWN_REASON_REBOOT 35
  57. #define OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN 36
  58. /* 37-38 reserved */
  59. #define OPA_LINKDOWN_REASON_FM_BOUNCE 39
  60. #define OPA_LINKDOWN_REASON_SPEED_POLICY 40
  61. #define OPA_LINKDOWN_REASON_WIDTH_POLICY 41
  62. /* 42-48 reserved */
  63. #define OPA_LINKDOWN_REASON_DISCONNECTED 49
  64. #define OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED 50
  65. #define OPA_LINKDOWN_REASON_NOT_INSTALLED 51
  66. #define OPA_LINKDOWN_REASON_CHASSIS_CONFIG 52
  67. /* 53 reserved */
  68. #define OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED 54
  69. /* 55 reserved */
  70. #define OPA_LINKDOWN_REASON_POWER_POLICY 56
  71. #define OPA_LINKDOWN_REASON_LINKSPEED_POLICY 57
  72. #define OPA_LINKDOWN_REASON_LINKWIDTH_POLICY 58
  73. /* 59 reserved */
  74. #define OPA_LINKDOWN_REASON_SWITCH_MGMT 60
  75. #define OPA_LINKDOWN_REASON_SMA_DISABLED 61
  76. /* 62 reserved */
  77. #define OPA_LINKDOWN_REASON_TRANSIENT 63
  78. /* 64-255 reserved */
  79. /* OPA Link Init reason; indicated as follows: */
  80. /* 3-7; 11-15 reserved; 8-15 cleared on Polling->LinkUp */
  81. #define OPA_LINKINIT_REASON_NOP 0
  82. #define OPA_LINKINIT_REASON_LINKUP (1 << 4)
  83. #define OPA_LINKINIT_REASON_FLAPPING (2 << 4)
  84. #define OPA_LINKINIT_REASON_CLEAR (8 << 4)
  85. #define OPA_LINKINIT_OUTSIDE_POLICY (8 << 4)
  86. #define OPA_LINKINIT_QUARANTINED (9 << 4)
  87. #define OPA_LINKINIT_INSUFIC_CAPABILITY (10 << 4)
  88. #define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */
  89. #define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */
  90. #define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */
  91. #define OPA_LINK_WIDTH_1X 0x0001
  92. #define OPA_LINK_WIDTH_2X 0x0002
  93. #define OPA_LINK_WIDTH_3X 0x0004
  94. #define OPA_LINK_WIDTH_4X 0x0008
  95. #define OPA_CAP_MASK3_IsEthOnFabricSupported (1 << 13)
  96. #define OPA_CAP_MASK3_IsSnoopSupported (1 << 7)
  97. #define OPA_CAP_MASK3_IsAsyncSC2VLSupported (1 << 6)
  98. #define OPA_CAP_MASK3_IsAddrRangeConfigSupported (1 << 5)
  99. #define OPA_CAP_MASK3_IsPassThroughSupported (1 << 4)
  100. #define OPA_CAP_MASK3_IsSharedSpaceSupported (1 << 3)
  101. /* reserved (1 << 2) */
  102. #define OPA_CAP_MASK3_IsVLMarkerSupported (1 << 1)
  103. #define OPA_CAP_MASK3_IsVLrSupported (1 << 0)
  104. enum {
  105. OPA_PORT_PHYS_CONF_DISCONNECTED = 0,
  106. OPA_PORT_PHYS_CONF_STANDARD = 1,
  107. OPA_PORT_PHYS_CONF_FIXED = 2,
  108. OPA_PORT_PHYS_CONF_VARIABLE = 3,
  109. OPA_PORT_PHYS_CONF_SI_PHOTO = 4
  110. };
  111. enum port_info_field_masks {
  112. /* vl.cap */
  113. OPA_PI_MASK_VL_CAP = 0x1F,
  114. /* port_states.ledenable_offlinereason */
  115. OPA_PI_MASK_OFFLINE_REASON = 0x0F,
  116. OPA_PI_MASK_LED_ENABLE = 0x40,
  117. /* port_states.unsleepstate_downdefstate */
  118. OPA_PI_MASK_UNSLEEP_STATE = 0xF0,
  119. OPA_PI_MASK_DOWNDEF_STATE = 0x0F,
  120. /* port_states.portphysstate_portstate */
  121. OPA_PI_MASK_PORT_PHYSICAL_STATE = 0xF0,
  122. OPA_PI_MASK_PORT_STATE = 0x0F,
  123. /* port_phys_conf */
  124. OPA_PI_MASK_PORT_PHYSICAL_CONF = 0x0F,
  125. /* collectivemask_multicastmask */
  126. OPA_PI_MASK_COLLECT_MASK = 0x38,
  127. OPA_PI_MASK_MULTICAST_MASK = 0x07,
  128. /* mkeyprotect_lmc */
  129. OPA_PI_MASK_MKEY_PROT_BIT = 0xC0,
  130. OPA_PI_MASK_LMC = 0x0F,
  131. /* smsl */
  132. OPA_PI_MASK_SMSL = 0x1F,
  133. /* partenforce_filterraw */
  134. /* Filter Raw In/Out bits 1 and 2 were removed */
  135. OPA_PI_MASK_LINKINIT_REASON = 0xF0,
  136. OPA_PI_MASK_PARTITION_ENFORCE_IN = 0x08,
  137. OPA_PI_MASK_PARTITION_ENFORCE_OUT = 0x04,
  138. /* operational_vls */
  139. OPA_PI_MASK_OPERATIONAL_VL = 0x1F,
  140. /* sa_qp */
  141. OPA_PI_MASK_SA_QP = 0x00FFFFFF,
  142. /* sm_trap_qp */
  143. OPA_PI_MASK_SM_TRAP_QP = 0x00FFFFFF,
  144. /* localphy_overrun_errors */
  145. OPA_PI_MASK_LOCAL_PHY_ERRORS = 0xF0,
  146. OPA_PI_MASK_OVERRUN_ERRORS = 0x0F,
  147. /* clientrereg_subnettimeout */
  148. OPA_PI_MASK_CLIENT_REREGISTER = 0x80,
  149. OPA_PI_MASK_SUBNET_TIMEOUT = 0x1F,
  150. /* port_link_mode */
  151. OPA_PI_MASK_PORT_LINK_SUPPORTED = (0x001F << 10),
  152. OPA_PI_MASK_PORT_LINK_ENABLED = (0x001F << 5),
  153. OPA_PI_MASK_PORT_LINK_ACTIVE = (0x001F << 0),
  154. /* port_link_crc_mode */
  155. OPA_PI_MASK_PORT_LINK_CRC_SUPPORTED = 0x0F00,
  156. OPA_PI_MASK_PORT_LINK_CRC_ENABLED = 0x00F0,
  157. OPA_PI_MASK_PORT_LINK_CRC_ACTIVE = 0x000F,
  158. /* port_mode */
  159. OPA_PI_MASK_PORT_MODE_SECURITY_CHECK = 0x0001,
  160. OPA_PI_MASK_PORT_MODE_16B_TRAP_QUERY = 0x0002,
  161. OPA_PI_MASK_PORT_MODE_PKEY_CONVERT = 0x0004,
  162. OPA_PI_MASK_PORT_MODE_SC2SC_MAPPING = 0x0008,
  163. OPA_PI_MASK_PORT_MODE_VL_MARKER = 0x0010,
  164. OPA_PI_MASK_PORT_PASS_THROUGH = 0x0020,
  165. OPA_PI_MASK_PORT_ACTIVE_OPTOMIZE = 0x0040,
  166. /* flit_control.interleave */
  167. OPA_PI_MASK_INTERLEAVE_DIST_SUP = (0x0003 << 12),
  168. OPA_PI_MASK_INTERLEAVE_DIST_ENABLE = (0x0003 << 10),
  169. OPA_PI_MASK_INTERLEAVE_MAX_NEST_TX = (0x001F << 5),
  170. OPA_PI_MASK_INTERLEAVE_MAX_NEST_RX = (0x001F << 0),
  171. /* port_error_action */
  172. OPA_PI_MASK_EX_BUFFER_OVERRUN = 0x80000000,
  173. /* 7 bits reserved */
  174. OPA_PI_MASK_FM_CFG_ERR_EXCEED_MULTICAST_LIMIT = 0x00800000,
  175. OPA_PI_MASK_FM_CFG_BAD_CONTROL_FLIT = 0x00400000,
  176. OPA_PI_MASK_FM_CFG_BAD_PREEMPT = 0x00200000,
  177. OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER = 0x00100000,
  178. OPA_PI_MASK_FM_CFG_BAD_CRDT_ACK = 0x00080000,
  179. OPA_PI_MASK_FM_CFG_BAD_CTRL_DIST = 0x00040000,
  180. OPA_PI_MASK_FM_CFG_BAD_TAIL_DIST = 0x00020000,
  181. OPA_PI_MASK_FM_CFG_BAD_HEAD_DIST = 0x00010000,
  182. /* 2 bits reserved */
  183. OPA_PI_MASK_PORT_RCV_BAD_VL_MARKER = 0x00002000,
  184. OPA_PI_MASK_PORT_RCV_PREEMPT_VL15 = 0x00001000,
  185. OPA_PI_MASK_PORT_RCV_PREEMPT_ERROR = 0x00000800,
  186. /* 1 bit reserved */
  187. OPA_PI_MASK_PORT_RCV_BAD_MidTail = 0x00000200,
  188. /* 1 bit reserved */
  189. OPA_PI_MASK_PORT_RCV_BAD_SC = 0x00000080,
  190. OPA_PI_MASK_PORT_RCV_BAD_L2 = 0x00000040,
  191. OPA_PI_MASK_PORT_RCV_BAD_DLID = 0x00000020,
  192. OPA_PI_MASK_PORT_RCV_BAD_SLID = 0x00000010,
  193. OPA_PI_MASK_PORT_RCV_PKTLEN_TOOSHORT = 0x00000008,
  194. OPA_PI_MASK_PORT_RCV_PKTLEN_TOOLONG = 0x00000004,
  195. OPA_PI_MASK_PORT_RCV_BAD_PKTLEN = 0x00000002,
  196. OPA_PI_MASK_PORT_RCV_BAD_LT = 0x00000001,
  197. /* pass_through.res_drctl */
  198. OPA_PI_MASK_PASS_THROUGH_DR_CONTROL = 0x01,
  199. /* buffer_units */
  200. OPA_PI_MASK_BUF_UNIT_VL15_INIT = (0x00000FFF << 11),
  201. OPA_PI_MASK_BUF_UNIT_VL15_CREDIT_RATE = (0x0000001F << 6),
  202. OPA_PI_MASK_BUF_UNIT_CREDIT_ACK = (0x00000003 << 3),
  203. OPA_PI_MASK_BUF_UNIT_BUF_ALLOC = (0x00000003 << 0),
  204. /* neigh_mtu.pvlx_to_mtu */
  205. OPA_PI_MASK_NEIGH_MTU_PVL0 = 0xF0,
  206. OPA_PI_MASK_NEIGH_MTU_PVL1 = 0x0F,
  207. /* neigh_mtu.vlstall_hoq_life */
  208. OPA_PI_MASK_VL_STALL = (0x03 << 5),
  209. OPA_PI_MASK_HOQ_LIFE = (0x1F << 0),
  210. /* port_neigh_mode */
  211. OPA_PI_MASK_NEIGH_MGMT_ALLOWED = (0x01 << 3),
  212. OPA_PI_MASK_NEIGH_FW_AUTH_BYPASS = (0x01 << 2),
  213. OPA_PI_MASK_NEIGH_NODE_TYPE = (0x03 << 0),
  214. /* resptime_value */
  215. OPA_PI_MASK_RESPONSE_TIME_VALUE = 0x1F,
  216. /* mtucap */
  217. OPA_PI_MASK_MTU_CAP = 0x0F,
  218. };
  219. struct opa_port_states {
  220. u8 reserved;
  221. u8 ledenable_offlinereason; /* 1 res, 1 bit, 6 bits */
  222. u8 reserved2;
  223. u8 portphysstate_portstate; /* 4 bits, 4 bits */
  224. };
  225. struct opa_port_state_info {
  226. struct opa_port_states port_states;
  227. __be16 link_width_downgrade_tx_active;
  228. __be16 link_width_downgrade_rx_active;
  229. };
  230. struct opa_port_info {
  231. __be32 lid;
  232. __be32 flow_control_mask;
  233. struct {
  234. u8 res; /* was inittype */
  235. u8 cap; /* 3 res, 5 bits */
  236. __be16 high_limit;
  237. __be16 preempt_limit;
  238. u8 arb_high_cap;
  239. u8 arb_low_cap;
  240. } vl;
  241. struct opa_port_states port_states;
  242. u8 port_phys_conf; /* 4 res, 4 bits */
  243. u8 collectivemask_multicastmask; /* 2 res, 3, 3 */
  244. u8 mkeyprotect_lmc; /* 2 bits, 2 res, 4 bits */
  245. u8 smsl; /* 3 res, 5 bits */
  246. u8 partenforce_filterraw; /* bit fields */
  247. u8 operational_vls; /* 3 res, 5 bits */
  248. __be16 pkey_8b;
  249. __be16 pkey_10b;
  250. __be16 mkey_violations;
  251. __be16 pkey_violations;
  252. __be16 qkey_violations;
  253. __be32 sm_trap_qp; /* 8 bits, 24 bits */
  254. __be32 sa_qp; /* 8 bits, 24 bits */
  255. u8 neigh_port_num;
  256. u8 link_down_reason;
  257. u8 neigh_link_down_reason;
  258. u8 clientrereg_subnettimeout; /* 1 bit, 2 bits, 5 */
  259. struct {
  260. __be16 supported;
  261. __be16 enabled;
  262. __be16 active;
  263. } link_speed;
  264. struct {
  265. __be16 supported;
  266. __be16 enabled;
  267. __be16 active;
  268. } link_width;
  269. struct {
  270. __be16 supported;
  271. __be16 enabled;
  272. __be16 tx_active;
  273. __be16 rx_active;
  274. } link_width_downgrade;
  275. __be16 port_link_mode; /* 1 res, 5 bits, 5 bits, 5 bits */
  276. __be16 port_ltp_crc_mode; /* 4 res, 4 bits, 4 bits, 4 bits */
  277. __be16 port_mode; /* 9 res, bit fields */
  278. struct {
  279. __be16 supported;
  280. __be16 enabled;
  281. } port_packet_format;
  282. struct {
  283. __be16 interleave; /* 2 res, 2,2,5,5 */
  284. struct {
  285. __be16 min_initial;
  286. __be16 min_tail;
  287. u8 large_pkt_limit;
  288. u8 small_pkt_limit;
  289. u8 max_small_pkt_limit;
  290. u8 preemption_limit;
  291. } preemption;
  292. } flit_control;
  293. __be32 reserved4;
  294. __be32 port_error_action; /* bit field */
  295. struct {
  296. u8 egress_port;
  297. u8 res_drctl; /* 7 res, 1 */
  298. } pass_through;
  299. __be16 mkey_lease_period;
  300. __be32 buffer_units; /* 9 res, 12, 5, 3, 3 */
  301. __be32 reserved5;
  302. __be32 sm_lid;
  303. __be64 mkey;
  304. __be64 subnet_prefix;
  305. struct {
  306. u8 pvlx_to_mtu[OPA_MAX_VLS/2]; /* 4 bits, 4 bits */
  307. } neigh_mtu;
  308. struct {
  309. u8 vlstall_hoqlife; /* 3 bits, 5 bits */
  310. } xmit_q[OPA_MAX_VLS];
  311. struct {
  312. u8 addr[16];
  313. } ipaddr_ipv6;
  314. struct {
  315. u8 addr[4];
  316. } ipaddr_ipv4;
  317. u32 reserved6;
  318. u32 reserved7;
  319. u32 reserved8;
  320. __be64 neigh_node_guid;
  321. __be32 ib_cap_mask;
  322. __be16 reserved9; /* was ib_cap_mask2 */
  323. __be16 opa_cap_mask;
  324. __be32 reserved10; /* was link_roundtrip_latency */
  325. __be16 overall_buffer_space;
  326. __be16 reserved11; /* was max_credit_hint */
  327. __be16 diag_code;
  328. struct {
  329. u8 buffer;
  330. u8 wire;
  331. } replay_depth;
  332. u8 port_neigh_mode;
  333. u8 mtucap; /* 4 res, 4 bits */
  334. u8 resptimevalue; /* 3 res, 5 bits */
  335. u8 local_port_num;
  336. u8 reserved12;
  337. u8 reserved13; /* was guid_cap */
  338. } __packed;
  339. #endif /* OPA_PORT_INFO_H */