ocxl.h 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. // Copyright 2017 IBM Corp.
  3. #ifndef _MISC_OCXL_H_
  4. #define _MISC_OCXL_H_
  5. #include <linux/pci.h>
  6. /*
  7. * Opencapi drivers all need some common facilities, like parsing the
  8. * device configuration space, adding a Process Element to the Shared
  9. * Process Area, etc...
  10. *
  11. * The ocxl module provides a kernel API, to allow other drivers to
  12. * reuse common code. A bit like a in-kernel library.
  13. */
  14. #define OCXL_AFU_NAME_SZ (24+1) /* add 1 for NULL termination */
  15. struct ocxl_afu_config {
  16. u8 idx;
  17. int dvsec_afu_control_pos; /* offset of AFU control DVSEC */
  18. char name[OCXL_AFU_NAME_SZ];
  19. u8 version_major;
  20. u8 version_minor;
  21. u8 afuc_type;
  22. u8 afum_type;
  23. u8 profile;
  24. u8 global_mmio_bar; /* global MMIO area */
  25. u64 global_mmio_offset;
  26. u32 global_mmio_size;
  27. u8 pp_mmio_bar; /* per-process MMIO area */
  28. u64 pp_mmio_offset;
  29. u32 pp_mmio_stride;
  30. u64 lpc_mem_offset;
  31. u64 lpc_mem_size;
  32. u64 special_purpose_mem_offset;
  33. u64 special_purpose_mem_size;
  34. u8 pasid_supported_log;
  35. u16 actag_supported;
  36. };
  37. struct ocxl_fn_config {
  38. int dvsec_tl_pos; /* offset of the Transaction Layer DVSEC */
  39. int dvsec_function_pos; /* offset of the Function DVSEC */
  40. int dvsec_afu_info_pos; /* offset of the AFU information DVSEC */
  41. s8 max_pasid_log;
  42. s8 max_afu_index;
  43. };
  44. enum ocxl_endian {
  45. OCXL_BIG_ENDIAN = 0, /**< AFU data is big-endian */
  46. OCXL_LITTLE_ENDIAN = 1, /**< AFU data is little-endian */
  47. OCXL_HOST_ENDIAN = 2, /**< AFU data is the same endianness as the host */
  48. };
  49. // These are opaque outside the ocxl driver
  50. struct ocxl_afu;
  51. struct ocxl_fn;
  52. struct ocxl_context;
  53. // Device detection & initialisation
  54. /**
  55. * ocxl_function_open() - Open an OpenCAPI function on an OpenCAPI device
  56. * @dev: The PCI device that contains the function
  57. *
  58. * Returns an opaque pointer to the function, or an error pointer (check with IS_ERR)
  59. */
  60. struct ocxl_fn *ocxl_function_open(struct pci_dev *dev);
  61. /**
  62. * ocxl_function_afu_list() - Get the list of AFUs associated with a PCI function device
  63. * Returns a list of struct ocxl_afu *
  64. *
  65. * @fn: The OpenCAPI function containing the AFUs
  66. */
  67. struct list_head *ocxl_function_afu_list(struct ocxl_fn *fn);
  68. /**
  69. * ocxl_function_fetch_afu() - Fetch an AFU instance from an OpenCAPI function
  70. * @fn: The OpenCAPI function to get the AFU from
  71. * @afu_idx: The index of the AFU to get
  72. *
  73. * If successful, the AFU should be released with ocxl_afu_put()
  74. *
  75. * Returns a pointer to the AFU, or NULL on error
  76. */
  77. struct ocxl_afu *ocxl_function_fetch_afu(struct ocxl_fn *fn, u8 afu_idx);
  78. /**
  79. * ocxl_afu_get() - Take a reference to an AFU
  80. * @afu: The AFU to increment the reference count on
  81. */
  82. void ocxl_afu_get(struct ocxl_afu *afu);
  83. /**
  84. * ocxl_afu_put() - Release a reference to an AFU
  85. * @afu: The AFU to decrement the reference count on
  86. */
  87. void ocxl_afu_put(struct ocxl_afu *afu);
  88. /**
  89. * ocxl_function_config() - Get the configuration information for an OpenCAPI function
  90. * @fn: The OpenCAPI function to get the config for
  91. *
  92. * Returns the function config, or NULL on error
  93. */
  94. const struct ocxl_fn_config *ocxl_function_config(struct ocxl_fn *fn);
  95. /**
  96. * ocxl_function_close() - Close an OpenCAPI function
  97. * This will free any AFUs previously retrieved from the function, and
  98. * detach and associated contexts. The contexts must by freed by the caller.
  99. *
  100. * @fn: The OpenCAPI function to close
  101. *
  102. */
  103. void ocxl_function_close(struct ocxl_fn *fn);
  104. // Context allocation
  105. /**
  106. * ocxl_context_alloc() - Allocate an OpenCAPI context
  107. * @context: The OpenCAPI context to allocate, must be freed with ocxl_context_free
  108. * @afu: The AFU the context belongs to
  109. * @mapping: The mapping to unmap when the context is closed (may be NULL)
  110. */
  111. int ocxl_context_alloc(struct ocxl_context **context, struct ocxl_afu *afu,
  112. struct address_space *mapping);
  113. /**
  114. * ocxl_context_free() - Free an OpenCAPI context
  115. * @ctx: The OpenCAPI context to free
  116. */
  117. void ocxl_context_free(struct ocxl_context *ctx);
  118. /**
  119. * ocxl_context_attach() - Grant access to an MM to an OpenCAPI context
  120. * @ctx: The OpenCAPI context to attach
  121. * @amr: The value of the AMR register to restrict access
  122. * @mm: The mm to attach to the context
  123. *
  124. * Returns 0 on success, negative on failure
  125. */
  126. int ocxl_context_attach(struct ocxl_context *ctx, u64 amr,
  127. struct mm_struct *mm);
  128. /**
  129. * ocxl_context_detach() - Detach an MM from an OpenCAPI context
  130. * @ctx: The OpenCAPI context to attach
  131. *
  132. * Returns 0 on success, negative on failure
  133. */
  134. int ocxl_context_detach(struct ocxl_context *ctx);
  135. // AFU IRQs
  136. /**
  137. * ocxl_afu_irq_alloc() - Allocate an IRQ associated with an AFU context
  138. * @ctx: the AFU context
  139. * @irq_id: out, the IRQ ID
  140. *
  141. * Returns 0 on success, negative on failure
  142. */
  143. int ocxl_afu_irq_alloc(struct ocxl_context *ctx, int *irq_id);
  144. /**
  145. * ocxl_afu_irq_free() - Frees an IRQ associated with an AFU context
  146. * @ctx: the AFU context
  147. * @irq_id: the IRQ ID
  148. *
  149. * Returns 0 on success, negative on failure
  150. */
  151. int ocxl_afu_irq_free(struct ocxl_context *ctx, int irq_id);
  152. /**
  153. * ocxl_afu_irq_get_addr() - Gets the address of the trigger page for an IRQ
  154. * This can then be provided to an AFU which will write to that
  155. * page to trigger the IRQ.
  156. * @ctx: The AFU context that the IRQ is associated with
  157. * @irq_id: The IRQ ID
  158. *
  159. * returns the trigger page address, or 0 if the IRQ is not valid
  160. */
  161. u64 ocxl_afu_irq_get_addr(struct ocxl_context *ctx, int irq_id);
  162. /**
  163. * ocxl_irq_set_handler() - Provide a callback to be called when an IRQ is triggered
  164. * @ctx: The AFU context that the IRQ is associated with
  165. * @irq_id: The IRQ ID
  166. * @handler: the callback to be called when the IRQ is triggered
  167. * @free_private: the callback to be called when the IRQ is freed (may be NULL)
  168. * @private: Private data to be passed to the callbacks
  169. *
  170. * Returns 0 on success, negative on failure
  171. */
  172. int ocxl_irq_set_handler(struct ocxl_context *ctx, int irq_id,
  173. irqreturn_t (*handler)(void *private),
  174. void (*free_private)(void *private),
  175. void *private);
  176. // AFU Metadata
  177. /**
  178. * ocxl_afu_config() - Get a pointer to the config for an AFU
  179. * @afu: a pointer to the AFU to get the config for
  180. *
  181. * Returns a pointer to the AFU config
  182. */
  183. struct ocxl_afu_config *ocxl_afu_config(struct ocxl_afu *afu);
  184. /**
  185. * ocxl_afu_set_private() - Assign opaque hardware specific information to an OpenCAPI AFU.
  186. * @afu: The OpenCAPI AFU
  187. * @private: the opaque hardware specific information to assign to the driver
  188. */
  189. void ocxl_afu_set_private(struct ocxl_afu *afu, void *private);
  190. /**
  191. * ocxl_afu_get_private() - Fetch the hardware specific information associated with
  192. * an external OpenCAPI AFU. This may be consumed by an external OpenCAPI driver.
  193. * @afu: The OpenCAPI AFU
  194. *
  195. * Returns the opaque pointer associated with the device, or NULL if not set
  196. */
  197. void *ocxl_afu_get_private(struct ocxl_afu *afu);
  198. // Global MMIO
  199. /**
  200. * ocxl_global_mmio_read32() - Read a 32 bit value from global MMIO
  201. * @afu: The AFU
  202. * @offset: The Offset from the start of MMIO
  203. * @endian: the endianness that the MMIO data is in
  204. * @val: returns the value
  205. *
  206. * Returns 0 for success, negative on error
  207. */
  208. int ocxl_global_mmio_read32(struct ocxl_afu *afu, size_t offset,
  209. enum ocxl_endian endian, u32 *val);
  210. /**
  211. * ocxl_global_mmio_read64() - Read a 64 bit value from global MMIO
  212. * @afu: The AFU
  213. * @offset: The Offset from the start of MMIO
  214. * @endian: the endianness that the MMIO data is in
  215. * @val: returns the value
  216. *
  217. * Returns 0 for success, negative on error
  218. */
  219. int ocxl_global_mmio_read64(struct ocxl_afu *afu, size_t offset,
  220. enum ocxl_endian endian, u64 *val);
  221. /**
  222. * ocxl_global_mmio_write32() - Write a 32 bit value to global MMIO
  223. * @afu: The AFU
  224. * @offset: The Offset from the start of MMIO
  225. * @endian: the endianness that the MMIO data is in
  226. * @val: The value to write
  227. *
  228. * Returns 0 for success, negative on error
  229. */
  230. int ocxl_global_mmio_write32(struct ocxl_afu *afu, size_t offset,
  231. enum ocxl_endian endian, u32 val);
  232. /**
  233. * ocxl_global_mmio_write64() - Write a 64 bit value to global MMIO
  234. * @afu: The AFU
  235. * @offset: The Offset from the start of MMIO
  236. * @endian: the endianness that the MMIO data is in
  237. * @val: The value to write
  238. *
  239. * Returns 0 for success, negative on error
  240. */
  241. int ocxl_global_mmio_write64(struct ocxl_afu *afu, size_t offset,
  242. enum ocxl_endian endian, u64 val);
  243. /**
  244. * ocxl_global_mmio_set32() - Set bits in a 32 bit global MMIO register
  245. * @afu: The AFU
  246. * @offset: The Offset from the start of MMIO
  247. * @endian: the endianness that the MMIO data is in
  248. * @mask: a mask of the bits to set
  249. *
  250. * Returns 0 for success, negative on error
  251. */
  252. int ocxl_global_mmio_set32(struct ocxl_afu *afu, size_t offset,
  253. enum ocxl_endian endian, u32 mask);
  254. /**
  255. * ocxl_global_mmio_set64() - Set bits in a 64 bit global MMIO register
  256. * @afu: The AFU
  257. * @offset: The Offset from the start of MMIO
  258. * @endian: the endianness that the MMIO data is in
  259. * @mask: a mask of the bits to set
  260. *
  261. * Returns 0 for success, negative on error
  262. */
  263. int ocxl_global_mmio_set64(struct ocxl_afu *afu, size_t offset,
  264. enum ocxl_endian endian, u64 mask);
  265. /**
  266. * ocxl_global_mmio_clear32() - Set bits in a 32 bit global MMIO register
  267. * @afu: The AFU
  268. * @offset: The Offset from the start of MMIO
  269. * @endian: the endianness that the MMIO data is in
  270. * @mask: a mask of the bits to set
  271. *
  272. * Returns 0 for success, negative on error
  273. */
  274. int ocxl_global_mmio_clear32(struct ocxl_afu *afu, size_t offset,
  275. enum ocxl_endian endian, u32 mask);
  276. /**
  277. * ocxl_global_mmio_clear64() - Set bits in a 64 bit global MMIO register
  278. * @afu: The AFU
  279. * @offset: The Offset from the start of MMIO
  280. * @endian: the endianness that the MMIO data is in
  281. * @mask: a mask of the bits to set
  282. *
  283. * Returns 0 for success, negative on error
  284. */
  285. int ocxl_global_mmio_clear64(struct ocxl_afu *afu, size_t offset,
  286. enum ocxl_endian endian, u64 mask);
  287. // Functions left here are for compatibility with the cxlflash driver
  288. /*
  289. * Read the configuration space of a function for the AFU specified by
  290. * the index 'afu_idx'. Fills in a ocxl_afu_config structure
  291. */
  292. int ocxl_config_read_afu(struct pci_dev *dev,
  293. struct ocxl_fn_config *fn,
  294. struct ocxl_afu_config *afu,
  295. u8 afu_idx);
  296. /*
  297. * Tell an AFU, by writing in the configuration space, the PASIDs that
  298. * it can use. Range starts at 'pasid_base' and its size is a multiple
  299. * of 2
  300. *
  301. * 'afu_control_offset' is the offset of the AFU control DVSEC which
  302. * can be found in the function configuration
  303. */
  304. void ocxl_config_set_afu_pasid(struct pci_dev *dev,
  305. int afu_control_offset,
  306. int pasid_base, u32 pasid_count_log);
  307. /*
  308. * Get the actag configuration for the function:
  309. * 'base' is the first actag value that can be used.
  310. * 'enabled' it the number of actags available, starting from base.
  311. * 'supported' is the total number of actags desired by all the AFUs
  312. * of the function.
  313. */
  314. int ocxl_config_get_actag_info(struct pci_dev *dev,
  315. u16 *base, u16 *enabled, u16 *supported);
  316. /*
  317. * Tell a function, by writing in the configuration space, the actags
  318. * it can use.
  319. *
  320. * 'func_offset' is the offset of the Function DVSEC that can found in
  321. * the function configuration
  322. */
  323. void ocxl_config_set_actag(struct pci_dev *dev, int func_offset,
  324. u32 actag_base, u32 actag_count);
  325. /*
  326. * Tell an AFU, by writing in the configuration space, the actags it
  327. * can use.
  328. *
  329. * 'afu_control_offset' is the offset of the AFU control DVSEC for the
  330. * desired AFU. It can be found in the AFU configuration
  331. */
  332. void ocxl_config_set_afu_actag(struct pci_dev *dev,
  333. int afu_control_offset,
  334. int actag_base, int actag_count);
  335. /*
  336. * Enable/disable an AFU, by writing in the configuration space.
  337. *
  338. * 'afu_control_offset' is the offset of the AFU control DVSEC for the
  339. * desired AFU. It can be found in the AFU configuration
  340. */
  341. void ocxl_config_set_afu_state(struct pci_dev *dev,
  342. int afu_control_offset, int enable);
  343. /*
  344. * Set the Transaction Layer configuration in the configuration space.
  345. * Only needed for function 0.
  346. *
  347. * It queries the host TL capabilities, find some common ground
  348. * between the host and device, and set the Transaction Layer on both
  349. * accordingly.
  350. */
  351. int ocxl_config_set_TL(struct pci_dev *dev, int tl_dvsec);
  352. /*
  353. * Request an AFU to terminate a PASID.
  354. * Will return once the AFU has acked the request, or an error in case
  355. * of timeout.
  356. *
  357. * The hardware can only terminate one PASID at a time, so caller must
  358. * guarantee some kind of serialization.
  359. *
  360. * 'afu_control_offset' is the offset of the AFU control DVSEC for the
  361. * desired AFU. It can be found in the AFU configuration
  362. */
  363. int ocxl_config_terminate_pasid(struct pci_dev *dev,
  364. int afu_control_offset, int pasid);
  365. /*
  366. * Read the configuration space of a function and fill in a
  367. * ocxl_fn_config structure with all the function details
  368. */
  369. int ocxl_config_read_function(struct pci_dev *dev,
  370. struct ocxl_fn_config *fn);
  371. /*
  372. * Set up the opencapi link for the function.
  373. *
  374. * When called for the first time for a link, it sets up the Shared
  375. * Process Area for the link and the interrupt handler to process
  376. * translation faults.
  377. *
  378. * Returns a 'link handle' that should be used for further calls for
  379. * the link
  380. */
  381. int ocxl_link_setup(struct pci_dev *dev, int PE_mask,
  382. void **link_handle);
  383. /*
  384. * Remove the association between the function and its link.
  385. */
  386. void ocxl_link_release(struct pci_dev *dev, void *link_handle);
  387. /*
  388. * Add a Process Element to the Shared Process Area for a link.
  389. * The process is defined by its PASID, pid, tid and its mm_struct.
  390. *
  391. * 'xsl_err_cb' is an optional callback if the driver wants to be
  392. * notified when the translation fault interrupt handler detects an
  393. * address error.
  394. * 'xsl_err_data' is an argument passed to the above callback, if
  395. * defined
  396. */
  397. int ocxl_link_add_pe(void *link_handle, int pasid, u32 pidr, u32 tidr,
  398. u64 amr, struct mm_struct *mm,
  399. void (*xsl_err_cb)(void *data, u64 addr, u64 dsisr),
  400. void *xsl_err_data);
  401. /*
  402. * Remove a Process Element from the Shared Process Area for a link
  403. */
  404. int ocxl_link_remove_pe(void *link_handle, int pasid);
  405. /*
  406. * Allocate an AFU interrupt associated to the link.
  407. *
  408. * 'hw_irq' is the hardware interrupt number
  409. */
  410. int ocxl_link_irq_alloc(void *link_handle, int *hw_irq);
  411. /*
  412. * Free a previously allocated AFU interrupt
  413. */
  414. void ocxl_link_free_irq(void *link_handle, int hw_irq);
  415. #endif /* _MISC_OCXL_H_ */