cxllib.h 3.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Copyright 2017 IBM Corp.
  4. */
  5. #ifndef _MISC_CXLLIB_H
  6. #define _MISC_CXLLIB_H
  7. #include <linux/pci.h>
  8. #include <asm/reg.h>
  9. /*
  10. * cxl driver exports a in-kernel 'library' API which can be called by
  11. * other drivers to help interacting with an IBM XSL.
  12. */
  13. /*
  14. * tells whether capi is supported on the PCIe slot where the
  15. * device is seated
  16. *
  17. * Input:
  18. * dev: device whose slot needs to be checked
  19. * flags: 0 for the time being
  20. */
  21. bool cxllib_slot_is_supported(struct pci_dev *dev, unsigned long flags);
  22. /*
  23. * Returns the configuration parameters to be used by the XSL or device
  24. *
  25. * Input:
  26. * dev: device, used to find PHB
  27. * Output:
  28. * struct cxllib_xsl_config:
  29. * version
  30. * capi BAR address, i.e. 0x2000000000000-0x2FFFFFFFFFFFF
  31. * capi BAR size
  32. * data send control (XSL_DSNCTL)
  33. * dummy read address (XSL_DRA)
  34. */
  35. #define CXL_XSL_CONFIG_VERSION1 1
  36. struct cxllib_xsl_config {
  37. u32 version; /* format version for register encoding */
  38. u32 log_bar_size;/* log size of the capi_window */
  39. u64 bar_addr; /* address of the start of capi window */
  40. u64 dsnctl; /* matches definition of XSL_DSNCTL */
  41. u64 dra; /* real address that can be used for dummy read */
  42. };
  43. int cxllib_get_xsl_config(struct pci_dev *dev, struct cxllib_xsl_config *cfg);
  44. /*
  45. * Activate capi for the pci host bridge associated with the device.
  46. * Can be extended to deactivate once we know how to do it.
  47. * Device must be ready to accept messages from the CAPP unit and
  48. * respond accordingly (TLB invalidates, ...)
  49. *
  50. * PHB is switched to capi mode through calls to skiboot.
  51. * CAPP snooping is activated
  52. *
  53. * Input:
  54. * dev: device whose PHB should switch mode
  55. * mode: mode to switch to i.e. CAPI or PCI
  56. * flags: options related to the mode
  57. */
  58. enum cxllib_mode {
  59. CXL_MODE_CXL,
  60. CXL_MODE_PCI,
  61. };
  62. #define CXL_MODE_NO_DMA 0
  63. #define CXL_MODE_DMA_TVT0 1
  64. #define CXL_MODE_DMA_TVT1 2
  65. int cxllib_switch_phb_mode(struct pci_dev *dev, enum cxllib_mode mode,
  66. unsigned long flags);
  67. /*
  68. * Set the device for capi DMA.
  69. * Define its dma_ops and dma offset so that allocations will be using TVT#1
  70. *
  71. * Input:
  72. * dev: device to set
  73. * flags: options. CXL_MODE_DMA_TVT1 should be used
  74. */
  75. int cxllib_set_device_dma(struct pci_dev *dev, unsigned long flags);
  76. /*
  77. * Get the Process Element structure for the given thread
  78. *
  79. * Input:
  80. * task: task_struct for the context of the translation
  81. * translation_mode: whether addresses should be translated
  82. * Output:
  83. * attr: attributes to fill up the Process Element structure from CAIA
  84. */
  85. struct cxllib_pe_attributes {
  86. u64 sr;
  87. u32 lpid;
  88. u32 tid;
  89. u32 pid;
  90. };
  91. #define CXL_TRANSLATED_MODE 0
  92. #define CXL_REAL_MODE 1
  93. int cxllib_get_PE_attributes(struct task_struct *task,
  94. unsigned long translation_mode, struct cxllib_pe_attributes *attr);
  95. /*
  96. * Handle memory fault.
  97. * Fault in all the pages of the specified buffer for the permissions
  98. * provided in ‘flags’
  99. *
  100. * Shouldn't be called from interrupt context
  101. *
  102. * Input:
  103. * mm: struct mm for the thread faulting the pages
  104. * addr: base address of the buffer to page in
  105. * size: size of the buffer to page in
  106. * flags: permission requested (DSISR_ISSTORE...)
  107. */
  108. int cxllib_handle_fault(struct mm_struct *mm, u64 addr, u64 size, u64 flags);
  109. #endif /* _MISC_CXLLIB_H */