ti-emif-sram.h 5.1 KB

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  1. /*
  2. * TI AM33XX EMIF Routines
  3. *
  4. * Copyright (C) 2016-2017 Texas Instruments Inc.
  5. * Dave Gerlach
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation version 2.
  10. *
  11. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12. * kind, whether express or implied; without even the implied warranty
  13. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #ifndef __LINUX_TI_EMIF_H
  17. #define __LINUX_TI_EMIF_H
  18. #include <linux/kbuild.h>
  19. #include <linux/types.h>
  20. #ifndef __ASSEMBLY__
  21. struct emif_regs_amx3 {
  22. u32 emif_sdcfg_val;
  23. u32 emif_timing1_val;
  24. u32 emif_timing2_val;
  25. u32 emif_timing3_val;
  26. u32 emif_ref_ctrl_val;
  27. u32 emif_zqcfg_val;
  28. u32 emif_pmcr_val;
  29. u32 emif_pmcr_shdw_val;
  30. u32 emif_rd_wr_level_ramp_ctrl;
  31. u32 emif_rd_wr_exec_thresh;
  32. u32 emif_cos_config;
  33. u32 emif_priority_to_cos_mapping;
  34. u32 emif_connect_id_serv_1_map;
  35. u32 emif_connect_id_serv_2_map;
  36. u32 emif_ocp_config_val;
  37. u32 emif_lpddr2_nvm_tim;
  38. u32 emif_lpddr2_nvm_tim_shdw;
  39. u32 emif_dll_calib_ctrl_val;
  40. u32 emif_dll_calib_ctrl_val_shdw;
  41. u32 emif_ddr_phy_ctlr_1;
  42. u32 emif_ext_phy_ctrl_vals[120];
  43. };
  44. struct ti_emif_pm_data {
  45. void __iomem *ti_emif_base_addr_virt;
  46. phys_addr_t ti_emif_base_addr_phys;
  47. unsigned long ti_emif_sram_config;
  48. struct emif_regs_amx3 *regs_virt;
  49. phys_addr_t regs_phys;
  50. } __packed __aligned(8);
  51. struct ti_emif_pm_functions {
  52. u32 save_context;
  53. u32 restore_context;
  54. u32 run_hw_leveling;
  55. u32 enter_sr;
  56. u32 exit_sr;
  57. u32 abort_sr;
  58. } __packed __aligned(8);
  59. static inline void ti_emif_asm_offsets(void)
  60. {
  61. DEFINE(EMIF_SDCFG_VAL_OFFSET,
  62. offsetof(struct emif_regs_amx3, emif_sdcfg_val));
  63. DEFINE(EMIF_TIMING1_VAL_OFFSET,
  64. offsetof(struct emif_regs_amx3, emif_timing1_val));
  65. DEFINE(EMIF_TIMING2_VAL_OFFSET,
  66. offsetof(struct emif_regs_amx3, emif_timing2_val));
  67. DEFINE(EMIF_TIMING3_VAL_OFFSET,
  68. offsetof(struct emif_regs_amx3, emif_timing3_val));
  69. DEFINE(EMIF_REF_CTRL_VAL_OFFSET,
  70. offsetof(struct emif_regs_amx3, emif_ref_ctrl_val));
  71. DEFINE(EMIF_ZQCFG_VAL_OFFSET,
  72. offsetof(struct emif_regs_amx3, emif_zqcfg_val));
  73. DEFINE(EMIF_PMCR_VAL_OFFSET,
  74. offsetof(struct emif_regs_amx3, emif_pmcr_val));
  75. DEFINE(EMIF_PMCR_SHDW_VAL_OFFSET,
  76. offsetof(struct emif_regs_amx3, emif_pmcr_shdw_val));
  77. DEFINE(EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET,
  78. offsetof(struct emif_regs_amx3, emif_rd_wr_level_ramp_ctrl));
  79. DEFINE(EMIF_RD_WR_EXEC_THRESH_OFFSET,
  80. offsetof(struct emif_regs_amx3, emif_rd_wr_exec_thresh));
  81. DEFINE(EMIF_COS_CONFIG_OFFSET,
  82. offsetof(struct emif_regs_amx3, emif_cos_config));
  83. DEFINE(EMIF_PRIORITY_TO_COS_MAPPING_OFFSET,
  84. offsetof(struct emif_regs_amx3, emif_priority_to_cos_mapping));
  85. DEFINE(EMIF_CONNECT_ID_SERV_1_MAP_OFFSET,
  86. offsetof(struct emif_regs_amx3, emif_connect_id_serv_1_map));
  87. DEFINE(EMIF_CONNECT_ID_SERV_2_MAP_OFFSET,
  88. offsetof(struct emif_regs_amx3, emif_connect_id_serv_2_map));
  89. DEFINE(EMIF_OCP_CONFIG_VAL_OFFSET,
  90. offsetof(struct emif_regs_amx3, emif_ocp_config_val));
  91. DEFINE(EMIF_LPDDR2_NVM_TIM_OFFSET,
  92. offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim));
  93. DEFINE(EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET,
  94. offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim_shdw));
  95. DEFINE(EMIF_DLL_CALIB_CTRL_VAL_OFFSET,
  96. offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val));
  97. DEFINE(EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET,
  98. offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val_shdw));
  99. DEFINE(EMIF_DDR_PHY_CTLR_1_OFFSET,
  100. offsetof(struct emif_regs_amx3, emif_ddr_phy_ctlr_1));
  101. DEFINE(EMIF_EXT_PHY_CTRL_VALS_OFFSET,
  102. offsetof(struct emif_regs_amx3, emif_ext_phy_ctrl_vals));
  103. DEFINE(EMIF_REGS_AMX3_SIZE, sizeof(struct emif_regs_amx3));
  104. BLANK();
  105. DEFINE(EMIF_PM_BASE_ADDR_VIRT_OFFSET,
  106. offsetof(struct ti_emif_pm_data, ti_emif_base_addr_virt));
  107. DEFINE(EMIF_PM_BASE_ADDR_PHYS_OFFSET,
  108. offsetof(struct ti_emif_pm_data, ti_emif_base_addr_phys));
  109. DEFINE(EMIF_PM_CONFIG_OFFSET,
  110. offsetof(struct ti_emif_pm_data, ti_emif_sram_config));
  111. DEFINE(EMIF_PM_REGS_VIRT_OFFSET,
  112. offsetof(struct ti_emif_pm_data, regs_virt));
  113. DEFINE(EMIF_PM_REGS_PHYS_OFFSET,
  114. offsetof(struct ti_emif_pm_data, regs_phys));
  115. DEFINE(EMIF_PM_DATA_SIZE, sizeof(struct ti_emif_pm_data));
  116. BLANK();
  117. DEFINE(EMIF_PM_SAVE_CONTEXT_OFFSET,
  118. offsetof(struct ti_emif_pm_functions, save_context));
  119. DEFINE(EMIF_PM_RESTORE_CONTEXT_OFFSET,
  120. offsetof(struct ti_emif_pm_functions, restore_context));
  121. DEFINE(EMIF_PM_RUN_HW_LEVELING,
  122. offsetof(struct ti_emif_pm_functions, run_hw_leveling));
  123. DEFINE(EMIF_PM_ENTER_SR_OFFSET,
  124. offsetof(struct ti_emif_pm_functions, enter_sr));
  125. DEFINE(EMIF_PM_EXIT_SR_OFFSET,
  126. offsetof(struct ti_emif_pm_functions, exit_sr));
  127. DEFINE(EMIF_PM_ABORT_SR_OFFSET,
  128. offsetof(struct ti_emif_pm_functions, abort_sr));
  129. DEFINE(EMIF_PM_FUNCTIONS_SIZE, sizeof(struct ti_emif_pm_functions));
  130. }
  131. struct gen_pool;
  132. int ti_emif_copy_pm_function_table(struct gen_pool *sram_pool, void *dst);
  133. int ti_emif_get_mem_type(void);
  134. #endif
  135. #endif /* __LINUX_TI_EMIF_H */