sxgbe_platform.h 1.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * 10G controller driver for Samsung Exynos SoCs
  4. *
  5. * Copyright (C) 2013 Samsung Electronics Co., Ltd.
  6. * http://www.samsung.com
  7. *
  8. * Author: Siva Reddy Kallam <siva.kallam@samsung.com>
  9. */
  10. #ifndef __SXGBE_PLATFORM_H__
  11. #define __SXGBE_PLATFORM_H__
  12. #include <linux/phy.h>
  13. /* MDC Clock Selection define*/
  14. #define SXGBE_CSR_100_150M 0x0 /* MDC = clk_scr_i/62 */
  15. #define SXGBE_CSR_150_250M 0x1 /* MDC = clk_scr_i/102 */
  16. #define SXGBE_CSR_250_300M 0x2 /* MDC = clk_scr_i/122 */
  17. #define SXGBE_CSR_300_350M 0x3 /* MDC = clk_scr_i/142 */
  18. #define SXGBE_CSR_350_400M 0x4 /* MDC = clk_scr_i/162 */
  19. #define SXGBE_CSR_400_500M 0x5 /* MDC = clk_scr_i/202 */
  20. /* Platfrom data for platform device structure's
  21. * platform_data field
  22. */
  23. struct sxgbe_mdio_bus_data {
  24. unsigned int phy_mask;
  25. int *irqs;
  26. int probed_phy_irq;
  27. };
  28. struct sxgbe_dma_cfg {
  29. int pbl;
  30. int fixed_burst;
  31. int burst_map;
  32. int adv_addr_mode;
  33. };
  34. struct sxgbe_plat_data {
  35. char *phy_bus_name;
  36. int bus_id;
  37. int phy_addr;
  38. phy_interface_t interface;
  39. struct sxgbe_mdio_bus_data *mdio_bus_data;
  40. struct sxgbe_dma_cfg *dma_cfg;
  41. int clk_csr;
  42. int pmt;
  43. int force_sf_dma_mode;
  44. int force_thresh_dma_mode;
  45. int riwt_off;
  46. };
  47. #endif /* __SXGBE_PLATFORM_H__ */