switchtec.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Microsemi Switchtec PCIe Driver
  4. * Copyright (c) 2017, Microsemi Corporation
  5. */
  6. #ifndef _SWITCHTEC_H
  7. #define _SWITCHTEC_H
  8. #include <linux/pci.h>
  9. #include <linux/cdev.h>
  10. #define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024
  11. #define SWITCHTEC_MAX_PFF_CSR 255
  12. #define SWITCHTEC_EVENT_OCCURRED BIT(0)
  13. #define SWITCHTEC_EVENT_CLEAR BIT(0)
  14. #define SWITCHTEC_EVENT_EN_LOG BIT(1)
  15. #define SWITCHTEC_EVENT_EN_CLI BIT(2)
  16. #define SWITCHTEC_EVENT_EN_IRQ BIT(3)
  17. #define SWITCHTEC_EVENT_FATAL BIT(4)
  18. #define SWITCHTEC_DMA_MRPC_EN BIT(0)
  19. #define MRPC_GAS_READ 0x29
  20. #define MRPC_GAS_WRITE 0x87
  21. #define MRPC_CMD_ID(x) ((x) & 0xffff)
  22. enum {
  23. SWITCHTEC_GAS_MRPC_OFFSET = 0x0000,
  24. SWITCHTEC_GAS_TOP_CFG_OFFSET = 0x1000,
  25. SWITCHTEC_GAS_SW_EVENT_OFFSET = 0x1800,
  26. SWITCHTEC_GAS_SYS_INFO_OFFSET = 0x2000,
  27. SWITCHTEC_GAS_FLASH_INFO_OFFSET = 0x2200,
  28. SWITCHTEC_GAS_PART_CFG_OFFSET = 0x4000,
  29. SWITCHTEC_GAS_NTB_OFFSET = 0x10000,
  30. SWITCHTEC_GAS_PFF_CSR_OFFSET = 0x134000,
  31. };
  32. enum switchtec_gen {
  33. SWITCHTEC_GEN3,
  34. SWITCHTEC_GEN4,
  35. };
  36. struct mrpc_regs {
  37. u8 input_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
  38. u8 output_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
  39. u32 cmd;
  40. u32 status;
  41. u32 ret_value;
  42. u32 dma_en;
  43. u64 dma_addr;
  44. u32 dma_vector;
  45. u32 dma_ver;
  46. } __packed;
  47. enum mrpc_status {
  48. SWITCHTEC_MRPC_STATUS_INPROGRESS = 1,
  49. SWITCHTEC_MRPC_STATUS_DONE = 2,
  50. SWITCHTEC_MRPC_STATUS_ERROR = 0xFF,
  51. SWITCHTEC_MRPC_STATUS_INTERRUPTED = 0x100,
  52. };
  53. struct sw_event_regs {
  54. u64 event_report_ctrl;
  55. u64 reserved1;
  56. u64 part_event_bitmap;
  57. u64 reserved2;
  58. u32 global_summary;
  59. u32 reserved3[3];
  60. u32 stack_error_event_hdr;
  61. u32 stack_error_event_data;
  62. u32 reserved4[4];
  63. u32 ppu_error_event_hdr;
  64. u32 ppu_error_event_data;
  65. u32 reserved5[4];
  66. u32 isp_error_event_hdr;
  67. u32 isp_error_event_data;
  68. u32 reserved6[4];
  69. u32 sys_reset_event_hdr;
  70. u32 reserved7[5];
  71. u32 fw_exception_hdr;
  72. u32 reserved8[5];
  73. u32 fw_nmi_hdr;
  74. u32 reserved9[5];
  75. u32 fw_non_fatal_hdr;
  76. u32 reserved10[5];
  77. u32 fw_fatal_hdr;
  78. u32 reserved11[5];
  79. u32 twi_mrpc_comp_hdr;
  80. u32 twi_mrpc_comp_data;
  81. u32 reserved12[4];
  82. u32 twi_mrpc_comp_async_hdr;
  83. u32 twi_mrpc_comp_async_data;
  84. u32 reserved13[4];
  85. u32 cli_mrpc_comp_hdr;
  86. u32 cli_mrpc_comp_data;
  87. u32 reserved14[4];
  88. u32 cli_mrpc_comp_async_hdr;
  89. u32 cli_mrpc_comp_async_data;
  90. u32 reserved15[4];
  91. u32 gpio_interrupt_hdr;
  92. u32 gpio_interrupt_data;
  93. u32 reserved16[4];
  94. u32 gfms_event_hdr;
  95. u32 gfms_event_data;
  96. u32 reserved17[4];
  97. } __packed;
  98. enum {
  99. SWITCHTEC_GEN3_CFG0_RUNNING = 0x04,
  100. SWITCHTEC_GEN3_CFG1_RUNNING = 0x05,
  101. SWITCHTEC_GEN3_IMG0_RUNNING = 0x03,
  102. SWITCHTEC_GEN3_IMG1_RUNNING = 0x07,
  103. };
  104. enum {
  105. SWITCHTEC_GEN4_MAP0_RUNNING = 0x00,
  106. SWITCHTEC_GEN4_MAP1_RUNNING = 0x01,
  107. SWITCHTEC_GEN4_KEY0_RUNNING = 0x02,
  108. SWITCHTEC_GEN4_KEY1_RUNNING = 0x03,
  109. SWITCHTEC_GEN4_BL2_0_RUNNING = 0x04,
  110. SWITCHTEC_GEN4_BL2_1_RUNNING = 0x05,
  111. SWITCHTEC_GEN4_CFG0_RUNNING = 0x06,
  112. SWITCHTEC_GEN4_CFG1_RUNNING = 0x07,
  113. SWITCHTEC_GEN4_IMG0_RUNNING = 0x08,
  114. SWITCHTEC_GEN4_IMG1_RUNNING = 0x09,
  115. };
  116. enum {
  117. SWITCHTEC_GEN4_KEY0_ACTIVE = 0,
  118. SWITCHTEC_GEN4_KEY1_ACTIVE = 1,
  119. SWITCHTEC_GEN4_BL2_0_ACTIVE = 0,
  120. SWITCHTEC_GEN4_BL2_1_ACTIVE = 1,
  121. SWITCHTEC_GEN4_CFG0_ACTIVE = 0,
  122. SWITCHTEC_GEN4_CFG1_ACTIVE = 1,
  123. SWITCHTEC_GEN4_IMG0_ACTIVE = 0,
  124. SWITCHTEC_GEN4_IMG1_ACTIVE = 1,
  125. };
  126. struct sys_info_regs_gen3 {
  127. u32 reserved1;
  128. u32 vendor_table_revision;
  129. u32 table_format_version;
  130. u32 partition_id;
  131. u32 cfg_file_fmt_version;
  132. u16 cfg_running;
  133. u16 img_running;
  134. u32 reserved2[57];
  135. char vendor_id[8];
  136. char product_id[16];
  137. char product_revision[4];
  138. char component_vendor[8];
  139. u16 component_id;
  140. u8 component_revision;
  141. } __packed;
  142. struct sys_info_regs_gen4 {
  143. u16 gas_layout_ver;
  144. u8 evlist_ver;
  145. u8 reserved1;
  146. u16 mgmt_cmd_set_ver;
  147. u16 fabric_cmd_set_ver;
  148. u32 reserved2[2];
  149. u8 mrpc_uart_ver;
  150. u8 mrpc_twi_ver;
  151. u8 mrpc_eth_ver;
  152. u8 mrpc_inband_ver;
  153. u32 reserved3[7];
  154. u32 fw_update_tmo;
  155. u32 xml_version_cfg;
  156. u32 xml_version_img;
  157. u32 partition_id;
  158. u16 bl2_running;
  159. u16 cfg_running;
  160. u16 img_running;
  161. u16 key_running;
  162. u32 reserved4[43];
  163. u32 vendor_seeprom_twi;
  164. u32 vendor_table_revision;
  165. u32 vendor_specific_info[2];
  166. u16 p2p_vendor_id;
  167. u16 p2p_device_id;
  168. u8 p2p_revision_id;
  169. u8 reserved5[3];
  170. u32 p2p_class_id;
  171. u16 subsystem_vendor_id;
  172. u16 subsystem_id;
  173. u32 p2p_serial_number[2];
  174. u8 mac_addr[6];
  175. u8 reserved6[2];
  176. u32 reserved7[3];
  177. char vendor_id[8];
  178. char product_id[24];
  179. char product_revision[2];
  180. u16 reserved8;
  181. } __packed;
  182. struct sys_info_regs {
  183. u32 device_id;
  184. u32 device_version;
  185. u32 firmware_version;
  186. union {
  187. struct sys_info_regs_gen3 gen3;
  188. struct sys_info_regs_gen4 gen4;
  189. };
  190. } __packed;
  191. struct partition_info {
  192. u32 address;
  193. u32 length;
  194. };
  195. struct flash_info_regs_gen3 {
  196. u32 flash_part_map_upd_idx;
  197. struct active_partition_info_gen3 {
  198. u32 address;
  199. u32 build_version;
  200. u32 build_string;
  201. } active_img;
  202. struct active_partition_info_gen3 active_cfg;
  203. struct active_partition_info_gen3 inactive_img;
  204. struct active_partition_info_gen3 inactive_cfg;
  205. u32 flash_length;
  206. struct partition_info cfg0;
  207. struct partition_info cfg1;
  208. struct partition_info img0;
  209. struct partition_info img1;
  210. struct partition_info nvlog;
  211. struct partition_info vendor[8];
  212. };
  213. struct flash_info_regs_gen4 {
  214. u32 flash_address;
  215. u32 flash_length;
  216. struct active_partition_info_gen4 {
  217. unsigned char bl2;
  218. unsigned char cfg;
  219. unsigned char img;
  220. unsigned char key;
  221. } active_flag;
  222. u32 reserved[3];
  223. struct partition_info map0;
  224. struct partition_info map1;
  225. struct partition_info key0;
  226. struct partition_info key1;
  227. struct partition_info bl2_0;
  228. struct partition_info bl2_1;
  229. struct partition_info cfg0;
  230. struct partition_info cfg1;
  231. struct partition_info img0;
  232. struct partition_info img1;
  233. struct partition_info nvlog;
  234. struct partition_info vendor[8];
  235. };
  236. struct flash_info_regs {
  237. union {
  238. struct flash_info_regs_gen3 gen3;
  239. struct flash_info_regs_gen4 gen4;
  240. };
  241. };
  242. enum {
  243. SWITCHTEC_NTB_REG_INFO_OFFSET = 0x0000,
  244. SWITCHTEC_NTB_REG_CTRL_OFFSET = 0x4000,
  245. SWITCHTEC_NTB_REG_DBMSG_OFFSET = 0x64000,
  246. };
  247. struct ntb_info_regs {
  248. u8 partition_count;
  249. u8 partition_id;
  250. u16 reserved1;
  251. u64 ep_map;
  252. u16 requester_id;
  253. u16 reserved2;
  254. u32 reserved3[4];
  255. struct nt_partition_info {
  256. u32 xlink_enabled;
  257. u32 target_part_low;
  258. u32 target_part_high;
  259. u32 reserved;
  260. } ntp_info[48];
  261. } __packed;
  262. struct part_cfg_regs {
  263. u32 status;
  264. u32 state;
  265. u32 port_cnt;
  266. u32 usp_port_mode;
  267. u32 usp_pff_inst_id;
  268. u32 vep_pff_inst_id;
  269. u32 dsp_pff_inst_id[47];
  270. u32 reserved1[11];
  271. u16 vep_vector_number;
  272. u16 usp_vector_number;
  273. u32 port_event_bitmap;
  274. u32 reserved2[3];
  275. u32 part_event_summary;
  276. u32 reserved3[3];
  277. u32 part_reset_hdr;
  278. u32 part_reset_data[5];
  279. u32 mrpc_comp_hdr;
  280. u32 mrpc_comp_data[5];
  281. u32 mrpc_comp_async_hdr;
  282. u32 mrpc_comp_async_data[5];
  283. u32 dyn_binding_hdr;
  284. u32 dyn_binding_data[5];
  285. u32 intercomm_notify_hdr;
  286. u32 intercomm_notify_data[5];
  287. u32 reserved4[153];
  288. } __packed;
  289. enum {
  290. NTB_CTRL_PART_OP_LOCK = 0x1,
  291. NTB_CTRL_PART_OP_CFG = 0x2,
  292. NTB_CTRL_PART_OP_RESET = 0x3,
  293. NTB_CTRL_PART_STATUS_NORMAL = 0x1,
  294. NTB_CTRL_PART_STATUS_LOCKED = 0x2,
  295. NTB_CTRL_PART_STATUS_LOCKING = 0x3,
  296. NTB_CTRL_PART_STATUS_CONFIGURING = 0x4,
  297. NTB_CTRL_PART_STATUS_RESETTING = 0x5,
  298. NTB_CTRL_BAR_VALID = 1 << 0,
  299. NTB_CTRL_BAR_DIR_WIN_EN = 1 << 4,
  300. NTB_CTRL_BAR_LUT_WIN_EN = 1 << 5,
  301. NTB_CTRL_REQ_ID_EN = 1 << 0,
  302. NTB_CTRL_LUT_EN = 1 << 0,
  303. NTB_PART_CTRL_ID_PROT_DIS = 1 << 0,
  304. };
  305. struct ntb_ctrl_regs {
  306. u32 partition_status;
  307. u32 partition_op;
  308. u32 partition_ctrl;
  309. u32 bar_setup;
  310. u32 bar_error;
  311. u16 lut_table_entries;
  312. u16 lut_table_offset;
  313. u32 lut_error;
  314. u16 req_id_table_size;
  315. u16 req_id_table_offset;
  316. u32 req_id_error;
  317. u32 reserved1[7];
  318. struct {
  319. u32 ctl;
  320. u32 win_size;
  321. u64 xlate_addr;
  322. } bar_entry[6];
  323. struct {
  324. u32 win_size;
  325. u32 reserved[3];
  326. } bar_ext_entry[6];
  327. u32 reserved2[192];
  328. u32 req_id_table[512];
  329. u32 reserved3[256];
  330. u64 lut_entry[512];
  331. } __packed;
  332. #define NTB_DBMSG_IMSG_STATUS BIT_ULL(32)
  333. #define NTB_DBMSG_IMSG_MASK BIT_ULL(40)
  334. struct ntb_dbmsg_regs {
  335. u32 reserved1[1024];
  336. u64 odb;
  337. u64 odb_mask;
  338. u64 idb;
  339. u64 idb_mask;
  340. u8 idb_vec_map[64];
  341. u32 msg_map;
  342. u32 reserved2;
  343. struct {
  344. u32 msg;
  345. u32 status;
  346. } omsg[4];
  347. struct {
  348. u32 msg;
  349. u8 status;
  350. u8 mask;
  351. u8 src;
  352. u8 reserved;
  353. } imsg[4];
  354. u8 reserved3[3928];
  355. u8 msix_table[1024];
  356. u8 reserved4[3072];
  357. u8 pba[24];
  358. u8 reserved5[4072];
  359. } __packed;
  360. enum {
  361. SWITCHTEC_PART_CFG_EVENT_RESET = 1 << 0,
  362. SWITCHTEC_PART_CFG_EVENT_MRPC_CMP = 1 << 1,
  363. SWITCHTEC_PART_CFG_EVENT_MRPC_ASYNC_CMP = 1 << 2,
  364. SWITCHTEC_PART_CFG_EVENT_DYN_PART_CMP = 1 << 3,
  365. };
  366. struct pff_csr_regs {
  367. u16 vendor_id;
  368. u16 device_id;
  369. u16 pcicmd;
  370. u16 pcists;
  371. u32 pci_class;
  372. u32 pci_opts;
  373. union {
  374. u32 pci_bar[6];
  375. u64 pci_bar64[3];
  376. };
  377. u32 pci_cardbus;
  378. u32 pci_subsystem_id;
  379. u32 pci_expansion_rom;
  380. u32 pci_cap_ptr;
  381. u32 reserved1;
  382. u32 pci_irq;
  383. u32 pci_cap_region[48];
  384. u32 pcie_cap_region[448];
  385. u32 indirect_gas_window[128];
  386. u32 indirect_gas_window_off;
  387. u32 reserved[127];
  388. u32 pff_event_summary;
  389. u32 reserved2[3];
  390. u32 aer_in_p2p_hdr;
  391. u32 aer_in_p2p_data[5];
  392. u32 aer_in_vep_hdr;
  393. u32 aer_in_vep_data[5];
  394. u32 dpc_hdr;
  395. u32 dpc_data[5];
  396. u32 cts_hdr;
  397. u32 cts_data[5];
  398. u32 uec_hdr;
  399. u32 uec_data[5];
  400. u32 hotplug_hdr;
  401. u32 hotplug_data[5];
  402. u32 ier_hdr;
  403. u32 ier_data[5];
  404. u32 threshold_hdr;
  405. u32 threshold_data[5];
  406. u32 power_mgmt_hdr;
  407. u32 power_mgmt_data[5];
  408. u32 tlp_throttling_hdr;
  409. u32 tlp_throttling_data[5];
  410. u32 force_speed_hdr;
  411. u32 force_speed_data[5];
  412. u32 credit_timeout_hdr;
  413. u32 credit_timeout_data[5];
  414. u32 link_state_hdr;
  415. u32 link_state_data[5];
  416. u32 reserved4[174];
  417. } __packed;
  418. struct switchtec_ntb;
  419. struct dma_mrpc_output {
  420. u32 status;
  421. u32 cmd_id;
  422. u32 rtn_code;
  423. u32 output_size;
  424. u8 data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
  425. };
  426. struct switchtec_dev {
  427. struct pci_dev *pdev;
  428. struct device dev;
  429. struct cdev cdev;
  430. enum switchtec_gen gen;
  431. int partition;
  432. int partition_count;
  433. int pff_csr_count;
  434. char pff_local[SWITCHTEC_MAX_PFF_CSR];
  435. void __iomem *mmio;
  436. struct mrpc_regs __iomem *mmio_mrpc;
  437. struct sw_event_regs __iomem *mmio_sw_event;
  438. struct sys_info_regs __iomem *mmio_sys_info;
  439. struct flash_info_regs __iomem *mmio_flash_info;
  440. struct ntb_info_regs __iomem *mmio_ntb;
  441. struct part_cfg_regs __iomem *mmio_part_cfg;
  442. struct part_cfg_regs __iomem *mmio_part_cfg_all;
  443. struct pff_csr_regs __iomem *mmio_pff_csr;
  444. /*
  445. * The mrpc mutex must be held when accessing the other
  446. * mrpc_ fields, alive flag and stuser->state field
  447. */
  448. struct mutex mrpc_mutex;
  449. struct list_head mrpc_queue;
  450. int mrpc_busy;
  451. struct work_struct mrpc_work;
  452. struct delayed_work mrpc_timeout;
  453. bool alive;
  454. wait_queue_head_t event_wq;
  455. atomic_t event_cnt;
  456. struct work_struct link_event_work;
  457. void (*link_notifier)(struct switchtec_dev *stdev);
  458. u8 link_event_count[SWITCHTEC_MAX_PFF_CSR];
  459. struct switchtec_ntb *sndev;
  460. struct dma_mrpc_output *dma_mrpc;
  461. dma_addr_t dma_mrpc_dma_addr;
  462. };
  463. static inline struct switchtec_dev *to_stdev(struct device *dev)
  464. {
  465. return container_of(dev, struct switchtec_dev, dev);
  466. }
  467. extern struct class *switchtec_class;
  468. #endif