stmmac.h 5.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*******************************************************************************
  3. Header file for stmmac platform data
  4. Copyright (C) 2009 STMicroelectronics Ltd
  5. Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  6. *******************************************************************************/
  7. #ifndef __STMMAC_PLATFORM_DATA
  8. #define __STMMAC_PLATFORM_DATA
  9. #include <linux/platform_device.h>
  10. #include <linux/phy.h>
  11. #define MTL_MAX_RX_QUEUES 8
  12. #define MTL_MAX_TX_QUEUES 8
  13. #define STMMAC_CH_MAX 8
  14. #define STMMAC_RX_COE_NONE 0
  15. #define STMMAC_RX_COE_TYPE1 1
  16. #define STMMAC_RX_COE_TYPE2 2
  17. /* Define the macros for CSR clock range parameters to be passed by
  18. * platform code.
  19. * This could also be configured at run time using CPU freq framework. */
  20. /* MDC Clock Selection define*/
  21. #define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */
  22. #define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */
  23. #define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */
  24. #define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */
  25. #define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */
  26. #define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */
  27. /* MTL algorithms identifiers */
  28. #define MTL_TX_ALGORITHM_WRR 0x0
  29. #define MTL_TX_ALGORITHM_WFQ 0x1
  30. #define MTL_TX_ALGORITHM_DWRR 0x2
  31. #define MTL_TX_ALGORITHM_SP 0x3
  32. #define MTL_RX_ALGORITHM_SP 0x4
  33. #define MTL_RX_ALGORITHM_WSP 0x5
  34. /* RX/TX Queue Mode */
  35. #define MTL_QUEUE_AVB 0x0
  36. #define MTL_QUEUE_DCB 0x1
  37. /* The MDC clock could be set higher than the IEEE 802.3
  38. * specified frequency limit 0f 2.5 MHz, by programming a clock divider
  39. * of value different than the above defined values. The resultant MDIO
  40. * clock frequency of 12.5 MHz is applicable for the interfacing chips
  41. * supporting higher MDC clocks.
  42. * The MDC clock selection macros need to be defined for MDC clock rate
  43. * of 12.5 MHz, corresponding to the following selection.
  44. */
  45. #define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */
  46. #define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */
  47. #define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */
  48. #define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */
  49. #define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */
  50. #define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */
  51. #define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */
  52. #define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */
  53. /* AXI DMA Burst length supported */
  54. #define DMA_AXI_BLEN_4 (1 << 1)
  55. #define DMA_AXI_BLEN_8 (1 << 2)
  56. #define DMA_AXI_BLEN_16 (1 << 3)
  57. #define DMA_AXI_BLEN_32 (1 << 4)
  58. #define DMA_AXI_BLEN_64 (1 << 5)
  59. #define DMA_AXI_BLEN_128 (1 << 6)
  60. #define DMA_AXI_BLEN_256 (1 << 7)
  61. #define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
  62. | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
  63. | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)
  64. /* Platfrom data for platform device structure's platform_data field */
  65. struct stmmac_mdio_bus_data {
  66. unsigned int phy_mask;
  67. unsigned int has_xpcs;
  68. int *irqs;
  69. int probed_phy_irq;
  70. bool needs_reset;
  71. };
  72. struct stmmac_dma_cfg {
  73. int pbl;
  74. int txpbl;
  75. int rxpbl;
  76. bool pblx8;
  77. int fixed_burst;
  78. int mixed_burst;
  79. bool aal;
  80. bool eame;
  81. };
  82. #define AXI_BLEN 7
  83. struct stmmac_axi {
  84. bool axi_lpi_en;
  85. bool axi_xit_frm;
  86. u32 axi_wr_osr_lmt;
  87. u32 axi_rd_osr_lmt;
  88. bool axi_kbbe;
  89. u32 axi_blen[AXI_BLEN];
  90. bool axi_fb;
  91. bool axi_mb;
  92. bool axi_rb;
  93. };
  94. #define EST_GCL 1024
  95. struct stmmac_est {
  96. struct mutex lock;
  97. int enable;
  98. u32 btr_offset[2];
  99. u32 btr[2];
  100. u32 ctr[2];
  101. u32 ter;
  102. u32 gcl_unaligned[EST_GCL];
  103. u32 gcl[EST_GCL];
  104. u32 gcl_size;
  105. };
  106. struct stmmac_rxq_cfg {
  107. u8 mode_to_use;
  108. u32 chan;
  109. u8 pkt_route;
  110. bool use_prio;
  111. u32 prio;
  112. };
  113. struct stmmac_txq_cfg {
  114. u32 weight;
  115. u8 mode_to_use;
  116. /* Credit Base Shaper parameters */
  117. u32 send_slope;
  118. u32 idle_slope;
  119. u32 high_credit;
  120. u32 low_credit;
  121. bool use_prio;
  122. u32 prio;
  123. int tbs_en;
  124. };
  125. struct plat_stmmacenet_data {
  126. int bus_id;
  127. int phy_addr;
  128. int interface;
  129. phy_interface_t phy_interface;
  130. struct stmmac_mdio_bus_data *mdio_bus_data;
  131. struct device_node *phy_node;
  132. struct device_node *phylink_node;
  133. struct device_node *mdio_node;
  134. struct stmmac_dma_cfg *dma_cfg;
  135. struct stmmac_est *est;
  136. int clk_csr;
  137. int has_gmac;
  138. int enh_desc;
  139. int tx_coe;
  140. int rx_coe;
  141. int bugged_jumbo;
  142. int pmt;
  143. int force_sf_dma_mode;
  144. int force_thresh_dma_mode;
  145. int riwt_off;
  146. int max_speed;
  147. int maxmtu;
  148. int multicast_filter_bins;
  149. int unicast_filter_entries;
  150. int tx_fifo_size;
  151. int rx_fifo_size;
  152. u32 addr64;
  153. u32 rx_queues_to_use;
  154. u32 tx_queues_to_use;
  155. u8 rx_sched_algorithm;
  156. u8 tx_sched_algorithm;
  157. struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
  158. struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
  159. void (*fix_mac_speed)(void *priv, unsigned int speed);
  160. int (*serdes_powerup)(struct net_device *ndev, void *priv);
  161. void (*serdes_powerdown)(struct net_device *ndev, void *priv);
  162. int (*init)(struct platform_device *pdev, void *priv);
  163. void (*exit)(struct platform_device *pdev, void *priv);
  164. struct mac_device_info *(*setup)(void *priv);
  165. void *bsp_priv;
  166. struct clk *stmmac_clk;
  167. struct clk *pclk;
  168. struct clk *clk_ptp_ref;
  169. unsigned int clk_ptp_rate;
  170. unsigned int clk_ref_rate;
  171. s32 ptp_max_adj;
  172. struct reset_control *stmmac_rst;
  173. struct stmmac_axi *axi;
  174. int has_gmac4;
  175. bool has_sun8i;
  176. bool tso_en;
  177. int rss_en;
  178. int mac_port_sel_speed;
  179. bool en_tx_lpi_clockgating;
  180. int has_xgmac;
  181. bool vlan_fail_q_en;
  182. u8 vlan_fail_q;
  183. unsigned int eee_usecs_rate;
  184. };
  185. #endif