sm501-regs.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /* sm501-regs.h
  3. *
  4. * Copyright 2006 Simtec Electronics
  5. *
  6. * Silicon Motion SM501 register definitions
  7. */
  8. /* System Configuration area */
  9. /* System config base */
  10. #define SM501_SYS_CONFIG (0x000000)
  11. /* config 1 */
  12. #define SM501_SYSTEM_CONTROL (0x000000)
  13. #define SM501_SYSCTRL_PANEL_TRISTATE (1<<0)
  14. #define SM501_SYSCTRL_MEM_TRISTATE (1<<1)
  15. #define SM501_SYSCTRL_CRT_TRISTATE (1<<2)
  16. #define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3<<4)
  17. #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0<<4)
  18. #define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1<<4)
  19. #define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2<<4)
  20. #define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3<<4)
  21. #define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1<<6)
  22. #define SM501_SYSCTRL_PCI_RETRY_DISABLE (1<<7)
  23. #define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1<<11)
  24. #define SM501_SYSCTRL_PCI_BURST_READ_EN (1<<15)
  25. #define SM501_SYSCTRL_2D_ENGINE_STATUS (1<<19)
  26. /* miscellaneous control */
  27. #define SM501_MISC_CONTROL (0x000004)
  28. #define SM501_MISC_BUS_SH (0x0)
  29. #define SM501_MISC_BUS_PCI (0x1)
  30. #define SM501_MISC_BUS_XSCALE (0x2)
  31. #define SM501_MISC_BUS_NEC (0x6)
  32. #define SM501_MISC_BUS_MASK (0x7)
  33. #define SM501_MISC_VR_62MB (1<<3)
  34. #define SM501_MISC_CDR_RESET (1<<7)
  35. #define SM501_MISC_USB_LB (1<<8)
  36. #define SM501_MISC_USB_SLAVE (1<<9)
  37. #define SM501_MISC_BL_1 (1<<10)
  38. #define SM501_MISC_MC (1<<11)
  39. #define SM501_MISC_DAC_POWER (1<<12)
  40. #define SM501_MISC_IRQ_INVERT (1<<16)
  41. #define SM501_MISC_SH (1<<17)
  42. #define SM501_MISC_HOLD_EMPTY (0<<18)
  43. #define SM501_MISC_HOLD_8 (1<<18)
  44. #define SM501_MISC_HOLD_16 (2<<18)
  45. #define SM501_MISC_HOLD_24 (3<<18)
  46. #define SM501_MISC_HOLD_32 (4<<18)
  47. #define SM501_MISC_HOLD_MASK (7<<18)
  48. #define SM501_MISC_FREQ_12 (1<<24)
  49. #define SM501_MISC_PNL_24BIT (1<<25)
  50. #define SM501_MISC_8051_LE (1<<26)
  51. #define SM501_GPIO31_0_CONTROL (0x000008)
  52. #define SM501_GPIO63_32_CONTROL (0x00000C)
  53. #define SM501_DRAM_CONTROL (0x000010)
  54. /* command list */
  55. #define SM501_ARBTRTN_CONTROL (0x000014)
  56. /* command list */
  57. #define SM501_COMMAND_LIST_STATUS (0x000024)
  58. /* interrupt debug */
  59. #define SM501_RAW_IRQ_STATUS (0x000028)
  60. #define SM501_RAW_IRQ_CLEAR (0x000028)
  61. #define SM501_IRQ_STATUS (0x00002C)
  62. #define SM501_IRQ_MASK (0x000030)
  63. #define SM501_DEBUG_CONTROL (0x000034)
  64. /* power management */
  65. #define SM501_POWERMODE_P2X_SRC (1<<29)
  66. #define SM501_POWERMODE_V2X_SRC (1<<20)
  67. #define SM501_POWERMODE_M_SRC (1<<12)
  68. #define SM501_POWERMODE_M1_SRC (1<<4)
  69. #define SM501_CURRENT_GATE (0x000038)
  70. #define SM501_CURRENT_CLOCK (0x00003C)
  71. #define SM501_POWER_MODE_0_GATE (0x000040)
  72. #define SM501_POWER_MODE_0_CLOCK (0x000044)
  73. #define SM501_POWER_MODE_1_GATE (0x000048)
  74. #define SM501_POWER_MODE_1_CLOCK (0x00004C)
  75. #define SM501_SLEEP_MODE_GATE (0x000050)
  76. #define SM501_POWER_MODE_CONTROL (0x000054)
  77. /* power gates for units within the 501 */
  78. #define SM501_GATE_HOST (0)
  79. #define SM501_GATE_MEMORY (1)
  80. #define SM501_GATE_DISPLAY (2)
  81. #define SM501_GATE_2D_ENGINE (3)
  82. #define SM501_GATE_CSC (4)
  83. #define SM501_GATE_ZVPORT (5)
  84. #define SM501_GATE_GPIO (6)
  85. #define SM501_GATE_UART0 (7)
  86. #define SM501_GATE_UART1 (8)
  87. #define SM501_GATE_SSP (10)
  88. #define SM501_GATE_USB_HOST (11)
  89. #define SM501_GATE_USB_GADGET (12)
  90. #define SM501_GATE_UCONTROLLER (17)
  91. #define SM501_GATE_AC97 (18)
  92. /* panel clock */
  93. #define SM501_CLOCK_P2XCLK (24)
  94. /* crt clock */
  95. #define SM501_CLOCK_V2XCLK (16)
  96. /* main clock */
  97. #define SM501_CLOCK_MCLK (8)
  98. /* SDRAM controller clock */
  99. #define SM501_CLOCK_M1XCLK (0)
  100. /* config 2 */
  101. #define SM501_PCI_MASTER_BASE (0x000058)
  102. #define SM501_ENDIAN_CONTROL (0x00005C)
  103. #define SM501_DEVICEID (0x000060)
  104. /* 0x050100A0 */
  105. #define SM501_DEVICEID_SM501 (0x05010000)
  106. #define SM501_DEVICEID_IDMASK (0xffff0000)
  107. #define SM501_DEVICEID_REVMASK (0x000000ff)
  108. #define SM501_PLLCLOCK_COUNT (0x000064)
  109. #define SM501_MISC_TIMING (0x000068)
  110. #define SM501_CURRENT_SDRAM_CLOCK (0x00006C)
  111. #define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074)
  112. /* GPIO base */
  113. #define SM501_GPIO (0x010000)
  114. #define SM501_GPIO_DATA_LOW (0x00)
  115. #define SM501_GPIO_DATA_HIGH (0x04)
  116. #define SM501_GPIO_DDR_LOW (0x08)
  117. #define SM501_GPIO_DDR_HIGH (0x0C)
  118. #define SM501_GPIO_IRQ_SETUP (0x10)
  119. #define SM501_GPIO_IRQ_STATUS (0x14)
  120. #define SM501_GPIO_IRQ_RESET (0x14)
  121. /* I2C controller base */
  122. #define SM501_I2C (0x010040)
  123. #define SM501_I2C_BYTE_COUNT (0x00)
  124. #define SM501_I2C_CONTROL (0x01)
  125. #define SM501_I2C_STATUS (0x02)
  126. #define SM501_I2C_RESET (0x02)
  127. #define SM501_I2C_SLAVE_ADDRESS (0x03)
  128. #define SM501_I2C_DATA (0x04)
  129. /* SSP base */
  130. #define SM501_SSP (0x020000)
  131. /* Uart 0 base */
  132. #define SM501_UART0 (0x030000)
  133. /* Uart 1 base */
  134. #define SM501_UART1 (0x030020)
  135. /* USB host port base */
  136. #define SM501_USB_HOST (0x040000)
  137. /* USB slave/gadget base */
  138. #define SM501_USB_GADGET (0x060000)
  139. /* USB slave/gadget data port base */
  140. #define SM501_USB_GADGET_DATA (0x070000)
  141. /* Display controller/video engine base */
  142. #define SM501_DC (0x080000)
  143. /* common defines for the SM501 address registers */
  144. #define SM501_ADDR_FLIP (1<<31)
  145. #define SM501_ADDR_EXT (1<<27)
  146. #define SM501_ADDR_CS1 (1<<26)
  147. #define SM501_ADDR_MASK (0x3f << 26)
  148. #define SM501_FIFO_MASK (0x3 << 16)
  149. #define SM501_FIFO_1 (0x0 << 16)
  150. #define SM501_FIFO_3 (0x1 << 16)
  151. #define SM501_FIFO_7 (0x2 << 16)
  152. #define SM501_FIFO_11 (0x3 << 16)
  153. /* common registers for panel and the crt */
  154. #define SM501_OFF_DC_H_TOT (0x000)
  155. #define SM501_OFF_DC_V_TOT (0x008)
  156. #define SM501_OFF_DC_H_SYNC (0x004)
  157. #define SM501_OFF_DC_V_SYNC (0x00C)
  158. #define SM501_DC_PANEL_CONTROL (0x000)
  159. #define SM501_DC_PANEL_CONTROL_FPEN (1<<27)
  160. #define SM501_DC_PANEL_CONTROL_BIAS (1<<26)
  161. #define SM501_DC_PANEL_CONTROL_DATA (1<<25)
  162. #define SM501_DC_PANEL_CONTROL_VDD (1<<24)
  163. #define SM501_DC_PANEL_CONTROL_DP (1<<23)
  164. #define SM501_DC_PANEL_CONTROL_TFT_888 (0<<21)
  165. #define SM501_DC_PANEL_CONTROL_TFT_333 (1<<21)
  166. #define SM501_DC_PANEL_CONTROL_TFT_444 (2<<21)
  167. #define SM501_DC_PANEL_CONTROL_DE (1<<20)
  168. #define SM501_DC_PANEL_CONTROL_LCD_TFT (0<<18)
  169. #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1<<18)
  170. #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2<<18)
  171. #define SM501_DC_PANEL_CONTROL_CP (1<<14)
  172. #define SM501_DC_PANEL_CONTROL_VSP (1<<13)
  173. #define SM501_DC_PANEL_CONTROL_HSP (1<<12)
  174. #define SM501_DC_PANEL_CONTROL_CK (1<<9)
  175. #define SM501_DC_PANEL_CONTROL_TE (1<<8)
  176. #define SM501_DC_PANEL_CONTROL_VPD (1<<7)
  177. #define SM501_DC_PANEL_CONTROL_VP (1<<6)
  178. #define SM501_DC_PANEL_CONTROL_HPD (1<<5)
  179. #define SM501_DC_PANEL_CONTROL_HP (1<<4)
  180. #define SM501_DC_PANEL_CONTROL_GAMMA (1<<3)
  181. #define SM501_DC_PANEL_CONTROL_EN (1<<2)
  182. #define SM501_DC_PANEL_CONTROL_8BPP (0<<0)
  183. #define SM501_DC_PANEL_CONTROL_16BPP (1<<0)
  184. #define SM501_DC_PANEL_CONTROL_32BPP (2<<0)
  185. #define SM501_DC_PANEL_PANNING_CONTROL (0x004)
  186. #define SM501_DC_PANEL_COLOR_KEY (0x008)
  187. #define SM501_DC_PANEL_FB_ADDR (0x00C)
  188. #define SM501_DC_PANEL_FB_OFFSET (0x010)
  189. #define SM501_DC_PANEL_FB_WIDTH (0x014)
  190. #define SM501_DC_PANEL_FB_HEIGHT (0x018)
  191. #define SM501_DC_PANEL_TL_LOC (0x01C)
  192. #define SM501_DC_PANEL_BR_LOC (0x020)
  193. #define SM501_DC_PANEL_H_TOT (0x024)
  194. #define SM501_DC_PANEL_H_SYNC (0x028)
  195. #define SM501_DC_PANEL_V_TOT (0x02C)
  196. #define SM501_DC_PANEL_V_SYNC (0x030)
  197. #define SM501_DC_PANEL_CUR_LINE (0x034)
  198. #define SM501_DC_VIDEO_CONTROL (0x040)
  199. #define SM501_DC_VIDEO_FB0_ADDR (0x044)
  200. #define SM501_DC_VIDEO_FB_WIDTH (0x048)
  201. #define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C)
  202. #define SM501_DC_VIDEO_TL_LOC (0x050)
  203. #define SM501_DC_VIDEO_BR_LOC (0x054)
  204. #define SM501_DC_VIDEO_SCALE (0x058)
  205. #define SM501_DC_VIDEO_INIT_SCALE (0x05C)
  206. #define SM501_DC_VIDEO_YUV_CONSTANTS (0x060)
  207. #define SM501_DC_VIDEO_FB1_ADDR (0x064)
  208. #define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068)
  209. #define SM501_DC_VIDEO_ALPHA_CONTROL (0x080)
  210. #define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084)
  211. #define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088)
  212. #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C)
  213. #define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090)
  214. #define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094)
  215. #define SM501_DC_VIDEO_ALPHA_SCALE (0x098)
  216. #define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C)
  217. #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0)
  218. #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4)
  219. #define SM501_DC_PANEL_HWC_BASE (0x0F0)
  220. #define SM501_DC_PANEL_HWC_ADDR (0x0F0)
  221. #define SM501_DC_PANEL_HWC_LOC (0x0F4)
  222. #define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8)
  223. #define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC)
  224. #define SM501_HWC_EN (1<<31)
  225. #define SM501_OFF_HWC_ADDR (0x00)
  226. #define SM501_OFF_HWC_LOC (0x04)
  227. #define SM501_OFF_HWC_COLOR_1_2 (0x08)
  228. #define SM501_OFF_HWC_COLOR_3 (0x0C)
  229. #define SM501_DC_ALPHA_CONTROL (0x100)
  230. #define SM501_DC_ALPHA_FB_ADDR (0x104)
  231. #define SM501_DC_ALPHA_FB_OFFSET (0x108)
  232. #define SM501_DC_ALPHA_TL_LOC (0x10C)
  233. #define SM501_DC_ALPHA_BR_LOC (0x110)
  234. #define SM501_DC_ALPHA_CHROMA_KEY (0x114)
  235. #define SM501_DC_ALPHA_COLOR_LOOKUP (0x118)
  236. #define SM501_DC_CRT_CONTROL (0x200)
  237. #define SM501_DC_CRT_CONTROL_TVP (1<<15)
  238. #define SM501_DC_CRT_CONTROL_CP (1<<14)
  239. #define SM501_DC_CRT_CONTROL_VSP (1<<13)
  240. #define SM501_DC_CRT_CONTROL_HSP (1<<12)
  241. #define SM501_DC_CRT_CONTROL_VS (1<<11)
  242. #define SM501_DC_CRT_CONTROL_BLANK (1<<10)
  243. #define SM501_DC_CRT_CONTROL_SEL (1<<9)
  244. #define SM501_DC_CRT_CONTROL_TE (1<<8)
  245. #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4)
  246. #define SM501_DC_CRT_CONTROL_GAMMA (1<<3)
  247. #define SM501_DC_CRT_CONTROL_ENABLE (1<<2)
  248. #define SM501_DC_CRT_CONTROL_8BPP (0<<0)
  249. #define SM501_DC_CRT_CONTROL_16BPP (1<<0)
  250. #define SM501_DC_CRT_CONTROL_32BPP (2<<0)
  251. #define SM501_DC_CRT_FB_ADDR (0x204)
  252. #define SM501_DC_CRT_FB_OFFSET (0x208)
  253. #define SM501_DC_CRT_H_TOT (0x20C)
  254. #define SM501_DC_CRT_H_SYNC (0x210)
  255. #define SM501_DC_CRT_V_TOT (0x214)
  256. #define SM501_DC_CRT_V_SYNC (0x218)
  257. #define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C)
  258. #define SM501_DC_CRT_CUR_LINE (0x220)
  259. #define SM501_DC_CRT_MONITOR_DETECT (0x224)
  260. #define SM501_DC_CRT_HWC_BASE (0x230)
  261. #define SM501_DC_CRT_HWC_ADDR (0x230)
  262. #define SM501_DC_CRT_HWC_LOC (0x234)
  263. #define SM501_DC_CRT_HWC_COLOR_1_2 (0x238)
  264. #define SM501_DC_CRT_HWC_COLOR_3 (0x23C)
  265. #define SM501_DC_PANEL_PALETTE (0x400)
  266. #define SM501_DC_VIDEO_PALETTE (0x800)
  267. #define SM501_DC_CRT_PALETTE (0xC00)
  268. /* Zoom Video port base */
  269. #define SM501_ZVPORT (0x090000)
  270. /* AC97/I2S base */
  271. #define SM501_AC97 (0x0A0000)
  272. /* 8051 micro controller base */
  273. #define SM501_UCONTROLLER (0x0B0000)
  274. /* 8051 micro controller SRAM base */
  275. #define SM501_UCONTROLLER_SRAM (0x0C0000)
  276. /* DMA base */
  277. #define SM501_DMA (0x0D0000)
  278. /* 2d engine base */
  279. #define SM501_2D_ENGINE (0x100000)
  280. #define SM501_2D_SOURCE (0x00)
  281. #define SM501_2D_DESTINATION (0x04)
  282. #define SM501_2D_DIMENSION (0x08)
  283. #define SM501_2D_CONTROL (0x0C)
  284. #define SM501_2D_PITCH (0x10)
  285. #define SM501_2D_FOREGROUND (0x14)
  286. #define SM501_2D_BACKGROUND (0x18)
  287. #define SM501_2D_STRETCH (0x1C)
  288. #define SM501_2D_COLOR_COMPARE (0x20)
  289. #define SM501_2D_COLOR_COMPARE_MASK (0x24)
  290. #define SM501_2D_MASK (0x28)
  291. #define SM501_2D_CLIP_TL (0x2C)
  292. #define SM501_2D_CLIP_BR (0x30)
  293. #define SM501_2D_MONO_PATTERN_LOW (0x34)
  294. #define SM501_2D_MONO_PATTERN_HIGH (0x38)
  295. #define SM501_2D_WINDOW_WIDTH (0x3C)
  296. #define SM501_2D_SOURCE_BASE (0x40)
  297. #define SM501_2D_DESTINATION_BASE (0x44)
  298. #define SM501_2D_ALPHA (0x48)
  299. #define SM501_2D_WRAP (0x4C)
  300. #define SM501_2D_STATUS (0x50)
  301. #define SM501_CSC_Y_SOURCE_BASE (0xC8)
  302. #define SM501_CSC_CONSTANTS (0xCC)
  303. #define SM501_CSC_Y_SOURCE_X (0xD0)
  304. #define SM501_CSC_Y_SOURCE_Y (0xD4)
  305. #define SM501_CSC_U_SOURCE_BASE (0xD8)
  306. #define SM501_CSC_V_SOURCE_BASE (0xDC)
  307. #define SM501_CSC_SOURCE_DIMENSION (0xE0)
  308. #define SM501_CSC_SOURCE_PITCH (0xE4)
  309. #define SM501_CSC_DESTINATION (0xE8)
  310. #define SM501_CSC_DESTINATION_DIMENSION (0xEC)
  311. #define SM501_CSC_DESTINATION_PITCH (0xF0)
  312. #define SM501_CSC_SCALE_FACTOR (0xF4)
  313. #define SM501_CSC_DESTINATION_BASE (0xF8)
  314. #define SM501_CSC_CONTROL (0xFC)
  315. /* 2d engine data port base */
  316. #define SM501_2D_ENGINE_DATA (0x110000)