shdma-base.h 4.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * Dmaengine driver base library for DMA controllers, found on SH-based SoCs
  4. *
  5. * extracted from shdma.c and headers
  6. *
  7. * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  8. * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
  9. * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
  10. * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
  11. */
  12. #ifndef SHDMA_BASE_H
  13. #define SHDMA_BASE_H
  14. #include <linux/dmaengine.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/list.h>
  17. #include <linux/types.h>
  18. /**
  19. * shdma_pm_state - DMA channel PM state
  20. * SHDMA_PM_ESTABLISHED: either idle or during data transfer
  21. * SHDMA_PM_BUSY: during the transfer preparation, when we have to
  22. * drop the lock temporarily
  23. * SHDMA_PM_PENDING: transfers pending
  24. */
  25. enum shdma_pm_state {
  26. SHDMA_PM_ESTABLISHED,
  27. SHDMA_PM_BUSY,
  28. SHDMA_PM_PENDING,
  29. };
  30. struct device;
  31. /*
  32. * Drivers, using this library are expected to embed struct shdma_dev,
  33. * struct shdma_chan, struct shdma_desc, and struct shdma_slave
  34. * in their respective device, channel, descriptor and slave objects.
  35. */
  36. struct shdma_slave {
  37. int slave_id;
  38. };
  39. struct shdma_desc {
  40. struct list_head node;
  41. struct dma_async_tx_descriptor async_tx;
  42. enum dma_transfer_direction direction;
  43. size_t partial;
  44. dma_cookie_t cookie;
  45. int chunks;
  46. int mark;
  47. bool cyclic; /* used as cyclic transfer */
  48. };
  49. struct shdma_chan {
  50. spinlock_t chan_lock; /* Channel operation lock */
  51. struct list_head ld_queue; /* Link descriptors queue */
  52. struct list_head ld_free; /* Free link descriptors */
  53. struct dma_chan dma_chan; /* DMA channel */
  54. struct device *dev; /* Channel device */
  55. void *desc; /* buffer for descriptor array */
  56. int desc_num; /* desc count */
  57. size_t max_xfer_len; /* max transfer length */
  58. int id; /* Raw id of this channel */
  59. int irq; /* Channel IRQ */
  60. int slave_id; /* Client ID for slave DMA */
  61. int real_slave_id; /* argument passed to filter function */
  62. int hw_req; /* DMA request line for slave DMA - same
  63. * as MID/RID, used with DT */
  64. enum shdma_pm_state pm_state;
  65. };
  66. /**
  67. * struct shdma_ops - simple DMA driver operations
  68. * desc_completed: return true, if this is the descriptor, that just has
  69. * completed (atomic)
  70. * halt_channel: stop DMA channel operation (atomic)
  71. * channel_busy: return true, if the channel is busy (atomic)
  72. * slave_addr: return slave DMA address
  73. * desc_setup: set up the hardware specific descriptor portion (atomic)
  74. * set_slave: bind channel to a slave
  75. * setup_xfer: configure channel hardware for operation (atomic)
  76. * start_xfer: start the DMA transfer (atomic)
  77. * embedded_desc: return Nth struct shdma_desc pointer from the
  78. * descriptor array
  79. * chan_irq: process channel IRQ, return true if a transfer has
  80. * completed (atomic)
  81. */
  82. struct shdma_ops {
  83. bool (*desc_completed)(struct shdma_chan *, struct shdma_desc *);
  84. void (*halt_channel)(struct shdma_chan *);
  85. bool (*channel_busy)(struct shdma_chan *);
  86. dma_addr_t (*slave_addr)(struct shdma_chan *);
  87. int (*desc_setup)(struct shdma_chan *, struct shdma_desc *,
  88. dma_addr_t, dma_addr_t, size_t *);
  89. int (*set_slave)(struct shdma_chan *, int, dma_addr_t, bool);
  90. void (*setup_xfer)(struct shdma_chan *, int);
  91. void (*start_xfer)(struct shdma_chan *, struct shdma_desc *);
  92. struct shdma_desc *(*embedded_desc)(void *, int);
  93. bool (*chan_irq)(struct shdma_chan *, int);
  94. size_t (*get_partial)(struct shdma_chan *, struct shdma_desc *);
  95. };
  96. struct shdma_dev {
  97. struct dma_device dma_dev;
  98. struct shdma_chan **schan;
  99. const struct shdma_ops *ops;
  100. size_t desc_size;
  101. };
  102. #define shdma_for_each_chan(c, d, i) for (i = 0, c = (d)->schan[0]; \
  103. i < (d)->dma_dev.chancnt; c = (d)->schan[++i])
  104. int shdma_request_irq(struct shdma_chan *, int,
  105. unsigned long, const char *);
  106. bool shdma_reset(struct shdma_dev *sdev);
  107. void shdma_chan_probe(struct shdma_dev *sdev,
  108. struct shdma_chan *schan, int id);
  109. void shdma_chan_remove(struct shdma_chan *schan);
  110. int shdma_init(struct device *dev, struct shdma_dev *sdev,
  111. int chan_num);
  112. void shdma_cleanup(struct shdma_dev *sdev);
  113. #if IS_ENABLED(CONFIG_SH_DMAE_BASE)
  114. bool shdma_chan_filter(struct dma_chan *chan, void *arg);
  115. #else
  116. static inline bool shdma_chan_filter(struct dma_chan *chan, void *arg)
  117. {
  118. return false;
  119. }
  120. #endif
  121. #endif