sh_clk.h 6.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef __SH_CLOCK_H
  3. #define __SH_CLOCK_H
  4. #include <linux/list.h>
  5. #include <linux/seq_file.h>
  6. #include <linux/cpufreq.h>
  7. #include <linux/types.h>
  8. #include <linux/kref.h>
  9. #include <linux/clk.h>
  10. #include <linux/err.h>
  11. struct clk;
  12. struct clk_mapping {
  13. phys_addr_t phys;
  14. void __iomem *base;
  15. unsigned long len;
  16. struct kref ref;
  17. };
  18. struct sh_clk_ops {
  19. #ifdef CONFIG_SH_CLK_CPG_LEGACY
  20. void (*init)(struct clk *clk);
  21. #endif
  22. int (*enable)(struct clk *clk);
  23. void (*disable)(struct clk *clk);
  24. unsigned long (*recalc)(struct clk *clk);
  25. int (*set_rate)(struct clk *clk, unsigned long rate);
  26. int (*set_parent)(struct clk *clk, struct clk *parent);
  27. long (*round_rate)(struct clk *clk, unsigned long rate);
  28. };
  29. #define SH_CLK_DIV_MSK(div) ((1 << (div)) - 1)
  30. #define SH_CLK_DIV4_MSK SH_CLK_DIV_MSK(4)
  31. #define SH_CLK_DIV6_MSK SH_CLK_DIV_MSK(6)
  32. struct clk {
  33. struct list_head node;
  34. struct clk *parent;
  35. struct clk **parent_table; /* list of parents to */
  36. unsigned short parent_num; /* choose between */
  37. unsigned char src_shift; /* source clock field in the */
  38. unsigned char src_width; /* configuration register */
  39. struct sh_clk_ops *ops;
  40. struct list_head children;
  41. struct list_head sibling; /* node for children */
  42. int usecount;
  43. unsigned long rate;
  44. unsigned long flags;
  45. void __iomem *enable_reg;
  46. void __iomem *status_reg;
  47. unsigned int enable_bit;
  48. void __iomem *mapped_reg;
  49. unsigned int div_mask;
  50. unsigned long arch_flags;
  51. void *priv;
  52. struct clk_mapping *mapping;
  53. struct cpufreq_frequency_table *freq_table;
  54. unsigned int nr_freqs;
  55. };
  56. #define CLK_ENABLE_ON_INIT BIT(0)
  57. #define CLK_ENABLE_REG_32BIT BIT(1) /* default access size */
  58. #define CLK_ENABLE_REG_16BIT BIT(2)
  59. #define CLK_ENABLE_REG_8BIT BIT(3)
  60. #define CLK_MASK_DIV_ON_DISABLE BIT(4)
  61. #define CLK_ENABLE_REG_MASK (CLK_ENABLE_REG_32BIT | \
  62. CLK_ENABLE_REG_16BIT | \
  63. CLK_ENABLE_REG_8BIT)
  64. /* drivers/sh/clk.c */
  65. unsigned long followparent_recalc(struct clk *);
  66. void recalculate_root_clocks(void);
  67. void propagate_rate(struct clk *);
  68. int clk_reparent(struct clk *child, struct clk *parent);
  69. int clk_register(struct clk *);
  70. void clk_unregister(struct clk *);
  71. void clk_enable_init_clocks(void);
  72. struct clk_div_mult_table {
  73. unsigned int *divisors;
  74. unsigned int nr_divisors;
  75. unsigned int *multipliers;
  76. unsigned int nr_multipliers;
  77. };
  78. struct cpufreq_frequency_table;
  79. void clk_rate_table_build(struct clk *clk,
  80. struct cpufreq_frequency_table *freq_table,
  81. int nr_freqs,
  82. struct clk_div_mult_table *src_table,
  83. unsigned long *bitmap);
  84. long clk_rate_table_round(struct clk *clk,
  85. struct cpufreq_frequency_table *freq_table,
  86. unsigned long rate);
  87. int clk_rate_table_find(struct clk *clk,
  88. struct cpufreq_frequency_table *freq_table,
  89. unsigned long rate);
  90. long clk_rate_div_range_round(struct clk *clk, unsigned int div_min,
  91. unsigned int div_max, unsigned long rate);
  92. long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min,
  93. unsigned int mult_max, unsigned long rate);
  94. #define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _status_reg, _flags) \
  95. { \
  96. .parent = _parent, \
  97. .enable_reg = (void __iomem *)_enable_reg, \
  98. .enable_bit = _enable_bit, \
  99. .status_reg = _status_reg, \
  100. .flags = _flags, \
  101. }
  102. #define SH_CLK_MSTP32(_p, _r, _b, _f) \
  103. SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_32BIT)
  104. #define SH_CLK_MSTP32_STS(_p, _r, _b, _s, _f) \
  105. SH_CLK_MSTP(_p, _r, _b, _s, _f | CLK_ENABLE_REG_32BIT)
  106. #define SH_CLK_MSTP16(_p, _r, _b, _f) \
  107. SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_16BIT)
  108. #define SH_CLK_MSTP8(_p, _r, _b, _f) \
  109. SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_8BIT)
  110. int sh_clk_mstp_register(struct clk *clks, int nr);
  111. /*
  112. * MSTP registration never really cared about access size, despite the
  113. * original enable/disable pairs assuming a 32-bit access. Clocks are
  114. * responsible for defining their access sizes either directly or via the
  115. * clock definition wrappers.
  116. */
  117. static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr)
  118. {
  119. return sh_clk_mstp_register(clks, nr);
  120. }
  121. #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \
  122. { \
  123. .parent = _parent, \
  124. .enable_reg = (void __iomem *)_reg, \
  125. .enable_bit = _shift, \
  126. .arch_flags = _div_bitmap, \
  127. .div_mask = SH_CLK_DIV4_MSK, \
  128. .flags = _flags, \
  129. }
  130. struct clk_div_table {
  131. struct clk_div_mult_table *div_mult_table;
  132. void (*kick)(struct clk *clk);
  133. };
  134. #define clk_div4_table clk_div_table
  135. int sh_clk_div4_register(struct clk *clks, int nr,
  136. struct clk_div4_table *table);
  137. int sh_clk_div4_enable_register(struct clk *clks, int nr,
  138. struct clk_div4_table *table);
  139. int sh_clk_div4_reparent_register(struct clk *clks, int nr,
  140. struct clk_div4_table *table);
  141. #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \
  142. _num_parents, _src_shift, _src_width) \
  143. { \
  144. .enable_reg = (void __iomem *)_reg, \
  145. .enable_bit = 0, /* unused */ \
  146. .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
  147. .div_mask = SH_CLK_DIV6_MSK, \
  148. .parent_table = _parents, \
  149. .parent_num = _num_parents, \
  150. .src_shift = _src_shift, \
  151. .src_width = _src_width, \
  152. }
  153. #define SH_CLK_DIV6(_parent, _reg, _flags) \
  154. { \
  155. .parent = _parent, \
  156. .enable_reg = (void __iomem *)_reg, \
  157. .enable_bit = 0, /* unused */ \
  158. .div_mask = SH_CLK_DIV6_MSK, \
  159. .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
  160. }
  161. int sh_clk_div6_register(struct clk *clks, int nr);
  162. int sh_clk_div6_reparent_register(struct clk *clks, int nr);
  163. #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
  164. #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
  165. #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
  166. /* .enable_reg will be updated to .mapping on sh_clk_fsidiv_register() */
  167. #define SH_CLK_FSIDIV(_reg, _parent) \
  168. { \
  169. .enable_reg = (void __iomem *)_reg, \
  170. .parent = _parent, \
  171. }
  172. int sh_clk_fsidiv_register(struct clk *clks, int nr);
  173. #endif /* __SH_CLOCK_H */