serial_s3c.h 8.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Internal header file for Samsung S3C2410 serial ports (UART0-2)
  4. *
  5. * Copyright (C) 2002 Shane Nay (shane@minirl.com)
  6. *
  7. * Additional defines, Copyright 2003 Simtec Electronics (linux@simtec.co.uk)
  8. *
  9. * Adapted from:
  10. *
  11. * Internal header file for MX1ADS serial ports (UART1 & 2)
  12. *
  13. * Copyright (C) 2002 Shane Nay (shane@minirl.com)
  14. */
  15. #ifndef __ASM_ARM_REGS_SERIAL_H
  16. #define __ASM_ARM_REGS_SERIAL_H
  17. #define S3C2410_URXH (0x24)
  18. #define S3C2410_UTXH (0x20)
  19. #define S3C2410_ULCON (0x00)
  20. #define S3C2410_UCON (0x04)
  21. #define S3C2410_UFCON (0x08)
  22. #define S3C2410_UMCON (0x0C)
  23. #define S3C2410_UBRDIV (0x28)
  24. #define S3C2410_UTRSTAT (0x10)
  25. #define S3C2410_UERSTAT (0x14)
  26. #define S3C2410_UFSTAT (0x18)
  27. #define S3C2410_UMSTAT (0x1C)
  28. #define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3))
  29. #define S3C2410_LCON_CS5 (0x0)
  30. #define S3C2410_LCON_CS6 (0x1)
  31. #define S3C2410_LCON_CS7 (0x2)
  32. #define S3C2410_LCON_CS8 (0x3)
  33. #define S3C2410_LCON_CSMASK (0x3)
  34. #define S3C2410_LCON_PNONE (0x0)
  35. #define S3C2410_LCON_PEVEN (0x5 << 3)
  36. #define S3C2410_LCON_PODD (0x4 << 3)
  37. #define S3C2410_LCON_PMASK (0x7 << 3)
  38. #define S3C2410_LCON_STOPB (1<<2)
  39. #define S3C2410_LCON_IRM (1<<6)
  40. #define S3C2440_UCON_CLKMASK (3<<10)
  41. #define S3C2440_UCON_CLKSHIFT (10)
  42. #define S3C2440_UCON_PCLK (0<<10)
  43. #define S3C2440_UCON_UCLK (1<<10)
  44. #define S3C2440_UCON_PCLK2 (2<<10)
  45. #define S3C2440_UCON_FCLK (3<<10)
  46. #define S3C2443_UCON_EPLL (3<<10)
  47. #define S3C6400_UCON_CLKMASK (3<<10)
  48. #define S3C6400_UCON_CLKSHIFT (10)
  49. #define S3C6400_UCON_PCLK (0<<10)
  50. #define S3C6400_UCON_PCLK2 (2<<10)
  51. #define S3C6400_UCON_UCLK0 (1<<10)
  52. #define S3C6400_UCON_UCLK1 (3<<10)
  53. #define S3C2440_UCON2_FCLK_EN (1<<15)
  54. #define S3C2440_UCON0_DIVMASK (15 << 12)
  55. #define S3C2440_UCON1_DIVMASK (15 << 12)
  56. #define S3C2440_UCON2_DIVMASK (7 << 12)
  57. #define S3C2440_UCON_DIVSHIFT (12)
  58. #define S3C2412_UCON_CLKMASK (3<<10)
  59. #define S3C2412_UCON_CLKSHIFT (10)
  60. #define S3C2412_UCON_UCLK (1<<10)
  61. #define S3C2412_UCON_USYSCLK (3<<10)
  62. #define S3C2412_UCON_PCLK (0<<10)
  63. #define S3C2412_UCON_PCLK2 (2<<10)
  64. #define S3C2410_UCON_CLKMASK (1 << 10)
  65. #define S3C2410_UCON_CLKSHIFT (10)
  66. #define S3C2410_UCON_UCLK (1<<10)
  67. #define S3C2410_UCON_SBREAK (1<<4)
  68. #define S3C2410_UCON_TXILEVEL (1<<9)
  69. #define S3C2410_UCON_RXILEVEL (1<<8)
  70. #define S3C2410_UCON_TXIRQMODE (1<<2)
  71. #define S3C2410_UCON_RXIRQMODE (1<<0)
  72. #define S3C2410_UCON_RXFIFO_TOI (1<<7)
  73. #define S3C2443_UCON_RXERR_IRQEN (1<<6)
  74. #define S3C2443_UCON_LOOPBACK (1<<5)
  75. #define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
  76. S3C2410_UCON_RXILEVEL | \
  77. S3C2410_UCON_TXIRQMODE | \
  78. S3C2410_UCON_RXIRQMODE | \
  79. S3C2410_UCON_RXFIFO_TOI)
  80. #define S3C64XX_UCON_TXBURST_1 (0<<20)
  81. #define S3C64XX_UCON_TXBURST_4 (1<<20)
  82. #define S3C64XX_UCON_TXBURST_8 (2<<20)
  83. #define S3C64XX_UCON_TXBURST_16 (3<<20)
  84. #define S3C64XX_UCON_TXBURST_MASK (0xf<<20)
  85. #define S3C64XX_UCON_RXBURST_1 (0<<16)
  86. #define S3C64XX_UCON_RXBURST_4 (1<<16)
  87. #define S3C64XX_UCON_RXBURST_8 (2<<16)
  88. #define S3C64XX_UCON_RXBURST_16 (3<<16)
  89. #define S3C64XX_UCON_RXBURST_MASK (0xf<<16)
  90. #define S3C64XX_UCON_TIMEOUT_SHIFT (12)
  91. #define S3C64XX_UCON_TIMEOUT_MASK (0xf<<12)
  92. #define S3C64XX_UCON_EMPTYINT_EN (1<<11)
  93. #define S3C64XX_UCON_DMASUS_EN (1<<10)
  94. #define S3C64XX_UCON_TXINT_LEVEL (1<<9)
  95. #define S3C64XX_UCON_RXINT_LEVEL (1<<8)
  96. #define S3C64XX_UCON_TIMEOUT_EN (1<<7)
  97. #define S3C64XX_UCON_ERRINT_EN (1<<6)
  98. #define S3C64XX_UCON_TXMODE_DMA (2<<2)
  99. #define S3C64XX_UCON_TXMODE_CPU (1<<2)
  100. #define S3C64XX_UCON_TXMODE_MASK (3<<2)
  101. #define S3C64XX_UCON_RXMODE_DMA (2<<0)
  102. #define S3C64XX_UCON_RXMODE_CPU (1<<0)
  103. #define S3C64XX_UCON_RXMODE_MASK (3<<0)
  104. #define S3C2410_UFCON_FIFOMODE (1<<0)
  105. #define S3C2410_UFCON_TXTRIG0 (0<<6)
  106. #define S3C2410_UFCON_RXTRIG8 (1<<4)
  107. #define S3C2410_UFCON_RXTRIG12 (2<<4)
  108. /* S3C2440 FIFO trigger levels */
  109. #define S3C2440_UFCON_RXTRIG1 (0<<4)
  110. #define S3C2440_UFCON_RXTRIG8 (1<<4)
  111. #define S3C2440_UFCON_RXTRIG16 (2<<4)
  112. #define S3C2440_UFCON_RXTRIG32 (3<<4)
  113. #define S3C2440_UFCON_TXTRIG0 (0<<6)
  114. #define S3C2440_UFCON_TXTRIG16 (1<<6)
  115. #define S3C2440_UFCON_TXTRIG32 (2<<6)
  116. #define S3C2440_UFCON_TXTRIG48 (3<<6)
  117. #define S3C2410_UFCON_RESETBOTH (3<<1)
  118. #define S3C2410_UFCON_RESETTX (1<<2)
  119. #define S3C2410_UFCON_RESETRX (1<<1)
  120. #define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
  121. S3C2410_UFCON_TXTRIG0 | \
  122. S3C2410_UFCON_RXTRIG8 )
  123. #define S3C2410_UMCOM_AFC (1<<4)
  124. #define S3C2410_UMCOM_RTS_LOW (1<<0)
  125. #define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */
  126. #define S3C2412_UMCON_AFC_56 (1<<5)
  127. #define S3C2412_UMCON_AFC_48 (2<<5)
  128. #define S3C2412_UMCON_AFC_40 (3<<5)
  129. #define S3C2412_UMCON_AFC_32 (4<<5)
  130. #define S3C2412_UMCON_AFC_24 (5<<5)
  131. #define S3C2412_UMCON_AFC_16 (6<<5)
  132. #define S3C2412_UMCON_AFC_8 (7<<5)
  133. #define S3C2410_UFSTAT_TXFULL (1<<9)
  134. #define S3C2410_UFSTAT_RXFULL (1<<8)
  135. #define S3C2410_UFSTAT_TXMASK (15<<4)
  136. #define S3C2410_UFSTAT_TXSHIFT (4)
  137. #define S3C2410_UFSTAT_RXMASK (15<<0)
  138. #define S3C2410_UFSTAT_RXSHIFT (0)
  139. /* UFSTAT S3C2443 same as S3C2440 */
  140. #define S3C2440_UFSTAT_TXFULL (1<<14)
  141. #define S3C2440_UFSTAT_RXFULL (1<<6)
  142. #define S3C2440_UFSTAT_TXSHIFT (8)
  143. #define S3C2440_UFSTAT_RXSHIFT (0)
  144. #define S3C2440_UFSTAT_TXMASK (63<<8)
  145. #define S3C2440_UFSTAT_RXMASK (63)
  146. #define S3C2410_UTRSTAT_TIMEOUT (1<<3)
  147. #define S3C2410_UTRSTAT_TXE (1<<2)
  148. #define S3C2410_UTRSTAT_TXFE (1<<1)
  149. #define S3C2410_UTRSTAT_RXDR (1<<0)
  150. #define S3C2410_UERSTAT_OVERRUN (1<<0)
  151. #define S3C2410_UERSTAT_FRAME (1<<2)
  152. #define S3C2410_UERSTAT_BREAK (1<<3)
  153. #define S3C2443_UERSTAT_PARITY (1<<1)
  154. #define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \
  155. S3C2410_UERSTAT_FRAME | \
  156. S3C2410_UERSTAT_BREAK)
  157. #define S3C2410_UMSTAT_CTS (1<<0)
  158. #define S3C2410_UMSTAT_DeltaCTS (1<<2)
  159. #define S3C2443_DIVSLOT (0x2C)
  160. /* S3C64XX interrupt registers. */
  161. #define S3C64XX_UINTP 0x30
  162. #define S3C64XX_UINTSP 0x34
  163. #define S3C64XX_UINTM 0x38
  164. #define S3C64XX_UINTM_RXD (0)
  165. #define S3C64XX_UINTM_ERROR (1)
  166. #define S3C64XX_UINTM_TXD (2)
  167. #define S3C64XX_UINTM_RXD_MSK (1 << S3C64XX_UINTM_RXD)
  168. #define S3C64XX_UINTM_ERR_MSK (1 << S3C64XX_UINTM_ERROR)
  169. #define S3C64XX_UINTM_TXD_MSK (1 << S3C64XX_UINTM_TXD)
  170. /* Following are specific to S5PV210 */
  171. #define S5PV210_UCON_CLKMASK (1<<10)
  172. #define S5PV210_UCON_CLKSHIFT (10)
  173. #define S5PV210_UCON_PCLK (0<<10)
  174. #define S5PV210_UCON_UCLK (1<<10)
  175. #define S5PV210_UFCON_TXTRIG0 (0<<8)
  176. #define S5PV210_UFCON_TXTRIG4 (1<<8)
  177. #define S5PV210_UFCON_TXTRIG8 (2<<8)
  178. #define S5PV210_UFCON_TXTRIG16 (3<<8)
  179. #define S5PV210_UFCON_TXTRIG32 (4<<8)
  180. #define S5PV210_UFCON_TXTRIG64 (5<<8)
  181. #define S5PV210_UFCON_TXTRIG128 (6<<8)
  182. #define S5PV210_UFCON_TXTRIG256 (7<<8)
  183. #define S5PV210_UFCON_RXTRIG1 (0<<4)
  184. #define S5PV210_UFCON_RXTRIG4 (1<<4)
  185. #define S5PV210_UFCON_RXTRIG8 (2<<4)
  186. #define S5PV210_UFCON_RXTRIG16 (3<<4)
  187. #define S5PV210_UFCON_RXTRIG32 (4<<4)
  188. #define S5PV210_UFCON_RXTRIG64 (5<<4)
  189. #define S5PV210_UFCON_RXTRIG128 (6<<4)
  190. #define S5PV210_UFCON_RXTRIG256 (7<<4)
  191. #define S5PV210_UFSTAT_TXFULL (1<<24)
  192. #define S5PV210_UFSTAT_RXFULL (1<<8)
  193. #define S5PV210_UFSTAT_TXMASK (255<<16)
  194. #define S5PV210_UFSTAT_TXSHIFT (16)
  195. #define S5PV210_UFSTAT_RXMASK (255<<0)
  196. #define S5PV210_UFSTAT_RXSHIFT (0)
  197. #define S3C2410_UCON_CLKSEL0 (1 << 0)
  198. #define S3C2410_UCON_CLKSEL1 (1 << 1)
  199. #define S3C2410_UCON_CLKSEL2 (1 << 2)
  200. #define S3C2410_UCON_CLKSEL3 (1 << 3)
  201. /* Default values for s5pv210 UCON and UFCON uart registers */
  202. #define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
  203. S3C2410_UCON_RXILEVEL | \
  204. S3C2410_UCON_TXIRQMODE | \
  205. S3C2410_UCON_RXIRQMODE | \
  206. S3C2410_UCON_RXFIFO_TOI | \
  207. S3C2443_UCON_RXERR_IRQEN)
  208. #define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
  209. S5PV210_UFCON_TXTRIG4 | \
  210. S5PV210_UFCON_RXTRIG4)
  211. #ifndef __ASSEMBLY__
  212. #include <linux/serial_core.h>
  213. /* configuration structure for per-machine configurations for the
  214. * serial port
  215. *
  216. * the pointer is setup by the machine specific initialisation from the
  217. * arch/arm/mach-s3c2410/ directory.
  218. */
  219. struct s3c2410_uartcfg {
  220. unsigned char hwport; /* hardware port number */
  221. unsigned char unused;
  222. unsigned short flags;
  223. upf_t uart_flags; /* default uart flags */
  224. unsigned int clk_sel;
  225. unsigned int has_fracval;
  226. unsigned long ucon; /* value of ucon for port */
  227. unsigned long ulcon; /* value of ulcon for port */
  228. unsigned long ufcon; /* value of ufcon for port */
  229. };
  230. #endif /* __ASSEMBLY__ */
  231. #endif /* __ASM_ARM_REGS_SERIAL_H */