rtsx_usb.h 15 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /* Driver for Realtek RTS5139 USB card reader
  3. *
  4. * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
  5. *
  6. * Author:
  7. * Roger Tseng <rogerable@realtek.com>
  8. */
  9. #ifndef __RTSX_USB_H
  10. #define __RTSX_USB_H
  11. #include <linux/usb.h>
  12. /* related module names */
  13. #define RTSX_USB_SD_CARD 0
  14. #define RTSX_USB_MS_CARD 1
  15. /* endpoint numbers */
  16. #define EP_BULK_OUT 1
  17. #define EP_BULK_IN 2
  18. #define EP_INTR_IN 3
  19. /* USB vendor requests */
  20. #define RTSX_USB_REQ_REG_OP 0x00
  21. #define RTSX_USB_REQ_POLL 0x02
  22. /* miscellaneous parameters */
  23. #define MIN_DIV_N 60
  24. #define MAX_DIV_N 120
  25. #define MAX_PHASE 15
  26. #define RX_TUNING_CNT 3
  27. #define QFN24 0
  28. #define LQFP48 1
  29. #define CHECK_PKG(ucr, pkg) ((ucr)->package == (pkg))
  30. /* data structures */
  31. struct rtsx_ucr {
  32. u16 vendor_id;
  33. u16 product_id;
  34. int package;
  35. u8 ic_version;
  36. bool is_rts5179;
  37. unsigned int cur_clk;
  38. u8 *cmd_buf;
  39. unsigned int cmd_idx;
  40. u8 *rsp_buf;
  41. struct usb_device *pusb_dev;
  42. struct usb_interface *pusb_intf;
  43. struct usb_sg_request current_sg;
  44. unsigned char *iobuf;
  45. dma_addr_t iobuf_dma;
  46. struct timer_list sg_timer;
  47. struct mutex dev_mutex;
  48. };
  49. /* buffer size */
  50. #define IOBUF_SIZE 1024
  51. /* prototypes of exported functions */
  52. extern int rtsx_usb_get_card_status(struct rtsx_ucr *ucr, u16 *status);
  53. extern int rtsx_usb_read_register(struct rtsx_ucr *ucr, u16 addr, u8 *data);
  54. extern int rtsx_usb_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask,
  55. u8 data);
  56. extern int rtsx_usb_ep0_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask,
  57. u8 data);
  58. extern int rtsx_usb_ep0_read_register(struct rtsx_ucr *ucr, u16 addr,
  59. u8 *data);
  60. extern void rtsx_usb_add_cmd(struct rtsx_ucr *ucr, u8 cmd_type,
  61. u16 reg_addr, u8 mask, u8 data);
  62. extern int rtsx_usb_send_cmd(struct rtsx_ucr *ucr, u8 flag, int timeout);
  63. extern int rtsx_usb_get_rsp(struct rtsx_ucr *ucr, int rsp_len, int timeout);
  64. extern int rtsx_usb_transfer_data(struct rtsx_ucr *ucr, unsigned int pipe,
  65. void *buf, unsigned int len, int use_sg,
  66. unsigned int *act_len, int timeout);
  67. extern int rtsx_usb_read_ppbuf(struct rtsx_ucr *ucr, u8 *buf, int buf_len);
  68. extern int rtsx_usb_write_ppbuf(struct rtsx_ucr *ucr, u8 *buf, int buf_len);
  69. extern int rtsx_usb_switch_clock(struct rtsx_ucr *ucr, unsigned int card_clock,
  70. u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
  71. extern int rtsx_usb_card_exclusive_check(struct rtsx_ucr *ucr, int card);
  72. /* card status */
  73. #define SD_CD 0x01
  74. #define MS_CD 0x02
  75. #define XD_CD 0x04
  76. #define CD_MASK (SD_CD | MS_CD | XD_CD)
  77. #define SD_WP 0x08
  78. /* reader command field offset & parameters */
  79. #define READ_REG_CMD 0
  80. #define WRITE_REG_CMD 1
  81. #define CHECK_REG_CMD 2
  82. #define PACKET_TYPE 4
  83. #define CNT_H 5
  84. #define CNT_L 6
  85. #define STAGE_FLAG 7
  86. #define CMD_OFFSET 8
  87. #define SEQ_WRITE_DATA_OFFSET 12
  88. #define BATCH_CMD 0
  89. #define SEQ_READ 1
  90. #define SEQ_WRITE 2
  91. #define STAGE_R 0x01
  92. #define STAGE_DI 0x02
  93. #define STAGE_DO 0x04
  94. #define STAGE_MS_STATUS 0x08
  95. #define STAGE_XD_STATUS 0x10
  96. #define MODE_C 0x00
  97. #define MODE_CR (STAGE_R)
  98. #define MODE_CDIR (STAGE_R | STAGE_DI)
  99. #define MODE_CDOR (STAGE_R | STAGE_DO)
  100. #define EP0_OP_SHIFT 14
  101. #define EP0_READ_REG_CMD 2
  102. #define EP0_WRITE_REG_CMD 3
  103. #define rtsx_usb_cmd_hdr_tag(ucr) \
  104. do { \
  105. ucr->cmd_buf[0] = 'R'; \
  106. ucr->cmd_buf[1] = 'T'; \
  107. ucr->cmd_buf[2] = 'C'; \
  108. ucr->cmd_buf[3] = 'R'; \
  109. } while (0)
  110. static inline void rtsx_usb_init_cmd(struct rtsx_ucr *ucr)
  111. {
  112. rtsx_usb_cmd_hdr_tag(ucr);
  113. ucr->cmd_idx = 0;
  114. ucr->cmd_buf[PACKET_TYPE] = BATCH_CMD;
  115. }
  116. /* internal register address */
  117. #define FPDCTL 0xFC00
  118. #define SSC_DIV_N_0 0xFC07
  119. #define SSC_CTL1 0xFC09
  120. #define SSC_CTL2 0xFC0A
  121. #define CFG_MODE 0xFC0E
  122. #define CFG_MODE_1 0xFC0F
  123. #define RCCTL 0xFC14
  124. #define SOF_WDOG 0xFC28
  125. #define SYS_DUMMY0 0xFC30
  126. #define MS_BLKEND 0xFD30
  127. #define MS_READ_START 0xFD31
  128. #define MS_READ_COUNT 0xFD32
  129. #define MS_WRITE_START 0xFD33
  130. #define MS_WRITE_COUNT 0xFD34
  131. #define MS_COMMAND 0xFD35
  132. #define MS_OLD_BLOCK_0 0xFD36
  133. #define MS_OLD_BLOCK_1 0xFD37
  134. #define MS_NEW_BLOCK_0 0xFD38
  135. #define MS_NEW_BLOCK_1 0xFD39
  136. #define MS_LOG_BLOCK_0 0xFD3A
  137. #define MS_LOG_BLOCK_1 0xFD3B
  138. #define MS_BUS_WIDTH 0xFD3C
  139. #define MS_PAGE_START 0xFD3D
  140. #define MS_PAGE_LENGTH 0xFD3E
  141. #define MS_CFG 0xFD40
  142. #define MS_TPC 0xFD41
  143. #define MS_TRANS_CFG 0xFD42
  144. #define MS_TRANSFER 0xFD43
  145. #define MS_INT_REG 0xFD44
  146. #define MS_BYTE_CNT 0xFD45
  147. #define MS_SECTOR_CNT_L 0xFD46
  148. #define MS_SECTOR_CNT_H 0xFD47
  149. #define MS_DBUS_H 0xFD48
  150. #define CARD_DMA1_CTL 0xFD5C
  151. #define CARD_PULL_CTL1 0xFD60
  152. #define CARD_PULL_CTL2 0xFD61
  153. #define CARD_PULL_CTL3 0xFD62
  154. #define CARD_PULL_CTL4 0xFD63
  155. #define CARD_PULL_CTL5 0xFD64
  156. #define CARD_PULL_CTL6 0xFD65
  157. #define CARD_EXIST 0xFD6F
  158. #define CARD_INT_PEND 0xFD71
  159. #define LDO_POWER_CFG 0xFD7B
  160. #define SD_CFG1 0xFDA0
  161. #define SD_CFG2 0xFDA1
  162. #define SD_CFG3 0xFDA2
  163. #define SD_STAT1 0xFDA3
  164. #define SD_STAT2 0xFDA4
  165. #define SD_BUS_STAT 0xFDA5
  166. #define SD_PAD_CTL 0xFDA6
  167. #define SD_SAMPLE_POINT_CTL 0xFDA7
  168. #define SD_PUSH_POINT_CTL 0xFDA8
  169. #define SD_CMD0 0xFDA9
  170. #define SD_CMD1 0xFDAA
  171. #define SD_CMD2 0xFDAB
  172. #define SD_CMD3 0xFDAC
  173. #define SD_CMD4 0xFDAD
  174. #define SD_CMD5 0xFDAE
  175. #define SD_BYTE_CNT_L 0xFDAF
  176. #define SD_BYTE_CNT_H 0xFDB0
  177. #define SD_BLOCK_CNT_L 0xFDB1
  178. #define SD_BLOCK_CNT_H 0xFDB2
  179. #define SD_TRANSFER 0xFDB3
  180. #define SD_CMD_STATE 0xFDB5
  181. #define SD_DATA_STATE 0xFDB6
  182. #define SD_VPCLK0_CTL 0xFC2A
  183. #define SD_VPCLK1_CTL 0xFC2B
  184. #define SD_DCMPS0_CTL 0xFC2C
  185. #define SD_DCMPS1_CTL 0xFC2D
  186. #define CARD_DMA1_CTL 0xFD5C
  187. #define HW_VERSION 0xFC01
  188. #define SSC_CLK_FPGA_SEL 0xFC02
  189. #define CLK_DIV 0xFC03
  190. #define SFSM_ED 0xFC04
  191. #define CD_DEGLITCH_WIDTH 0xFC20
  192. #define CD_DEGLITCH_EN 0xFC21
  193. #define AUTO_DELINK_EN 0xFC23
  194. #define FPGA_PULL_CTL 0xFC1D
  195. #define CARD_CLK_SOURCE 0xFC2E
  196. #define CARD_SHARE_MODE 0xFD51
  197. #define CARD_DRIVE_SEL 0xFD52
  198. #define CARD_STOP 0xFD53
  199. #define CARD_OE 0xFD54
  200. #define CARD_AUTO_BLINK 0xFD55
  201. #define CARD_GPIO 0xFD56
  202. #define SD30_DRIVE_SEL 0xFD57
  203. #define CARD_DATA_SOURCE 0xFD5D
  204. #define CARD_SELECT 0xFD5E
  205. #define CARD_CLK_EN 0xFD79
  206. #define CARD_PWR_CTL 0xFD7A
  207. #define OCPCTL 0xFD80
  208. #define OCPPARA1 0xFD81
  209. #define OCPPARA2 0xFD82
  210. #define OCPSTAT 0xFD83
  211. #define HS_USB_STAT 0xFE01
  212. #define HS_VCONTROL 0xFE26
  213. #define HS_VSTAIN 0xFE27
  214. #define HS_VLOADM 0xFE28
  215. #define HS_VSTAOUT 0xFE29
  216. #define MC_IRQ 0xFF00
  217. #define MC_IRQEN 0xFF01
  218. #define MC_FIFO_CTL 0xFF02
  219. #define MC_FIFO_BC0 0xFF03
  220. #define MC_FIFO_BC1 0xFF04
  221. #define MC_FIFO_STAT 0xFF05
  222. #define MC_FIFO_MODE 0xFF06
  223. #define MC_FIFO_RD_PTR0 0xFF07
  224. #define MC_FIFO_RD_PTR1 0xFF08
  225. #define MC_DMA_CTL 0xFF10
  226. #define MC_DMA_TC0 0xFF11
  227. #define MC_DMA_TC1 0xFF12
  228. #define MC_DMA_TC2 0xFF13
  229. #define MC_DMA_TC3 0xFF14
  230. #define MC_DMA_RST 0xFF15
  231. #define RBUF_SIZE_MASK 0xFBFF
  232. #define RBUF_BASE 0xF000
  233. #define PPBUF_BASE1 0xF800
  234. #define PPBUF_BASE2 0xFA00
  235. /* internal register value macros */
  236. #define POWER_OFF 0x03
  237. #define PARTIAL_POWER_ON 0x02
  238. #define POWER_ON 0x00
  239. #define POWER_MASK 0x03
  240. #define LDO3318_PWR_MASK 0x0C
  241. #define LDO_ON 0x00
  242. #define LDO_SUSPEND 0x08
  243. #define LDO_OFF 0x0C
  244. #define DV3318_AUTO_PWR_OFF 0x10
  245. #define FORCE_LDO_POWERB 0x60
  246. /* LDO_POWER_CFG */
  247. #define TUNE_SD18_MASK 0x1C
  248. #define TUNE_SD18_1V7 0x00
  249. #define TUNE_SD18_1V8 (0x01 << 2)
  250. #define TUNE_SD18_1V9 (0x02 << 2)
  251. #define TUNE_SD18_2V0 (0x03 << 2)
  252. #define TUNE_SD18_2V7 (0x04 << 2)
  253. #define TUNE_SD18_2V8 (0x05 << 2)
  254. #define TUNE_SD18_2V9 (0x06 << 2)
  255. #define TUNE_SD18_3V3 (0x07 << 2)
  256. /* CLK_DIV */
  257. #define CLK_CHANGE 0x80
  258. #define CLK_DIV_1 0x00
  259. #define CLK_DIV_2 0x01
  260. #define CLK_DIV_4 0x02
  261. #define CLK_DIV_8 0x03
  262. #define SSC_POWER_MASK 0x01
  263. #define SSC_POWER_DOWN 0x01
  264. #define SSC_POWER_ON 0x00
  265. #define FPGA_VER 0x80
  266. #define HW_VER_MASK 0x0F
  267. #define EXTEND_DMA1_ASYNC_SIGNAL 0x02
  268. /* CFG_MODE*/
  269. #define XTAL_FREE 0x80
  270. #define CLK_MODE_MASK 0x03
  271. #define CLK_MODE_12M_XTAL 0x00
  272. #define CLK_MODE_NON_XTAL 0x01
  273. #define CLK_MODE_24M_OSC 0x02
  274. #define CLK_MODE_48M_OSC 0x03
  275. /* CFG_MODE_1*/
  276. #define RTS5179 0x02
  277. #define NYET_EN 0x01
  278. #define NYET_MSAK 0x01
  279. #define SD30_DRIVE_MASK 0x07
  280. #define SD20_DRIVE_MASK 0x03
  281. #define DISABLE_SD_CD 0x08
  282. #define DISABLE_MS_CD 0x10
  283. #define DISABLE_XD_CD 0x20
  284. #define SD_CD_DEGLITCH_EN 0x01
  285. #define MS_CD_DEGLITCH_EN 0x02
  286. #define XD_CD_DEGLITCH_EN 0x04
  287. #define CARD_SHARE_LQFP48 0x04
  288. #define CARD_SHARE_QFN24 0x00
  289. #define CARD_SHARE_LQFP_SEL 0x04
  290. #define CARD_SHARE_XD 0x00
  291. #define CARD_SHARE_SD 0x01
  292. #define CARD_SHARE_MS 0x02
  293. #define CARD_SHARE_MASK 0x03
  294. /* SD30_DRIVE_SEL */
  295. #define DRIVER_TYPE_A 0x05
  296. #define DRIVER_TYPE_B 0x03
  297. #define DRIVER_TYPE_C 0x02
  298. #define DRIVER_TYPE_D 0x01
  299. /* SD_BUS_STAT */
  300. #define SD_CLK_TOGGLE_EN 0x80
  301. #define SD_CLK_FORCE_STOP 0x40
  302. #define SD_DAT3_STATUS 0x10
  303. #define SD_DAT2_STATUS 0x08
  304. #define SD_DAT1_STATUS 0x04
  305. #define SD_DAT0_STATUS 0x02
  306. #define SD_CMD_STATUS 0x01
  307. /* SD_PAD_CTL */
  308. #define SD_IO_USING_1V8 0x80
  309. #define SD_IO_USING_3V3 0x7F
  310. #define TYPE_A_DRIVING 0x00
  311. #define TYPE_B_DRIVING 0x01
  312. #define TYPE_C_DRIVING 0x02
  313. #define TYPE_D_DRIVING 0x03
  314. /* CARD_CLK_EN */
  315. #define SD_CLK_EN 0x04
  316. #define MS_CLK_EN 0x08
  317. /* CARD_SELECT */
  318. #define SD_MOD_SEL 2
  319. #define MS_MOD_SEL 3
  320. /* CARD_SHARE_MODE */
  321. #define CARD_SHARE_LQFP48 0x04
  322. #define CARD_SHARE_QFN24 0x00
  323. #define CARD_SHARE_LQFP_SEL 0x04
  324. #define CARD_SHARE_XD 0x00
  325. #define CARD_SHARE_SD 0x01
  326. #define CARD_SHARE_MS 0x02
  327. #define CARD_SHARE_MASK 0x03
  328. /* SSC_CTL1 */
  329. #define SSC_RSTB 0x80
  330. #define SSC_8X_EN 0x40
  331. #define SSC_FIX_FRAC 0x20
  332. #define SSC_SEL_1M 0x00
  333. #define SSC_SEL_2M 0x08
  334. #define SSC_SEL_4M 0x10
  335. #define SSC_SEL_8M 0x18
  336. /* SSC_CTL2 */
  337. #define SSC_DEPTH_MASK 0x03
  338. #define SSC_DEPTH_DISALBE 0x00
  339. #define SSC_DEPTH_2M 0x01
  340. #define SSC_DEPTH_1M 0x02
  341. #define SSC_DEPTH_512K 0x03
  342. /* SD_VPCLK0_CTL */
  343. #define PHASE_CHANGE 0x80
  344. #define PHASE_NOT_RESET 0x40
  345. /* SD_TRANSFER */
  346. #define SD_TRANSFER_START 0x80
  347. #define SD_TRANSFER_END 0x40
  348. #define SD_STAT_IDLE 0x20
  349. #define SD_TRANSFER_ERR 0x10
  350. #define SD_TM_NORMAL_WRITE 0x00
  351. #define SD_TM_AUTO_WRITE_3 0x01
  352. #define SD_TM_AUTO_WRITE_4 0x02
  353. #define SD_TM_AUTO_READ_3 0x05
  354. #define SD_TM_AUTO_READ_4 0x06
  355. #define SD_TM_CMD_RSP 0x08
  356. #define SD_TM_AUTO_WRITE_1 0x09
  357. #define SD_TM_AUTO_WRITE_2 0x0A
  358. #define SD_TM_NORMAL_READ 0x0C
  359. #define SD_TM_AUTO_READ_1 0x0D
  360. #define SD_TM_AUTO_READ_2 0x0E
  361. #define SD_TM_AUTO_TUNING 0x0F
  362. /* SD_CFG1 */
  363. #define SD_CLK_DIVIDE_0 0x00
  364. #define SD_CLK_DIVIDE_256 0xC0
  365. #define SD_CLK_DIVIDE_128 0x80
  366. #define SD_CLK_DIVIDE_MASK 0xC0
  367. #define SD_BUS_WIDTH_1BIT 0x00
  368. #define SD_BUS_WIDTH_4BIT 0x01
  369. #define SD_BUS_WIDTH_8BIT 0x02
  370. #define SD_ASYNC_FIFO_RST 0x10
  371. #define SD_20_MODE 0x00
  372. #define SD_DDR_MODE 0x04
  373. #define SD_30_MODE 0x08
  374. /* SD_CFG2 */
  375. #define SD_CALCULATE_CRC7 0x00
  376. #define SD_NO_CALCULATE_CRC7 0x80
  377. #define SD_CHECK_CRC16 0x00
  378. #define SD_NO_CHECK_CRC16 0x40
  379. #define SD_WAIT_CRC_TO_EN 0x20
  380. #define SD_WAIT_BUSY_END 0x08
  381. #define SD_NO_WAIT_BUSY_END 0x00
  382. #define SD_CHECK_CRC7 0x00
  383. #define SD_NO_CHECK_CRC7 0x04
  384. #define SD_RSP_LEN_0 0x00
  385. #define SD_RSP_LEN_6 0x01
  386. #define SD_RSP_LEN_17 0x02
  387. #define SD_RSP_TYPE_R0 0x04
  388. #define SD_RSP_TYPE_R1 0x01
  389. #define SD_RSP_TYPE_R1b 0x09
  390. #define SD_RSP_TYPE_R2 0x02
  391. #define SD_RSP_TYPE_R3 0x05
  392. #define SD_RSP_TYPE_R4 0x05
  393. #define SD_RSP_TYPE_R5 0x01
  394. #define SD_RSP_TYPE_R6 0x01
  395. #define SD_RSP_TYPE_R7 0x01
  396. /* SD_STAT1 */
  397. #define SD_CRC7_ERR 0x80
  398. #define SD_CRC16_ERR 0x40
  399. #define SD_CRC_WRITE_ERR 0x20
  400. #define SD_CRC_WRITE_ERR_MASK 0x1C
  401. #define GET_CRC_TIME_OUT 0x02
  402. #define SD_TUNING_COMPARE_ERR 0x01
  403. /* SD_DATA_STATE */
  404. #define SD_DATA_IDLE 0x80
  405. /* CARD_DATA_SOURCE */
  406. #define PINGPONG_BUFFER 0x01
  407. #define RING_BUFFER 0x00
  408. /* CARD_OE */
  409. #define SD_OUTPUT_EN 0x04
  410. #define MS_OUTPUT_EN 0x08
  411. /* CARD_STOP */
  412. #define SD_STOP 0x04
  413. #define MS_STOP 0x08
  414. #define SD_CLR_ERR 0x40
  415. #define MS_CLR_ERR 0x80
  416. /* CARD_CLK_SOURCE */
  417. #define CRC_FIX_CLK (0x00 << 0)
  418. #define CRC_VAR_CLK0 (0x01 << 0)
  419. #define CRC_VAR_CLK1 (0x02 << 0)
  420. #define SD30_FIX_CLK (0x00 << 2)
  421. #define SD30_VAR_CLK0 (0x01 << 2)
  422. #define SD30_VAR_CLK1 (0x02 << 2)
  423. #define SAMPLE_FIX_CLK (0x00 << 4)
  424. #define SAMPLE_VAR_CLK0 (0x01 << 4)
  425. #define SAMPLE_VAR_CLK1 (0x02 << 4)
  426. /* SD_SAMPLE_POINT_CTL */
  427. #define DDR_FIX_RX_DAT 0x00
  428. #define DDR_VAR_RX_DAT 0x80
  429. #define DDR_FIX_RX_DAT_EDGE 0x00
  430. #define DDR_FIX_RX_DAT_14_DELAY 0x40
  431. #define DDR_FIX_RX_CMD 0x00
  432. #define DDR_VAR_RX_CMD 0x20
  433. #define DDR_FIX_RX_CMD_POS_EDGE 0x00
  434. #define DDR_FIX_RX_CMD_14_DELAY 0x10
  435. #define SD20_RX_POS_EDGE 0x00
  436. #define SD20_RX_14_DELAY 0x08
  437. #define SD20_RX_SEL_MASK 0x08
  438. /* SD_PUSH_POINT_CTL */
  439. #define DDR_FIX_TX_CMD_DAT 0x00
  440. #define DDR_VAR_TX_CMD_DAT 0x80
  441. #define DDR_FIX_TX_DAT_14_TSU 0x00
  442. #define DDR_FIX_TX_DAT_12_TSU 0x40
  443. #define DDR_FIX_TX_CMD_NEG_EDGE 0x00
  444. #define DDR_FIX_TX_CMD_14_AHEAD 0x20
  445. #define SD20_TX_NEG_EDGE 0x00
  446. #define SD20_TX_14_AHEAD 0x10
  447. #define SD20_TX_SEL_MASK 0x10
  448. #define DDR_VAR_SDCLK_POL_SWAP 0x01
  449. /* MS_CFG */
  450. #define SAMPLE_TIME_RISING 0x00
  451. #define SAMPLE_TIME_FALLING 0x80
  452. #define PUSH_TIME_DEFAULT 0x00
  453. #define PUSH_TIME_ODD 0x40
  454. #define NO_EXTEND_TOGGLE 0x00
  455. #define EXTEND_TOGGLE_CHK 0x20
  456. #define MS_BUS_WIDTH_1 0x00
  457. #define MS_BUS_WIDTH_4 0x10
  458. #define MS_BUS_WIDTH_8 0x18
  459. #define MS_2K_SECTOR_MODE 0x04
  460. #define MS_512_SECTOR_MODE 0x00
  461. #define MS_TOGGLE_TIMEOUT_EN 0x00
  462. #define MS_TOGGLE_TIMEOUT_DISEN 0x01
  463. #define MS_NO_CHECK_INT 0x02
  464. /* MS_TRANS_CFG */
  465. #define WAIT_INT 0x80
  466. #define NO_WAIT_INT 0x00
  467. #define NO_AUTO_READ_INT_REG 0x00
  468. #define AUTO_READ_INT_REG 0x40
  469. #define MS_CRC16_ERR 0x20
  470. #define MS_RDY_TIMEOUT 0x10
  471. #define MS_INT_CMDNK 0x08
  472. #define MS_INT_BREQ 0x04
  473. #define MS_INT_ERR 0x02
  474. #define MS_INT_CED 0x01
  475. /* MS_TRANSFER */
  476. #define MS_TRANSFER_START 0x80
  477. #define MS_TRANSFER_END 0x40
  478. #define MS_TRANSFER_ERR 0x20
  479. #define MS_BS_STATE 0x10
  480. #define MS_TM_READ_BYTES 0x00
  481. #define MS_TM_NORMAL_READ 0x01
  482. #define MS_TM_WRITE_BYTES 0x04
  483. #define MS_TM_NORMAL_WRITE 0x05
  484. #define MS_TM_AUTO_READ 0x08
  485. #define MS_TM_AUTO_WRITE 0x0C
  486. #define MS_TM_SET_CMD 0x06
  487. #define MS_TM_COPY_PAGE 0x07
  488. #define MS_TM_MULTI_READ 0x02
  489. #define MS_TM_MULTI_WRITE 0x03
  490. /* MC_FIFO_CTL */
  491. #define FIFO_FLUSH 0x01
  492. /* MC_DMA_RST */
  493. #define DMA_RESET 0x01
  494. /* MC_DMA_CTL */
  495. #define DMA_TC_EQ_0 0x80
  496. #define DMA_DIR_TO_CARD 0x00
  497. #define DMA_DIR_FROM_CARD 0x02
  498. #define DMA_EN 0x01
  499. #define DMA_128 (0 << 2)
  500. #define DMA_256 (1 << 2)
  501. #define DMA_512 (2 << 2)
  502. #define DMA_1024 (3 << 2)
  503. #define DMA_PACK_SIZE_MASK 0x0C
  504. /* CARD_INT_PEND */
  505. #define XD_INT 0x10
  506. #define MS_INT 0x08
  507. #define SD_INT 0x04
  508. /* LED operations*/
  509. static inline int rtsx_usb_turn_on_led(struct rtsx_ucr *ucr)
  510. {
  511. return rtsx_usb_ep0_write_register(ucr, CARD_GPIO, 0x03, 0x02);
  512. }
  513. static inline int rtsx_usb_turn_off_led(struct rtsx_ucr *ucr)
  514. {
  515. return rtsx_usb_ep0_write_register(ucr, CARD_GPIO, 0x03, 0x03);
  516. }
  517. /* HW error clearing */
  518. static inline void rtsx_usb_clear_fsm_err(struct rtsx_ucr *ucr)
  519. {
  520. rtsx_usb_ep0_write_register(ucr, SFSM_ED, 0xf8, 0xf8);
  521. }
  522. static inline void rtsx_usb_clear_dma_err(struct rtsx_ucr *ucr)
  523. {
  524. rtsx_usb_ep0_write_register(ucr, MC_FIFO_CTL,
  525. FIFO_FLUSH, FIFO_FLUSH);
  526. rtsx_usb_ep0_write_register(ucr, MC_DMA_RST, DMA_RESET, DMA_RESET);
  527. }
  528. #endif /* __RTS51139_H */