rtsx_pci.h 39 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /* Driver for Realtek PCI-Express card reader
  3. *
  4. * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
  5. *
  6. * Author:
  7. * Wei WANG <wei_wang@realsil.com.cn>
  8. */
  9. #ifndef __RTSX_PCI_H
  10. #define __RTSX_PCI_H
  11. #include <linux/sched.h>
  12. #include <linux/pci.h>
  13. #include <linux/rtsx_common.h>
  14. #define MAX_RW_REG_CNT 1024
  15. #define RTSX_HCBAR 0x00
  16. #define RTSX_HCBCTLR 0x04
  17. #define STOP_CMD (0x01 << 28)
  18. #define READ_REG_CMD 0
  19. #define WRITE_REG_CMD 1
  20. #define CHECK_REG_CMD 2
  21. #define RTSX_HDBAR 0x08
  22. #define RTSX_SG_INT 0x04
  23. #define RTSX_SG_END 0x02
  24. #define RTSX_SG_VALID 0x01
  25. #define RTSX_SG_NO_OP 0x00
  26. #define RTSX_SG_TRANS_DATA (0x02 << 4)
  27. #define RTSX_SG_LINK_DESC (0x03 << 4)
  28. #define RTSX_HDBCTLR 0x0C
  29. #define SDMA_MODE 0x00
  30. #define ADMA_MODE (0x02 << 26)
  31. #define STOP_DMA (0x01 << 28)
  32. #define TRIG_DMA (0x01 << 31)
  33. #define RTSX_HAIMR 0x10
  34. #define HAIMR_TRANS_START (0x01 << 31)
  35. #define HAIMR_READ 0x00
  36. #define HAIMR_WRITE (0x01 << 30)
  37. #define HAIMR_READ_START (HAIMR_TRANS_START | HAIMR_READ)
  38. #define HAIMR_WRITE_START (HAIMR_TRANS_START | HAIMR_WRITE)
  39. #define HAIMR_TRANS_END (HAIMR_TRANS_START)
  40. #define RTSX_BIPR 0x14
  41. #define CMD_DONE_INT (1 << 31)
  42. #define DATA_DONE_INT (1 << 30)
  43. #define TRANS_OK_INT (1 << 29)
  44. #define TRANS_FAIL_INT (1 << 28)
  45. #define XD_INT (1 << 27)
  46. #define MS_INT (1 << 26)
  47. #define SD_INT (1 << 25)
  48. #define GPIO0_INT (1 << 24)
  49. #define OC_INT (1 << 23)
  50. #define SD_WRITE_PROTECT (1 << 19)
  51. #define XD_EXIST (1 << 18)
  52. #define MS_EXIST (1 << 17)
  53. #define SD_EXIST (1 << 16)
  54. #define DELINK_INT GPIO0_INT
  55. #define MS_OC_INT (1 << 23)
  56. #define SD_OC_INT (1 << 22)
  57. #define CARD_INT (XD_INT | MS_INT | SD_INT)
  58. #define NEED_COMPLETE_INT (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT)
  59. #define RTSX_INT (CMD_DONE_INT | NEED_COMPLETE_INT | \
  60. CARD_INT | GPIO0_INT | OC_INT)
  61. #define CARD_EXIST (XD_EXIST | MS_EXIST | SD_EXIST)
  62. #define RTSX_BIER 0x18
  63. #define CMD_DONE_INT_EN (1 << 31)
  64. #define DATA_DONE_INT_EN (1 << 30)
  65. #define TRANS_OK_INT_EN (1 << 29)
  66. #define TRANS_FAIL_INT_EN (1 << 28)
  67. #define XD_INT_EN (1 << 27)
  68. #define MS_INT_EN (1 << 26)
  69. #define SD_INT_EN (1 << 25)
  70. #define GPIO0_INT_EN (1 << 24)
  71. #define OC_INT_EN (1 << 23)
  72. #define DELINK_INT_EN GPIO0_INT_EN
  73. #define MS_OC_INT_EN (1 << 23)
  74. #define SD_OC_INT_EN (1 << 22)
  75. /*
  76. * macros for easy use
  77. */
  78. #define rtsx_pci_writel(pcr, reg, value) \
  79. iowrite32(value, (pcr)->remap_addr + reg)
  80. #define rtsx_pci_readl(pcr, reg) \
  81. ioread32((pcr)->remap_addr + reg)
  82. #define rtsx_pci_writew(pcr, reg, value) \
  83. iowrite16(value, (pcr)->remap_addr + reg)
  84. #define rtsx_pci_readw(pcr, reg) \
  85. ioread16((pcr)->remap_addr + reg)
  86. #define rtsx_pci_writeb(pcr, reg, value) \
  87. iowrite8(value, (pcr)->remap_addr + reg)
  88. #define rtsx_pci_readb(pcr, reg) \
  89. ioread8((pcr)->remap_addr + reg)
  90. #define STATE_TRANS_NONE 0
  91. #define STATE_TRANS_CMD 1
  92. #define STATE_TRANS_BUF 2
  93. #define STATE_TRANS_SG 3
  94. #define TRANS_NOT_READY 0
  95. #define TRANS_RESULT_OK 1
  96. #define TRANS_RESULT_FAIL 2
  97. #define TRANS_NO_DEVICE 3
  98. #define RTSX_RESV_BUF_LEN 4096
  99. #define HOST_CMDS_BUF_LEN 1024
  100. #define HOST_SG_TBL_BUF_LEN (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)
  101. #define HOST_SG_TBL_ITEMS (HOST_SG_TBL_BUF_LEN / 8)
  102. #define MAX_SG_ITEM_LEN 0x80000
  103. #define HOST_TO_DEVICE 0
  104. #define DEVICE_TO_HOST 1
  105. #define OUTPUT_3V3 0
  106. #define OUTPUT_1V8 1
  107. #define RTSX_PHASE_MAX 32
  108. #define RX_TUNING_CNT 3
  109. #define MS_CFG 0xFD40
  110. #define SAMPLE_TIME_RISING 0x00
  111. #define SAMPLE_TIME_FALLING 0x80
  112. #define PUSH_TIME_DEFAULT 0x00
  113. #define PUSH_TIME_ODD 0x40
  114. #define NO_EXTEND_TOGGLE 0x00
  115. #define EXTEND_TOGGLE_CHK 0x20
  116. #define MS_BUS_WIDTH_1 0x00
  117. #define MS_BUS_WIDTH_4 0x10
  118. #define MS_BUS_WIDTH_8 0x18
  119. #define MS_2K_SECTOR_MODE 0x04
  120. #define MS_512_SECTOR_MODE 0x00
  121. #define MS_TOGGLE_TIMEOUT_EN 0x00
  122. #define MS_TOGGLE_TIMEOUT_DISEN 0x01
  123. #define MS_NO_CHECK_INT 0x02
  124. #define MS_TPC 0xFD41
  125. #define MS_TRANS_CFG 0xFD42
  126. #define WAIT_INT 0x80
  127. #define NO_WAIT_INT 0x00
  128. #define NO_AUTO_READ_INT_REG 0x00
  129. #define AUTO_READ_INT_REG 0x40
  130. #define MS_CRC16_ERR 0x20
  131. #define MS_RDY_TIMEOUT 0x10
  132. #define MS_INT_CMDNK 0x08
  133. #define MS_INT_BREQ 0x04
  134. #define MS_INT_ERR 0x02
  135. #define MS_INT_CED 0x01
  136. #define MS_TRANSFER 0xFD43
  137. #define MS_TRANSFER_START 0x80
  138. #define MS_TRANSFER_END 0x40
  139. #define MS_TRANSFER_ERR 0x20
  140. #define MS_BS_STATE 0x10
  141. #define MS_TM_READ_BYTES 0x00
  142. #define MS_TM_NORMAL_READ 0x01
  143. #define MS_TM_WRITE_BYTES 0x04
  144. #define MS_TM_NORMAL_WRITE 0x05
  145. #define MS_TM_AUTO_READ 0x08
  146. #define MS_TM_AUTO_WRITE 0x0C
  147. #define MS_INT_REG 0xFD44
  148. #define MS_BYTE_CNT 0xFD45
  149. #define MS_SECTOR_CNT_L 0xFD46
  150. #define MS_SECTOR_CNT_H 0xFD47
  151. #define MS_DBUS_H 0xFD48
  152. #define SD_CFG1 0xFDA0
  153. #define SD_CLK_DIVIDE_0 0x00
  154. #define SD_CLK_DIVIDE_256 0xC0
  155. #define SD_CLK_DIVIDE_128 0x80
  156. #define SD_BUS_WIDTH_1BIT 0x00
  157. #define SD_BUS_WIDTH_4BIT 0x01
  158. #define SD_BUS_WIDTH_8BIT 0x02
  159. #define SD_ASYNC_FIFO_NOT_RST 0x10
  160. #define SD_20_MODE 0x00
  161. #define SD_DDR_MODE 0x04
  162. #define SD_30_MODE 0x08
  163. #define SD_CLK_DIVIDE_MASK 0xC0
  164. #define SD_MODE_SELECT_MASK 0x0C
  165. #define SD_CFG2 0xFDA1
  166. #define SD_CALCULATE_CRC7 0x00
  167. #define SD_NO_CALCULATE_CRC7 0x80
  168. #define SD_CHECK_CRC16 0x00
  169. #define SD_NO_CHECK_CRC16 0x40
  170. #define SD_NO_CHECK_WAIT_CRC_TO 0x20
  171. #define SD_WAIT_BUSY_END 0x08
  172. #define SD_NO_WAIT_BUSY_END 0x00
  173. #define SD_CHECK_CRC7 0x00
  174. #define SD_NO_CHECK_CRC7 0x04
  175. #define SD_RSP_LEN_0 0x00
  176. #define SD_RSP_LEN_6 0x01
  177. #define SD_RSP_LEN_17 0x02
  178. #define SD_RSP_TYPE_R0 0x04
  179. #define SD_RSP_TYPE_R1 0x01
  180. #define SD_RSP_TYPE_R1b 0x09
  181. #define SD_RSP_TYPE_R2 0x02
  182. #define SD_RSP_TYPE_R3 0x05
  183. #define SD_RSP_TYPE_R4 0x05
  184. #define SD_RSP_TYPE_R5 0x01
  185. #define SD_RSP_TYPE_R6 0x01
  186. #define SD_RSP_TYPE_R7 0x01
  187. #define SD_CFG3 0xFDA2
  188. #define SD30_CLK_END_EN 0x10
  189. #define SD_RSP_80CLK_TIMEOUT_EN 0x01
  190. #define SD_STAT1 0xFDA3
  191. #define SD_CRC7_ERR 0x80
  192. #define SD_CRC16_ERR 0x40
  193. #define SD_CRC_WRITE_ERR 0x20
  194. #define SD_CRC_WRITE_ERR_MASK 0x1C
  195. #define GET_CRC_TIME_OUT 0x02
  196. #define SD_TUNING_COMPARE_ERR 0x01
  197. #define SD_STAT2 0xFDA4
  198. #define SD_RSP_80CLK_TIMEOUT 0x01
  199. #define SD_BUS_STAT 0xFDA5
  200. #define SD_CLK_TOGGLE_EN 0x80
  201. #define SD_CLK_FORCE_STOP 0x40
  202. #define SD_DAT3_STATUS 0x10
  203. #define SD_DAT2_STATUS 0x08
  204. #define SD_DAT1_STATUS 0x04
  205. #define SD_DAT0_STATUS 0x02
  206. #define SD_CMD_STATUS 0x01
  207. #define SD_PAD_CTL 0xFDA6
  208. #define SD_IO_USING_1V8 0x80
  209. #define SD_IO_USING_3V3 0x7F
  210. #define TYPE_A_DRIVING 0x00
  211. #define TYPE_B_DRIVING 0x01
  212. #define TYPE_C_DRIVING 0x02
  213. #define TYPE_D_DRIVING 0x03
  214. #define SD_SAMPLE_POINT_CTL 0xFDA7
  215. #define DDR_FIX_RX_DAT 0x00
  216. #define DDR_VAR_RX_DAT 0x80
  217. #define DDR_FIX_RX_DAT_EDGE 0x00
  218. #define DDR_FIX_RX_DAT_14_DELAY 0x40
  219. #define DDR_FIX_RX_CMD 0x00
  220. #define DDR_VAR_RX_CMD 0x20
  221. #define DDR_FIX_RX_CMD_POS_EDGE 0x00
  222. #define DDR_FIX_RX_CMD_14_DELAY 0x10
  223. #define SD20_RX_POS_EDGE 0x00
  224. #define SD20_RX_14_DELAY 0x08
  225. #define SD20_RX_SEL_MASK 0x08
  226. #define SD_PUSH_POINT_CTL 0xFDA8
  227. #define DDR_FIX_TX_CMD_DAT 0x00
  228. #define DDR_VAR_TX_CMD_DAT 0x80
  229. #define DDR_FIX_TX_DAT_14_TSU 0x00
  230. #define DDR_FIX_TX_DAT_12_TSU 0x40
  231. #define DDR_FIX_TX_CMD_NEG_EDGE 0x00
  232. #define DDR_FIX_TX_CMD_14_AHEAD 0x20
  233. #define SD20_TX_NEG_EDGE 0x00
  234. #define SD20_TX_14_AHEAD 0x10
  235. #define SD20_TX_SEL_MASK 0x10
  236. #define DDR_VAR_SDCLK_POL_SWAP 0x01
  237. #define SD_CMD0 0xFDA9
  238. #define SD_CMD_START 0x40
  239. #define SD_CMD1 0xFDAA
  240. #define SD_CMD2 0xFDAB
  241. #define SD_CMD3 0xFDAC
  242. #define SD_CMD4 0xFDAD
  243. #define SD_CMD5 0xFDAE
  244. #define SD_BYTE_CNT_L 0xFDAF
  245. #define SD_BYTE_CNT_H 0xFDB0
  246. #define SD_BLOCK_CNT_L 0xFDB1
  247. #define SD_BLOCK_CNT_H 0xFDB2
  248. #define SD_TRANSFER 0xFDB3
  249. #define SD_TRANSFER_START 0x80
  250. #define SD_TRANSFER_END 0x40
  251. #define SD_STAT_IDLE 0x20
  252. #define SD_TRANSFER_ERR 0x10
  253. #define SD_TM_NORMAL_WRITE 0x00
  254. #define SD_TM_AUTO_WRITE_3 0x01
  255. #define SD_TM_AUTO_WRITE_4 0x02
  256. #define SD_TM_AUTO_READ_3 0x05
  257. #define SD_TM_AUTO_READ_4 0x06
  258. #define SD_TM_CMD_RSP 0x08
  259. #define SD_TM_AUTO_WRITE_1 0x09
  260. #define SD_TM_AUTO_WRITE_2 0x0A
  261. #define SD_TM_NORMAL_READ 0x0C
  262. #define SD_TM_AUTO_READ_1 0x0D
  263. #define SD_TM_AUTO_READ_2 0x0E
  264. #define SD_TM_AUTO_TUNING 0x0F
  265. #define SD_CMD_STATE 0xFDB5
  266. #define SD_CMD_IDLE 0x80
  267. #define SD_DATA_STATE 0xFDB6
  268. #define SD_DATA_IDLE 0x80
  269. #define REG_SD_STOP_SDCLK_CFG 0xFDB8
  270. #define SD30_CLK_STOP_CFG_EN 0x04
  271. #define SD30_CLK_STOP_CFG1 0x02
  272. #define SD30_CLK_STOP_CFG0 0x01
  273. #define REG_PRE_RW_MODE 0xFD70
  274. #define EN_INFINITE_MODE 0x01
  275. #define REG_CRC_DUMMY_0 0xFD71
  276. #define CFG_SD_POW_AUTO_PD (1<<0)
  277. #define SRCTL 0xFC13
  278. #define DCM_DRP_CTL 0xFC23
  279. #define DCM_RESET 0x08
  280. #define DCM_LOCKED 0x04
  281. #define DCM_208M 0x00
  282. #define DCM_TX 0x01
  283. #define DCM_RX 0x02
  284. #define DCM_DRP_TRIG 0xFC24
  285. #define DRP_START 0x80
  286. #define DRP_DONE 0x40
  287. #define DCM_DRP_CFG 0xFC25
  288. #define DRP_WRITE 0x80
  289. #define DRP_READ 0x00
  290. #define DCM_WRITE_ADDRESS_50 0x50
  291. #define DCM_WRITE_ADDRESS_51 0x51
  292. #define DCM_READ_ADDRESS_00 0x00
  293. #define DCM_READ_ADDRESS_51 0x51
  294. #define DCM_DRP_WR_DATA_L 0xFC26
  295. #define DCM_DRP_WR_DATA_H 0xFC27
  296. #define DCM_DRP_RD_DATA_L 0xFC28
  297. #define DCM_DRP_RD_DATA_H 0xFC29
  298. #define SD_VPCLK0_CTL 0xFC2A
  299. #define SD_VPCLK1_CTL 0xFC2B
  300. #define PHASE_SELECT_MASK 0x1F
  301. #define SD_DCMPS0_CTL 0xFC2C
  302. #define SD_DCMPS1_CTL 0xFC2D
  303. #define SD_VPTX_CTL SD_VPCLK0_CTL
  304. #define SD_VPRX_CTL SD_VPCLK1_CTL
  305. #define PHASE_CHANGE 0x80
  306. #define PHASE_NOT_RESET 0x40
  307. #define SD_DCMPS_TX_CTL SD_DCMPS0_CTL
  308. #define SD_DCMPS_RX_CTL SD_DCMPS1_CTL
  309. #define DCMPS_CHANGE 0x80
  310. #define DCMPS_CHANGE_DONE 0x40
  311. #define DCMPS_ERROR 0x20
  312. #define DCMPS_CURRENT_PHASE 0x1F
  313. #define CARD_CLK_SOURCE 0xFC2E
  314. #define CRC_FIX_CLK (0x00 << 0)
  315. #define CRC_VAR_CLK0 (0x01 << 0)
  316. #define CRC_VAR_CLK1 (0x02 << 0)
  317. #define SD30_FIX_CLK (0x00 << 2)
  318. #define SD30_VAR_CLK0 (0x01 << 2)
  319. #define SD30_VAR_CLK1 (0x02 << 2)
  320. #define SAMPLE_FIX_CLK (0x00 << 4)
  321. #define SAMPLE_VAR_CLK0 (0x01 << 4)
  322. #define SAMPLE_VAR_CLK1 (0x02 << 4)
  323. #define CARD_PWR_CTL 0xFD50
  324. #define PMOS_STRG_MASK 0x10
  325. #define PMOS_STRG_800mA 0x10
  326. #define PMOS_STRG_400mA 0x00
  327. #define SD_POWER_OFF 0x03
  328. #define SD_PARTIAL_POWER_ON 0x01
  329. #define SD_POWER_ON 0x00
  330. #define SD_POWER_MASK 0x03
  331. #define MS_POWER_OFF 0x0C
  332. #define MS_PARTIAL_POWER_ON 0x04
  333. #define MS_POWER_ON 0x00
  334. #define MS_POWER_MASK 0x0C
  335. #define BPP_POWER_OFF 0x0F
  336. #define BPP_POWER_5_PERCENT_ON 0x0E
  337. #define BPP_POWER_10_PERCENT_ON 0x0C
  338. #define BPP_POWER_15_PERCENT_ON 0x08
  339. #define BPP_POWER_ON 0x00
  340. #define BPP_POWER_MASK 0x0F
  341. #define SD_VCC_PARTIAL_POWER_ON 0x02
  342. #define SD_VCC_POWER_ON 0x00
  343. #define CARD_CLK_SWITCH 0xFD51
  344. #define RTL8411B_PACKAGE_MODE 0xFD51
  345. #define CARD_SHARE_MODE 0xFD52
  346. #define CARD_SHARE_MASK 0x0F
  347. #define CARD_SHARE_MULTI_LUN 0x00
  348. #define CARD_SHARE_NORMAL 0x00
  349. #define CARD_SHARE_48_SD 0x04
  350. #define CARD_SHARE_48_MS 0x08
  351. #define CARD_SHARE_BAROSSA_SD 0x01
  352. #define CARD_SHARE_BAROSSA_MS 0x02
  353. #define CARD_DRIVE_SEL 0xFD53
  354. #define MS_DRIVE_8mA (0x01 << 6)
  355. #define MMC_DRIVE_8mA (0x01 << 4)
  356. #define XD_DRIVE_8mA (0x01 << 2)
  357. #define GPIO_DRIVE_8mA 0x01
  358. #define RTS5209_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\
  359. XD_DRIVE_8mA | GPIO_DRIVE_8mA)
  360. #define RTL8411_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\
  361. XD_DRIVE_8mA)
  362. #define RTSX_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | GPIO_DRIVE_8mA)
  363. #define CARD_STOP 0xFD54
  364. #define SPI_STOP 0x01
  365. #define XD_STOP 0x02
  366. #define SD_STOP 0x04
  367. #define MS_STOP 0x08
  368. #define SPI_CLR_ERR 0x10
  369. #define XD_CLR_ERR 0x20
  370. #define SD_CLR_ERR 0x40
  371. #define MS_CLR_ERR 0x80
  372. #define CARD_OE 0xFD55
  373. #define SD_OUTPUT_EN 0x04
  374. #define MS_OUTPUT_EN 0x08
  375. #define CARD_AUTO_BLINK 0xFD56
  376. #define CARD_GPIO_DIR 0xFD57
  377. #define CARD_GPIO 0xFD58
  378. #define CARD_DATA_SOURCE 0xFD5B
  379. #define PINGPONG_BUFFER 0x01
  380. #define RING_BUFFER 0x00
  381. #define SD30_CLK_DRIVE_SEL 0xFD5A
  382. #define DRIVER_TYPE_A 0x05
  383. #define DRIVER_TYPE_B 0x03
  384. #define DRIVER_TYPE_C 0x02
  385. #define DRIVER_TYPE_D 0x01
  386. #define CARD_SELECT 0xFD5C
  387. #define SD_MOD_SEL 2
  388. #define MS_MOD_SEL 3
  389. #define SD30_DRIVE_SEL 0xFD5E
  390. #define CFG_DRIVER_TYPE_A 0x02
  391. #define CFG_DRIVER_TYPE_B 0x03
  392. #define CFG_DRIVER_TYPE_C 0x01
  393. #define CFG_DRIVER_TYPE_D 0x00
  394. #define SD30_CMD_DRIVE_SEL 0xFD5E
  395. #define SD30_DAT_DRIVE_SEL 0xFD5F
  396. #define CARD_CLK_EN 0xFD69
  397. #define SD_CLK_EN 0x04
  398. #define MS_CLK_EN 0x08
  399. #define SD40_CLK_EN 0x10
  400. #define SDIO_CTRL 0xFD6B
  401. #define CD_PAD_CTL 0xFD73
  402. #define CD_DISABLE_MASK 0x07
  403. #define MS_CD_DISABLE 0x04
  404. #define SD_CD_DISABLE 0x02
  405. #define XD_CD_DISABLE 0x01
  406. #define CD_DISABLE 0x07
  407. #define CD_ENABLE 0x00
  408. #define MS_CD_EN_ONLY 0x03
  409. #define SD_CD_EN_ONLY 0x05
  410. #define XD_CD_EN_ONLY 0x06
  411. #define FORCE_CD_LOW_MASK 0x38
  412. #define FORCE_CD_XD_LOW 0x08
  413. #define FORCE_CD_SD_LOW 0x10
  414. #define FORCE_CD_MS_LOW 0x20
  415. #define CD_AUTO_DISABLE 0x40
  416. #define FPDCTL 0xFC00
  417. #define SSC_POWER_DOWN 0x01
  418. #define SD_OC_POWER_DOWN 0x02
  419. #define ALL_POWER_DOWN 0x03
  420. #define OC_POWER_DOWN 0x02
  421. #define PDINFO 0xFC01
  422. #define CLK_CTL 0xFC02
  423. #define CHANGE_CLK 0x01
  424. #define CLK_LOW_FREQ 0x01
  425. #define CLK_DIV 0xFC03
  426. #define CLK_DIV_1 0x01
  427. #define CLK_DIV_2 0x02
  428. #define CLK_DIV_4 0x03
  429. #define CLK_DIV_8 0x04
  430. #define CLK_SEL 0xFC04
  431. #define SSC_DIV_N_0 0xFC0F
  432. #define SSC_DIV_N_1 0xFC10
  433. #define SSC_CTL1 0xFC11
  434. #define SSC_RSTB 0x80
  435. #define SSC_8X_EN 0x40
  436. #define SSC_FIX_FRAC 0x20
  437. #define SSC_SEL_1M 0x00
  438. #define SSC_SEL_2M 0x08
  439. #define SSC_SEL_4M 0x10
  440. #define SSC_SEL_8M 0x18
  441. #define SSC_CTL2 0xFC12
  442. #define SSC_DEPTH_MASK 0x07
  443. #define SSC_DEPTH_DISALBE 0x00
  444. #define SSC_DEPTH_4M 0x01
  445. #define SSC_DEPTH_2M 0x02
  446. #define SSC_DEPTH_1M 0x03
  447. #define SSC_DEPTH_500K 0x04
  448. #define SSC_DEPTH_250K 0x05
  449. #define RCCTL 0xFC14
  450. #define FPGA_PULL_CTL 0xFC1D
  451. #define OLT_LED_CTL 0xFC1E
  452. #define LED_SHINE_MASK 0x08
  453. #define LED_SHINE_EN 0x08
  454. #define LED_SHINE_DISABLE 0x00
  455. #define GPIO_CTL 0xFC1F
  456. #define LDO_CTL 0xFC1E
  457. #define BPP_ASIC_1V7 0x00
  458. #define BPP_ASIC_1V8 0x01
  459. #define BPP_ASIC_1V9 0x02
  460. #define BPP_ASIC_2V0 0x03
  461. #define BPP_ASIC_2V7 0x04
  462. #define BPP_ASIC_2V8 0x05
  463. #define BPP_ASIC_3V2 0x06
  464. #define BPP_ASIC_3V3 0x07
  465. #define BPP_REG_TUNED18 0x07
  466. #define BPP_TUNED18_SHIFT_8402 5
  467. #define BPP_TUNED18_SHIFT_8411 4
  468. #define BPP_PAD_MASK 0x04
  469. #define BPP_PAD_3V3 0x04
  470. #define BPP_PAD_1V8 0x00
  471. #define BPP_LDO_POWB 0x03
  472. #define BPP_LDO_ON 0x00
  473. #define BPP_LDO_SUSPEND 0x02
  474. #define BPP_LDO_OFF 0x03
  475. #define EFUSE_CTL 0xFC30
  476. #define EFUSE_ADD 0xFC31
  477. #define SYS_VER 0xFC32
  478. #define EFUSE_DATAL 0xFC34
  479. #define EFUSE_DATAH 0xFC35
  480. #define CARD_PULL_CTL1 0xFD60
  481. #define CARD_PULL_CTL2 0xFD61
  482. #define CARD_PULL_CTL3 0xFD62
  483. #define CARD_PULL_CTL4 0xFD63
  484. #define CARD_PULL_CTL5 0xFD64
  485. #define CARD_PULL_CTL6 0xFD65
  486. /* PCI Express Related Registers */
  487. #define IRQEN0 0xFE20
  488. #define IRQSTAT0 0xFE21
  489. #define DMA_DONE_INT 0x80
  490. #define SUSPEND_INT 0x40
  491. #define LINK_RDY_INT 0x20
  492. #define LINK_DOWN_INT 0x10
  493. #define IRQEN1 0xFE22
  494. #define IRQSTAT1 0xFE23
  495. #define TLPRIEN 0xFE24
  496. #define TLPRISTAT 0xFE25
  497. #define TLPTIEN 0xFE26
  498. #define TLPTISTAT 0xFE27
  499. #define DMATC0 0xFE28
  500. #define DMATC1 0xFE29
  501. #define DMATC2 0xFE2A
  502. #define DMATC3 0xFE2B
  503. #define DMACTL 0xFE2C
  504. #define DMA_RST 0x80
  505. #define DMA_BUSY 0x04
  506. #define DMA_DIR_TO_CARD 0x00
  507. #define DMA_DIR_FROM_CARD 0x02
  508. #define DMA_EN 0x01
  509. #define DMA_128 (0 << 4)
  510. #define DMA_256 (1 << 4)
  511. #define DMA_512 (2 << 4)
  512. #define DMA_1024 (3 << 4)
  513. #define DMA_PACK_SIZE_MASK 0x30
  514. #define BCTL 0xFE2D
  515. #define RBBC0 0xFE2E
  516. #define RBBC1 0xFE2F
  517. #define RBDAT 0xFE30
  518. #define RBCTL 0xFE34
  519. #define U_AUTO_DMA_EN_MASK 0x20
  520. #define U_AUTO_DMA_DISABLE 0x00
  521. #define RB_FLUSH 0x80
  522. #define CFGADDR0 0xFE35
  523. #define CFGADDR1 0xFE36
  524. #define CFGDATA0 0xFE37
  525. #define CFGDATA1 0xFE38
  526. #define CFGDATA2 0xFE39
  527. #define CFGDATA3 0xFE3A
  528. #define CFGRWCTL 0xFE3B
  529. #define PHYRWCTL 0xFE3C
  530. #define PHYDATA0 0xFE3D
  531. #define PHYDATA1 0xFE3E
  532. #define PHYADDR 0xFE3F
  533. #define MSGRXDATA0 0xFE40
  534. #define MSGRXDATA1 0xFE41
  535. #define MSGRXDATA2 0xFE42
  536. #define MSGRXDATA3 0xFE43
  537. #define MSGTXDATA0 0xFE44
  538. #define MSGTXDATA1 0xFE45
  539. #define MSGTXDATA2 0xFE46
  540. #define MSGTXDATA3 0xFE47
  541. #define MSGTXCTL 0xFE48
  542. #define LTR_CTL 0xFE4A
  543. #define LTR_TX_EN_MASK BIT(7)
  544. #define LTR_TX_EN_1 BIT(7)
  545. #define LTR_TX_EN_0 0
  546. #define LTR_LATENCY_MODE_MASK BIT(6)
  547. #define LTR_LATENCY_MODE_HW 0
  548. #define LTR_LATENCY_MODE_SW BIT(6)
  549. #define OBFF_CFG 0xFE4C
  550. #define OBFF_EN_MASK 0x03
  551. #define OBFF_DISABLE 0x00
  552. #define CDRESUMECTL 0xFE52
  553. #define WAKE_SEL_CTL 0xFE54
  554. #define PCLK_CTL 0xFE55
  555. #define PCLK_MODE_SEL 0x20
  556. #define PME_FORCE_CTL 0xFE56
  557. #define ASPM_FORCE_CTL 0xFE57
  558. #define FORCE_ASPM_CTL0 0x10
  559. #define FORCE_ASPM_CTL1 0x20
  560. #define FORCE_ASPM_VAL_MASK 0x03
  561. #define FORCE_ASPM_L1_EN 0x02
  562. #define FORCE_ASPM_L0_EN 0x01
  563. #define FORCE_ASPM_NO_ASPM 0x00
  564. #define PM_CLK_FORCE_CTL 0xFE58
  565. #define CLK_PM_EN 0x01
  566. #define FUNC_FORCE_CTL 0xFE59
  567. #define FUNC_FORCE_UPME_XMT_DBG 0x02
  568. #define PERST_GLITCH_WIDTH 0xFE5C
  569. #define CHANGE_LINK_STATE 0xFE5B
  570. #define RESET_LOAD_REG 0xFE5E
  571. #define EFUSE_CONTENT 0xFE5F
  572. #define HOST_SLEEP_STATE 0xFE60
  573. #define HOST_ENTER_S1 1
  574. #define HOST_ENTER_S3 2
  575. #define SDIO_CFG 0xFE70
  576. #define PM_EVENT_DEBUG 0xFE71
  577. #define PME_DEBUG_0 0x08
  578. #define NFTS_TX_CTRL 0xFE72
  579. #define PWR_GATE_CTRL 0xFE75
  580. #define PWR_GATE_EN 0x01
  581. #define LDO3318_PWR_MASK 0x06
  582. #define LDO_ON 0x00
  583. #define LDO_SUSPEND 0x04
  584. #define LDO_OFF 0x06
  585. #define PWD_SUSPEND_EN 0xFE76
  586. #define LDO_PWR_SEL 0xFE78
  587. #define L1SUB_CONFIG1 0xFE8D
  588. #define AUX_CLK_ACTIVE_SEL_MASK 0x01
  589. #define MAC_CKSW_DONE 0x00
  590. #define L1SUB_CONFIG2 0xFE8E
  591. #define L1SUB_AUTO_CFG 0x02
  592. #define L1SUB_CONFIG3 0xFE8F
  593. #define L1OFF_MBIAS2_EN_5250 BIT(7)
  594. #define DUMMY_REG_RESET_0 0xFE90
  595. #define IC_VERSION_MASK 0x0F
  596. #define REG_VREF 0xFE97
  597. #define PWD_SUSPND_EN 0x10
  598. #define RTS5260_DMA_RST_CTL_0 0xFEBF
  599. #define RTS5260_DMA_RST 0x80
  600. #define RTS5260_ADMA3_RST 0x40
  601. #define AUTOLOAD_CFG_BASE 0xFF00
  602. #define RELINK_TIME_MASK 0x01
  603. #define PETXCFG 0xFF03
  604. #define FORCE_CLKREQ_DELINK_MASK BIT(7)
  605. #define FORCE_CLKREQ_LOW 0x80
  606. #define FORCE_CLKREQ_HIGH 0x00
  607. #define PM_CTRL1 0xFF44
  608. #define CD_RESUME_EN_MASK 0xF0
  609. #define PM_CTRL2 0xFF45
  610. #define PM_CTRL3 0xFF46
  611. #define SDIO_SEND_PME_EN 0x80
  612. #define FORCE_RC_MODE_ON 0x40
  613. #define FORCE_RX50_LINK_ON 0x20
  614. #define D3_DELINK_MODE_EN 0x10
  615. #define USE_PESRTB_CTL_DELINK 0x08
  616. #define DELAY_PIN_WAKE 0x04
  617. #define RESET_PIN_WAKE 0x02
  618. #define PM_WAKE_EN 0x01
  619. #define PM_CTRL4 0xFF47
  620. #define REG_CFG_OOBS_OFF_TIMER 0xFEA6
  621. #define REG_CFG_OOBS_ON_TIMER 0xFEA7
  622. #define REG_CFG_VCM_ON_TIMER 0xFEA8
  623. #define REG_CFG_OOBS_POLLING 0xFEA9
  624. /* Memory mapping */
  625. #define SRAM_BASE 0xE600
  626. #define RBUF_BASE 0xF400
  627. #define PPBUF_BASE1 0xF800
  628. #define PPBUF_BASE2 0xFA00
  629. #define IMAGE_FLAG_ADDR0 0xCE80
  630. #define IMAGE_FLAG_ADDR1 0xCE81
  631. #define RREF_CFG 0xFF6C
  632. #define RREF_VBGSEL_MASK 0x38
  633. #define RREF_VBGSEL_1V25 0x28
  634. #define OOBS_CONFIG 0xFF6E
  635. #define OOBS_AUTOK_DIS 0x80
  636. #define OOBS_VAL_MASK 0x1F
  637. #define LDO_DV18_CFG 0xFF70
  638. #define LDO_DV18_SR_MASK 0xC0
  639. #define LDO_DV18_SR_DF 0x40
  640. #define DV331812_MASK 0x70
  641. #define DV331812_33 0x70
  642. #define DV331812_17 0x30
  643. #define LDO_CONFIG2 0xFF71
  644. #define LDO_D3318_MASK 0x07
  645. #define LDO_D3318_33V 0x07
  646. #define LDO_D3318_18V 0x02
  647. #define DV331812_VDD1 0x04
  648. #define DV331812_POWERON 0x08
  649. #define DV331812_POWEROFF 0x00
  650. #define LDO_VCC_CFG0 0xFF72
  651. #define LDO_VCC_LMTVTH_MASK 0x30
  652. #define LDO_VCC_LMTVTH_2A 0x10
  653. /*RTS5260*/
  654. #define RTS5260_DVCC_TUNE_MASK 0x70
  655. #define RTS5260_DVCC_33 0x70
  656. #define LDO_VCC_CFG1 0xFF73
  657. #define LDO_VCC_REF_TUNE_MASK 0x30
  658. #define LDO_VCC_REF_1V2 0x20
  659. #define LDO_VCC_TUNE_MASK 0x07
  660. #define LDO_VCC_1V8 0x04
  661. #define LDO_VCC_3V3 0x07
  662. #define LDO_VCC_LMT_EN 0x08
  663. /*RTS5260*/
  664. #define LDO_POW_SDVDD1_MASK 0x08
  665. #define LDO_POW_SDVDD1_ON 0x08
  666. #define LDO_POW_SDVDD1_OFF 0x00
  667. #define LDO_VIO_CFG 0xFF75
  668. #define LDO_VIO_SR_MASK 0xC0
  669. #define LDO_VIO_SR_DF 0x40
  670. #define LDO_VIO_REF_TUNE_MASK 0x30
  671. #define LDO_VIO_REF_1V2 0x20
  672. #define LDO_VIO_TUNE_MASK 0x07
  673. #define LDO_VIO_1V7 0x03
  674. #define LDO_VIO_1V8 0x04
  675. #define LDO_VIO_3V3 0x07
  676. #define LDO_DV12S_CFG 0xFF76
  677. #define LDO_REF12_TUNE_MASK 0x18
  678. #define LDO_REF12_TUNE_DF 0x10
  679. #define LDO_D12_TUNE_MASK 0x07
  680. #define LDO_D12_TUNE_DF 0x04
  681. #define LDO_AV12S_CFG 0xFF77
  682. #define LDO_AV12S_TUNE_MASK 0x07
  683. #define LDO_AV12S_TUNE_DF 0x04
  684. #define SD40_LDO_CTL1 0xFE7D
  685. #define SD40_VIO_TUNE_MASK 0x70
  686. #define SD40_VIO_TUNE_1V7 0x30
  687. #define SD_VIO_LDO_1V8 0x40
  688. #define SD_VIO_LDO_3V3 0x70
  689. #define RTS5260_AUTOLOAD_CFG4 0xFF7F
  690. #define RTS5260_MIMO_DISABLE 0x8A
  691. #define RTS5260_REG_GPIO_CTL0 0xFC1A
  692. #define RTS5260_REG_GPIO_MASK 0x01
  693. #define RTS5260_REG_GPIO_ON 0x01
  694. #define RTS5260_REG_GPIO_OFF 0x00
  695. #define PWR_GLOBAL_CTRL 0xF200
  696. #define PCIE_L1_2_EN 0x0C
  697. #define PCIE_L1_1_EN 0x0A
  698. #define PCIE_L1_0_EN 0x09
  699. #define PWR_FE_CTL 0xF201
  700. #define PCIE_L1_2_PD_FE_EN 0x0C
  701. #define PCIE_L1_1_PD_FE_EN 0x0A
  702. #define PCIE_L1_0_PD_FE_EN 0x09
  703. #define CFG_PCIE_APHY_OFF_0 0xF204
  704. #define CFG_PCIE_APHY_OFF_0_DEFAULT 0xBF
  705. #define CFG_PCIE_APHY_OFF_1 0xF205
  706. #define CFG_PCIE_APHY_OFF_1_DEFAULT 0xFF
  707. #define CFG_PCIE_APHY_OFF_2 0xF206
  708. #define CFG_PCIE_APHY_OFF_2_DEFAULT 0x01
  709. #define CFG_PCIE_APHY_OFF_3 0xF207
  710. #define CFG_PCIE_APHY_OFF_3_DEFAULT 0x00
  711. #define CFG_L1_0_PCIE_MAC_RET_VALUE 0xF20C
  712. #define CFG_L1_0_PCIE_DPHY_RET_VALUE 0xF20E
  713. #define CFG_L1_0_SYS_RET_VALUE 0xF210
  714. #define CFG_L1_0_CRC_MISC_RET_VALUE 0xF212
  715. #define CFG_L1_0_CRC_SD30_RET_VALUE 0xF214
  716. #define CFG_L1_0_CRC_SD40_RET_VALUE 0xF216
  717. #define CFG_LP_FPWM_VALUE 0xF219
  718. #define CFG_LP_FPWM_VALUE_DEFAULT 0x18
  719. #define PWC_CDR 0xF253
  720. #define PWC_CDR_DEFAULT 0x03
  721. #define CFG_L1_0_RET_VALUE_DEFAULT 0x1B
  722. #define CFG_L1_0_CRC_MISC_RET_VALUE_DEFAULT 0x0C
  723. /* OCPCTL */
  724. #define SD_DETECT_EN 0x08
  725. #define SD_OCP_INT_EN 0x04
  726. #define SD_OCP_INT_CLR 0x02
  727. #define SD_OC_CLR 0x01
  728. #define SDVIO_DETECT_EN (1 << 7)
  729. #define SDVIO_OCP_INT_EN (1 << 6)
  730. #define SDVIO_OCP_INT_CLR (1 << 5)
  731. #define SDVIO_OC_CLR (1 << 4)
  732. /* OCPSTAT */
  733. #define SD_OCP_DETECT 0x08
  734. #define SD_OC_NOW 0x04
  735. #define SD_OC_EVER 0x02
  736. #define SDVIO_OC_NOW (1 << 6)
  737. #define SDVIO_OC_EVER (1 << 5)
  738. #define REG_OCPCTL 0xFD6A
  739. #define REG_OCPSTAT 0xFD6E
  740. #define REG_OCPGLITCH 0xFD6C
  741. #define REG_OCPPARA1 0xFD6B
  742. #define REG_OCPPARA2 0xFD6D
  743. /* rts5260 DV3318 OCP-related registers */
  744. #define REG_DV3318_OCPCTL 0xFD89
  745. #define DV3318_OCP_TIME_MASK 0xF0
  746. #define DV3318_DETECT_EN 0x08
  747. #define DV3318_OCP_INT_EN 0x04
  748. #define DV3318_OCP_INT_CLR 0x02
  749. #define DV3318_OCP_CLR 0x01
  750. #define REG_DV3318_OCPSTAT 0xFD8A
  751. #define DV3318_OCP_GlITCH_TIME_MASK 0xF0
  752. #define DV3318_OCP_DETECT 0x08
  753. #define DV3318_OCP_NOW 0x04
  754. #define DV3318_OCP_EVER 0x02
  755. #define SD_OCP_GLITCH_MASK 0x0F
  756. /* OCPPARA1 */
  757. #define SDVIO_OCP_TIME_60 0x00
  758. #define SDVIO_OCP_TIME_100 0x10
  759. #define SDVIO_OCP_TIME_200 0x20
  760. #define SDVIO_OCP_TIME_400 0x30
  761. #define SDVIO_OCP_TIME_600 0x40
  762. #define SDVIO_OCP_TIME_800 0x50
  763. #define SDVIO_OCP_TIME_1100 0x60
  764. #define SDVIO_OCP_TIME_MASK 0x70
  765. #define SD_OCP_TIME_60 0x00
  766. #define SD_OCP_TIME_100 0x01
  767. #define SD_OCP_TIME_200 0x02
  768. #define SD_OCP_TIME_400 0x03
  769. #define SD_OCP_TIME_600 0x04
  770. #define SD_OCP_TIME_800 0x05
  771. #define SD_OCP_TIME_1100 0x06
  772. #define SD_OCP_TIME_MASK 0x07
  773. /* OCPPARA2 */
  774. #define SDVIO_OCP_THD_190 0x00
  775. #define SDVIO_OCP_THD_250 0x10
  776. #define SDVIO_OCP_THD_320 0x20
  777. #define SDVIO_OCP_THD_380 0x30
  778. #define SDVIO_OCP_THD_440 0x40
  779. #define SDVIO_OCP_THD_500 0x50
  780. #define SDVIO_OCP_THD_570 0x60
  781. #define SDVIO_OCP_THD_630 0x70
  782. #define SDVIO_OCP_THD_MASK 0x70
  783. #define SD_OCP_THD_450 0x00
  784. #define SD_OCP_THD_550 0x01
  785. #define SD_OCP_THD_650 0x02
  786. #define SD_OCP_THD_750 0x03
  787. #define SD_OCP_THD_850 0x04
  788. #define SD_OCP_THD_950 0x05
  789. #define SD_OCP_THD_1050 0x06
  790. #define SD_OCP_THD_1150 0x07
  791. #define SD_OCP_THD_MASK 0x07
  792. #define SDVIO_OCP_GLITCH_MASK 0xF0
  793. #define SDVIO_OCP_GLITCH_NONE 0x00
  794. #define SDVIO_OCP_GLITCH_50U 0x10
  795. #define SDVIO_OCP_GLITCH_100U 0x20
  796. #define SDVIO_OCP_GLITCH_200U 0x30
  797. #define SDVIO_OCP_GLITCH_600U 0x40
  798. #define SDVIO_OCP_GLITCH_800U 0x50
  799. #define SDVIO_OCP_GLITCH_1M 0x60
  800. #define SDVIO_OCP_GLITCH_2M 0x70
  801. #define SDVIO_OCP_GLITCH_3M 0x80
  802. #define SDVIO_OCP_GLITCH_4M 0x90
  803. #define SDVIO_OCP_GLIVCH_5M 0xA0
  804. #define SDVIO_OCP_GLITCH_6M 0xB0
  805. #define SDVIO_OCP_GLITCH_7M 0xC0
  806. #define SDVIO_OCP_GLITCH_8M 0xD0
  807. #define SDVIO_OCP_GLITCH_9M 0xE0
  808. #define SDVIO_OCP_GLITCH_10M 0xF0
  809. #define SD_OCP_GLITCH_MASK 0x0F
  810. #define SD_OCP_GLITCH_NONE 0x00
  811. #define SD_OCP_GLITCH_50U 0x01
  812. #define SD_OCP_GLITCH_100U 0x02
  813. #define SD_OCP_GLITCH_200U 0x03
  814. #define SD_OCP_GLITCH_600U 0x04
  815. #define SD_OCP_GLITCH_800U 0x05
  816. #define SD_OCP_GLITCH_1M 0x06
  817. #define SD_OCP_GLITCH_2M 0x07
  818. #define SD_OCP_GLITCH_3M 0x08
  819. #define SD_OCP_GLITCH_4M 0x09
  820. #define SD_OCP_GLIVCH_5M 0x0A
  821. #define SD_OCP_GLITCH_6M 0x0B
  822. #define SD_OCP_GLITCH_7M 0x0C
  823. #define SD_OCP_GLITCH_8M 0x0D
  824. #define SD_OCP_GLITCH_9M 0x0E
  825. #define SD_OCP_GLITCH_10M 0x0F
  826. /* Phy register */
  827. #define PHY_PCR 0x00
  828. #define PHY_PCR_FORCE_CODE 0xB000
  829. #define PHY_PCR_OOBS_CALI_50 0x0800
  830. #define PHY_PCR_OOBS_VCM_08 0x0200
  831. #define PHY_PCR_OOBS_SEN_90 0x0040
  832. #define PHY_PCR_RSSI_EN 0x0002
  833. #define PHY_PCR_RX10K 0x0001
  834. #define PHY_RCR0 0x01
  835. #define PHY_RCR1 0x02
  836. #define PHY_RCR1_ADP_TIME_4 0x0400
  837. #define PHY_RCR1_VCO_COARSE 0x001F
  838. #define PHY_RCR1_INIT_27S 0x0A1F
  839. #define PHY_SSCCR2 0x02
  840. #define PHY_SSCCR2_PLL_NCODE 0x0A00
  841. #define PHY_SSCCR2_TIME0 0x001C
  842. #define PHY_SSCCR2_TIME2_WIDTH 0x0003
  843. #define PHY_RCR2 0x03
  844. #define PHY_RCR2_EMPHASE_EN 0x8000
  845. #define PHY_RCR2_NADJR 0x4000
  846. #define PHY_RCR2_CDR_SR_2 0x0100
  847. #define PHY_RCR2_FREQSEL_12 0x0040
  848. #define PHY_RCR2_CDR_SC_12P 0x0010
  849. #define PHY_RCR2_CALIB_LATE 0x0002
  850. #define PHY_RCR2_INIT_27S 0xC152
  851. #define PHY_SSCCR3 0x03
  852. #define PHY_SSCCR3_STEP_IN 0x2740
  853. #define PHY_SSCCR3_CHECK_DELAY 0x0008
  854. #define _PHY_ANA03 0x03
  855. #define _PHY_ANA03_TIMER_MAX 0x2700
  856. #define _PHY_ANA03_OOBS_DEB_EN 0x0040
  857. #define _PHY_CMU_DEBUG_EN 0x0008
  858. #define PHY_RTCR 0x04
  859. #define PHY_RDR 0x05
  860. #define PHY_RDR_RXDSEL_1_9 0x4000
  861. #define PHY_SSC_AUTO_PWD 0x0600
  862. #define PHY_TCR0 0x06
  863. #define PHY_TCR1 0x07
  864. #define PHY_TUNE 0x08
  865. #define PHY_TUNE_TUNEREF_1_0 0x4000
  866. #define PHY_TUNE_VBGSEL_1252 0x0C00
  867. #define PHY_TUNE_SDBUS_33 0x0200
  868. #define PHY_TUNE_TUNED18 0x01C0
  869. #define PHY_TUNE_TUNED12 0X0020
  870. #define PHY_TUNE_TUNEA12 0x0004
  871. #define PHY_TUNE_VOLTAGE_MASK 0xFC3F
  872. #define PHY_TUNE_VOLTAGE_3V3 0x03C0
  873. #define PHY_TUNE_D18_1V8 0x0100
  874. #define PHY_TUNE_D18_1V7 0x0080
  875. #define PHY_ANA08 0x08
  876. #define PHY_ANA08_RX_EQ_DCGAIN 0x5000
  877. #define PHY_ANA08_SEL_RX_EN 0x0400
  878. #define PHY_ANA08_RX_EQ_VAL 0x03C0
  879. #define PHY_ANA08_SCP 0x0020
  880. #define PHY_ANA08_SEL_IPI 0x0004
  881. #define PHY_IMR 0x09
  882. #define PHY_BPCR 0x0A
  883. #define PHY_BPCR_IBRXSEL 0x0400
  884. #define PHY_BPCR_IBTXSEL 0x0100
  885. #define PHY_BPCR_IB_FILTER 0x0080
  886. #define PHY_BPCR_CMIRROR_EN 0x0040
  887. #define PHY_BIST 0x0B
  888. #define PHY_RAW_L 0x0C
  889. #define PHY_RAW_H 0x0D
  890. #define PHY_RAW_DATA 0x0E
  891. #define PHY_HOST_CLK_CTRL 0x0F
  892. #define PHY_DMR 0x10
  893. #define PHY_BACR 0x11
  894. #define PHY_BACR_BASIC_MASK 0xFFF3
  895. #define PHY_IER 0x12
  896. #define PHY_BCSR 0x13
  897. #define PHY_BPR 0x14
  898. #define PHY_BPNR2 0x15
  899. #define PHY_BPNR 0x16
  900. #define PHY_BRNR2 0x17
  901. #define PHY_BENR 0x18
  902. #define PHY_REV 0x19
  903. #define PHY_REV_RESV 0xE000
  904. #define PHY_REV_RXIDLE_LATCHED 0x1000
  905. #define PHY_REV_P1_EN 0x0800
  906. #define PHY_REV_RXIDLE_EN 0x0400
  907. #define PHY_REV_CLKREQ_TX_EN 0x0200
  908. #define PHY_REV_CLKREQ_RX_EN 0x0100
  909. #define PHY_REV_CLKREQ_DT_1_0 0x0040
  910. #define PHY_REV_STOP_CLKRD 0x0020
  911. #define PHY_REV_RX_PWST 0x0008
  912. #define PHY_REV_STOP_CLKWR 0x0004
  913. #define _PHY_REV0 0x19
  914. #define _PHY_REV0_FILTER_OUT 0x3800
  915. #define _PHY_REV0_CDR_BYPASS_PFD 0x0100
  916. #define _PHY_REV0_CDR_RX_IDLE_BYPASS 0x0002
  917. #define PHY_FLD0 0x1A
  918. #define PHY_ANA1A 0x1A
  919. #define PHY_ANA1A_TXR_LOOPBACK 0x2000
  920. #define PHY_ANA1A_RXT_BIST 0x0500
  921. #define PHY_ANA1A_TXR_BIST 0x0040
  922. #define PHY_ANA1A_REV 0x0006
  923. #define PHY_FLD0_INIT_27S 0x2546
  924. #define PHY_FLD1 0x1B
  925. #define PHY_FLD2 0x1C
  926. #define PHY_FLD3 0x1D
  927. #define PHY_FLD3_TIMER_4 0x0800
  928. #define PHY_FLD3_TIMER_6 0x0020
  929. #define PHY_FLD3_RXDELINK 0x0004
  930. #define PHY_FLD3_INIT_27S 0x0004
  931. #define PHY_ANA1D 0x1D
  932. #define PHY_ANA1D_DEBUG_ADDR 0x0004
  933. #define _PHY_FLD0 0x1D
  934. #define _PHY_FLD0_CLK_REQ_20C 0x8000
  935. #define _PHY_FLD0_RX_IDLE_EN 0x1000
  936. #define _PHY_FLD0_BIT_ERR_RSTN 0x0800
  937. #define _PHY_FLD0_BER_COUNT 0x01E0
  938. #define _PHY_FLD0_BER_TIMER 0x001E
  939. #define _PHY_FLD0_CHECK_EN 0x0001
  940. #define PHY_FLD4 0x1E
  941. #define PHY_FLD4_FLDEN_SEL 0x4000
  942. #define PHY_FLD4_REQ_REF 0x2000
  943. #define PHY_FLD4_RXAMP_OFF 0x1000
  944. #define PHY_FLD4_REQ_ADDA 0x0800
  945. #define PHY_FLD4_BER_COUNT 0x00E0
  946. #define PHY_FLD4_BER_TIMER 0x000A
  947. #define PHY_FLD4_BER_CHK_EN 0x0001
  948. #define PHY_FLD4_INIT_27S 0x5C7F
  949. #define PHY_DIG1E 0x1E
  950. #define PHY_DIG1E_REV 0x4000
  951. #define PHY_DIG1E_D0_X_D1 0x1000
  952. #define PHY_DIG1E_RX_ON_HOST 0x0800
  953. #define PHY_DIG1E_RCLK_REF_HOST 0x0400
  954. #define PHY_DIG1E_RCLK_TX_EN_KEEP 0x0040
  955. #define PHY_DIG1E_RCLK_TX_TERM_KEEP 0x0020
  956. #define PHY_DIG1E_RCLK_RX_EIDLE_ON 0x0010
  957. #define PHY_DIG1E_TX_TERM_KEEP 0x0008
  958. #define PHY_DIG1E_RX_TERM_KEEP 0x0004
  959. #define PHY_DIG1E_TX_EN_KEEP 0x0002
  960. #define PHY_DIG1E_RX_EN_KEEP 0x0001
  961. #define PHY_DUM_REG 0x1F
  962. #define PCR_SETTING_REG1 0x724
  963. #define PCR_SETTING_REG2 0x814
  964. #define PCR_SETTING_REG3 0x747
  965. #define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0)
  966. #define RTS5227_DEVICE_ID 0x5227
  967. #define RTS_MAX_TIMES_FREQ_REDUCTION 8
  968. struct rtsx_pcr;
  969. struct pcr_handle {
  970. struct rtsx_pcr *pcr;
  971. };
  972. struct pcr_ops {
  973. int (*write_phy)(struct rtsx_pcr *pcr, u8 addr, u16 val);
  974. int (*read_phy)(struct rtsx_pcr *pcr, u8 addr, u16 *val);
  975. int (*extra_init_hw)(struct rtsx_pcr *pcr);
  976. int (*optimize_phy)(struct rtsx_pcr *pcr);
  977. int (*turn_on_led)(struct rtsx_pcr *pcr);
  978. int (*turn_off_led)(struct rtsx_pcr *pcr);
  979. int (*enable_auto_blink)(struct rtsx_pcr *pcr);
  980. int (*disable_auto_blink)(struct rtsx_pcr *pcr);
  981. int (*card_power_on)(struct rtsx_pcr *pcr, int card);
  982. int (*card_power_off)(struct rtsx_pcr *pcr, int card);
  983. int (*switch_output_voltage)(struct rtsx_pcr *pcr,
  984. u8 voltage);
  985. unsigned int (*cd_deglitch)(struct rtsx_pcr *pcr);
  986. int (*conv_clk_and_div_n)(int clk, int dir);
  987. void (*fetch_vendor_settings)(struct rtsx_pcr *pcr);
  988. void (*force_power_down)(struct rtsx_pcr *pcr, u8 pm_state);
  989. void (*stop_cmd)(struct rtsx_pcr *pcr);
  990. void (*set_aspm)(struct rtsx_pcr *pcr, bool enable);
  991. void (*set_l1off_cfg_sub_d0)(struct rtsx_pcr *pcr, int active);
  992. void (*enable_ocp)(struct rtsx_pcr *pcr);
  993. void (*disable_ocp)(struct rtsx_pcr *pcr);
  994. void (*init_ocp)(struct rtsx_pcr *pcr);
  995. void (*process_ocp)(struct rtsx_pcr *pcr);
  996. int (*get_ocpstat)(struct rtsx_pcr *pcr, u8 *val);
  997. void (*clear_ocpstat)(struct rtsx_pcr *pcr);
  998. };
  999. enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN};
  1000. #define ASPM_L1_1_EN BIT(0)
  1001. #define ASPM_L1_2_EN BIT(1)
  1002. #define PM_L1_1_EN BIT(2)
  1003. #define PM_L1_2_EN BIT(3)
  1004. #define LTR_L1SS_PWR_GATE_EN BIT(4)
  1005. #define L1_SNOOZE_TEST_EN BIT(5)
  1006. #define LTR_L1SS_PWR_GATE_CHECK_CARD_EN BIT(6)
  1007. /*
  1008. * struct rtsx_cr_option - card reader option
  1009. * @dev_flags: device flags
  1010. * @force_clkreq_0: force clock request
  1011. * @ltr_en: enable ltr mode flag
  1012. * @ltr_enabled: ltr mode in configure space flag
  1013. * @ltr_active: ltr mode status
  1014. * @ltr_active_latency: ltr mode active latency
  1015. * @ltr_idle_latency: ltr mode idle latency
  1016. * @ltr_l1off_latency: ltr mode l1off latency
  1017. * @l1_snooze_delay: l1 snooze delay
  1018. * @ltr_l1off_sspwrgate: ltr l1off sspwrgate
  1019. * @ltr_l1off_snooze_sspwrgate: ltr l1off snooze sspwrgate
  1020. * @ocp_en: enable ocp flag
  1021. * @sd_400mA_ocp_thd: 400mA ocp thd
  1022. * @sd_800mA_ocp_thd: 800mA ocp thd
  1023. */
  1024. struct rtsx_cr_option {
  1025. u32 dev_flags;
  1026. bool force_clkreq_0;
  1027. bool ltr_en;
  1028. bool ltr_enabled;
  1029. bool ltr_active;
  1030. u32 ltr_active_latency;
  1031. u32 ltr_idle_latency;
  1032. u32 ltr_l1off_latency;
  1033. u32 l1_snooze_delay;
  1034. u8 ltr_l1off_sspwrgate;
  1035. u8 ltr_l1off_snooze_sspwrgate;
  1036. bool ocp_en;
  1037. u8 sd_400mA_ocp_thd;
  1038. u8 sd_800mA_ocp_thd;
  1039. };
  1040. /*
  1041. * struct rtsx_hw_param - card reader hardware param
  1042. * @interrupt_en: indicate which interrutp enable
  1043. * @ocp_glitch: ocp glitch time
  1044. */
  1045. struct rtsx_hw_param {
  1046. u32 interrupt_en;
  1047. u8 ocp_glitch;
  1048. };
  1049. #define rtsx_set_dev_flag(cr, flag) \
  1050. ((cr)->option.dev_flags |= (flag))
  1051. #define rtsx_clear_dev_flag(cr, flag) \
  1052. ((cr)->option.dev_flags &= ~(flag))
  1053. #define rtsx_check_dev_flag(cr, flag) \
  1054. ((cr)->option.dev_flags & (flag))
  1055. struct rtsx_pcr {
  1056. struct pci_dev *pci;
  1057. unsigned int id;
  1058. struct rtsx_cr_option option;
  1059. struct rtsx_hw_param hw_param;
  1060. /* pci resources */
  1061. unsigned long addr;
  1062. void __iomem *remap_addr;
  1063. int irq;
  1064. /* host reserved buffer */
  1065. void *rtsx_resv_buf;
  1066. dma_addr_t rtsx_resv_buf_addr;
  1067. void *host_cmds_ptr;
  1068. dma_addr_t host_cmds_addr;
  1069. int ci;
  1070. void *host_sg_tbl_ptr;
  1071. dma_addr_t host_sg_tbl_addr;
  1072. int sgi;
  1073. u32 bier;
  1074. char trans_result;
  1075. unsigned int card_inserted;
  1076. unsigned int card_removed;
  1077. unsigned int card_exist;
  1078. struct delayed_work carddet_work;
  1079. struct delayed_work idle_work;
  1080. spinlock_t lock;
  1081. struct mutex pcr_mutex;
  1082. struct completion *done;
  1083. struct completion *finish_me;
  1084. unsigned int cur_clock;
  1085. bool remove_pci;
  1086. bool msi_en;
  1087. #define EXTRA_CAPS_SD_SDR50 (1 << 0)
  1088. #define EXTRA_CAPS_SD_SDR104 (1 << 1)
  1089. #define EXTRA_CAPS_SD_DDR50 (1 << 2)
  1090. #define EXTRA_CAPS_MMC_HSDDR (1 << 3)
  1091. #define EXTRA_CAPS_MMC_HS200 (1 << 4)
  1092. #define EXTRA_CAPS_MMC_8BIT (1 << 5)
  1093. #define EXTRA_CAPS_NO_MMC (1 << 7)
  1094. u32 extra_caps;
  1095. #define IC_VER_A 0
  1096. #define IC_VER_B 1
  1097. #define IC_VER_C 2
  1098. #define IC_VER_D 3
  1099. u8 ic_version;
  1100. u8 sd30_drive_sel_1v8;
  1101. u8 sd30_drive_sel_3v3;
  1102. u8 card_drive_sel;
  1103. #define ASPM_L1_EN 0x02
  1104. u8 aspm_en;
  1105. bool aspm_enabled;
  1106. #define PCR_MS_PMOS (1 << 0)
  1107. #define PCR_REVERSE_SOCKET (1 << 1)
  1108. u32 flags;
  1109. u32 tx_initial_phase;
  1110. u32 rx_initial_phase;
  1111. const u32 *sd_pull_ctl_enable_tbl;
  1112. const u32 *sd_pull_ctl_disable_tbl;
  1113. const u32 *ms_pull_ctl_enable_tbl;
  1114. const u32 *ms_pull_ctl_disable_tbl;
  1115. const struct pcr_ops *ops;
  1116. enum PDEV_STAT state;
  1117. u16 reg_pm_ctrl3;
  1118. int num_slots;
  1119. struct rtsx_slot *slots;
  1120. u8 dma_error_count;
  1121. u8 ocp_stat;
  1122. u8 ocp_stat2;
  1123. u8 rtd3_en;
  1124. };
  1125. #define PID_524A 0x524A
  1126. #define PID_5249 0x5249
  1127. #define PID_5250 0x5250
  1128. #define PID_525A 0x525A
  1129. #define PID_5260 0x5260
  1130. #define PID_5261 0x5261
  1131. #define PID_5228 0x5228
  1132. #define CHK_PCI_PID(pcr, pid) ((pcr)->pci->device == (pid))
  1133. #define PCI_VID(pcr) ((pcr)->pci->vendor)
  1134. #define PCI_PID(pcr) ((pcr)->pci->device)
  1135. #define is_version(pcr, pid, ver) \
  1136. (CHK_PCI_PID(pcr, pid) && (pcr)->ic_version == (ver))
  1137. #define pcr_dbg(pcr, fmt, arg...) \
  1138. dev_dbg(&(pcr)->pci->dev, fmt, ##arg)
  1139. #define SDR104_PHASE(val) ((val) & 0xFF)
  1140. #define SDR50_PHASE(val) (((val) >> 8) & 0xFF)
  1141. #define DDR50_PHASE(val) (((val) >> 16) & 0xFF)
  1142. #define SDR104_TX_PHASE(pcr) SDR104_PHASE((pcr)->tx_initial_phase)
  1143. #define SDR50_TX_PHASE(pcr) SDR50_PHASE((pcr)->tx_initial_phase)
  1144. #define DDR50_TX_PHASE(pcr) DDR50_PHASE((pcr)->tx_initial_phase)
  1145. #define SDR104_RX_PHASE(pcr) SDR104_PHASE((pcr)->rx_initial_phase)
  1146. #define SDR50_RX_PHASE(pcr) SDR50_PHASE((pcr)->rx_initial_phase)
  1147. #define DDR50_RX_PHASE(pcr) DDR50_PHASE((pcr)->rx_initial_phase)
  1148. #define SET_CLOCK_PHASE(sdr104, sdr50, ddr50) \
  1149. (((ddr50) << 16) | ((sdr50) << 8) | (sdr104))
  1150. void rtsx_pci_start_run(struct rtsx_pcr *pcr);
  1151. int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data);
  1152. int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data);
  1153. int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
  1154. int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
  1155. void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr);
  1156. void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
  1157. u8 cmd_type, u16 reg_addr, u8 mask, u8 data);
  1158. void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr);
  1159. int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout);
  1160. int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
  1161. int num_sg, bool read, int timeout);
  1162. int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
  1163. int num_sg, bool read);
  1164. void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
  1165. int num_sg, bool read);
  1166. int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
  1167. int count, bool read, int timeout);
  1168. int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
  1169. int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
  1170. int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card);
  1171. int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card);
  1172. int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
  1173. u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
  1174. int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card);
  1175. int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card);
  1176. int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card);
  1177. int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage);
  1178. unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr);
  1179. void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr);
  1180. static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)
  1181. {
  1182. return (u8 *)(pcr->host_cmds_ptr);
  1183. }
  1184. static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val)
  1185. {
  1186. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg, 0xFF, val >> 24);
  1187. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 1, 0xFF, val >> 16);
  1188. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 2, 0xFF, val >> 8);
  1189. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val);
  1190. }
  1191. static inline int rtsx_pci_update_phy(struct rtsx_pcr *pcr, u8 addr,
  1192. u16 mask, u16 append)
  1193. {
  1194. int err;
  1195. u16 val;
  1196. err = rtsx_pci_read_phy_register(pcr, addr, &val);
  1197. if (err < 0)
  1198. return err;
  1199. return rtsx_pci_write_phy_register(pcr, addr, (val & mask) | append);
  1200. }
  1201. #endif