qcom_scm.h 6.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /* Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2015 Linaro Ltd.
  4. */
  5. #ifndef __QCOM_SCM_H
  6. #define __QCOM_SCM_H
  7. #include <linux/err.h>
  8. #include <linux/types.h>
  9. #include <linux/cpumask.h>
  10. #define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
  11. #define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
  12. #define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
  13. #define QCOM_SCM_HDCP_MAX_REQ_CNT 5
  14. struct qcom_scm_hdcp_req {
  15. u32 addr;
  16. u32 val;
  17. };
  18. struct qcom_scm_vmperm {
  19. int vmid;
  20. int perm;
  21. };
  22. enum qcom_scm_ocmem_client {
  23. QCOM_SCM_OCMEM_UNUSED_ID = 0x0,
  24. QCOM_SCM_OCMEM_GRAPHICS_ID,
  25. QCOM_SCM_OCMEM_VIDEO_ID,
  26. QCOM_SCM_OCMEM_LP_AUDIO_ID,
  27. QCOM_SCM_OCMEM_SENSORS_ID,
  28. QCOM_SCM_OCMEM_OTHER_OS_ID,
  29. QCOM_SCM_OCMEM_DEBUG_ID,
  30. };
  31. enum qcom_scm_sec_dev_id {
  32. QCOM_SCM_MDSS_DEV_ID = 1,
  33. QCOM_SCM_OCMEM_DEV_ID = 5,
  34. QCOM_SCM_PCIE0_DEV_ID = 11,
  35. QCOM_SCM_PCIE1_DEV_ID = 12,
  36. QCOM_SCM_GFX_DEV_ID = 18,
  37. QCOM_SCM_UFS_DEV_ID = 19,
  38. QCOM_SCM_ICE_DEV_ID = 20,
  39. };
  40. enum qcom_scm_ice_cipher {
  41. QCOM_SCM_ICE_CIPHER_AES_128_XTS = 0,
  42. QCOM_SCM_ICE_CIPHER_AES_128_CBC = 1,
  43. QCOM_SCM_ICE_CIPHER_AES_256_XTS = 3,
  44. QCOM_SCM_ICE_CIPHER_AES_256_CBC = 4,
  45. };
  46. #define QCOM_SCM_VMID_HLOS 0x3
  47. #define QCOM_SCM_VMID_MSS_MSA 0xF
  48. #define QCOM_SCM_VMID_WLAN 0x18
  49. #define QCOM_SCM_VMID_WLAN_CE 0x19
  50. #define QCOM_SCM_PERM_READ 0x4
  51. #define QCOM_SCM_PERM_WRITE 0x2
  52. #define QCOM_SCM_PERM_EXEC 0x1
  53. #define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE)
  54. #define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
  55. #if IS_ENABLED(CONFIG_QCOM_SCM)
  56. extern bool qcom_scm_is_available(void);
  57. extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
  58. extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
  59. extern void qcom_scm_cpu_power_down(u32 flags);
  60. extern int qcom_scm_set_remote_state(u32 state, u32 id);
  61. extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
  62. size_t size);
  63. extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
  64. phys_addr_t size);
  65. extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
  66. extern int qcom_scm_pas_shutdown(u32 peripheral);
  67. extern bool qcom_scm_pas_supported(u32 peripheral);
  68. extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
  69. extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
  70. extern bool qcom_scm_restore_sec_cfg_available(void);
  71. extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
  72. extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
  73. extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
  74. extern int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
  75. u32 cp_nonpixel_start,
  76. u32 cp_nonpixel_size);
  77. extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
  78. unsigned int *src,
  79. const struct qcom_scm_vmperm *newvm,
  80. unsigned int dest_cnt);
  81. extern bool qcom_scm_ocmem_lock_available(void);
  82. extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
  83. u32 size, u32 mode);
  84. extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset,
  85. u32 size);
  86. extern bool qcom_scm_ice_available(void);
  87. extern int qcom_scm_ice_invalidate_key(u32 index);
  88. extern int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size,
  89. enum qcom_scm_ice_cipher cipher,
  90. u32 data_unit_size);
  91. extern bool qcom_scm_hdcp_available(void);
  92. extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
  93. u32 *resp);
  94. extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
  95. #else
  96. #include <linux/errno.h>
  97. static inline bool qcom_scm_is_available(void) { return false; }
  98. static inline int qcom_scm_set_cold_boot_addr(void *entry,
  99. const cpumask_t *cpus) { return -ENODEV; }
  100. static inline int qcom_scm_set_warm_boot_addr(void *entry,
  101. const cpumask_t *cpus) { return -ENODEV; }
  102. static inline void qcom_scm_cpu_power_down(u32 flags) {}
  103. static inline u32 qcom_scm_set_remote_state(u32 state,u32 id)
  104. { return -ENODEV; }
  105. static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
  106. size_t size) { return -ENODEV; }
  107. static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
  108. phys_addr_t size) { return -ENODEV; }
  109. static inline int qcom_scm_pas_auth_and_reset(u32 peripheral)
  110. { return -ENODEV; }
  111. static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
  112. static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
  113. static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
  114. { return -ENODEV; }
  115. static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
  116. { return -ENODEV; }
  117. static inline bool qcom_scm_restore_sec_cfg_available(void) { return false; }
  118. static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
  119. { return -ENODEV; }
  120. static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
  121. { return -ENODEV; }
  122. static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
  123. { return -ENODEV; }
  124. extern inline int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
  125. u32 cp_nonpixel_start,
  126. u32 cp_nonpixel_size)
  127. { return -ENODEV; }
  128. static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
  129. unsigned int *src, const struct qcom_scm_vmperm *newvm,
  130. unsigned int dest_cnt) { return -ENODEV; }
  131. static inline bool qcom_scm_ocmem_lock_available(void) { return false; }
  132. static inline int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
  133. u32 size, u32 mode) { return -ENODEV; }
  134. static inline int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id,
  135. u32 offset, u32 size) { return -ENODEV; }
  136. static inline bool qcom_scm_ice_available(void) { return false; }
  137. static inline int qcom_scm_ice_invalidate_key(u32 index) { return -ENODEV; }
  138. static inline int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size,
  139. enum qcom_scm_ice_cipher cipher,
  140. u32 data_unit_size) { return -ENODEV; }
  141. static inline bool qcom_scm_hdcp_available(void) { return false; }
  142. static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
  143. u32 *resp) { return -ENODEV; }
  144. static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
  145. { return -ENODEV; }
  146. #endif
  147. #endif