pxa2xx_ssp.h 10 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) 2003 Russell King, All Rights Reserved.
  4. *
  5. * This driver supports the following PXA CPU/SSP ports:-
  6. *
  7. * PXA250 SSP
  8. * PXA255 SSP, NSSP
  9. * PXA26x SSP, NSSP, ASSP
  10. * PXA27x SSP1, SSP2, SSP3
  11. * PXA3xx SSP1, SSP2, SSP3, SSP4
  12. */
  13. #ifndef __LINUX_SSP_H
  14. #define __LINUX_SSP_H
  15. #include <linux/bits.h>
  16. #include <linux/compiler_types.h>
  17. #include <linux/io.h>
  18. #include <linux/kconfig.h>
  19. #include <linux/list.h>
  20. #include <linux/types.h>
  21. struct clk;
  22. struct device;
  23. struct device_node;
  24. /*
  25. * SSP Serial Port Registers
  26. * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
  27. * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
  28. */
  29. #define SSCR0 (0x00) /* SSP Control Register 0 */
  30. #define SSCR1 (0x04) /* SSP Control Register 1 */
  31. #define SSSR (0x08) /* SSP Status Register */
  32. #define SSITR (0x0C) /* SSP Interrupt Test Register */
  33. #define SSDR (0x10) /* SSP Data Write/Data Read Register */
  34. #define SSTO (0x28) /* SSP Time Out Register */
  35. #define DDS_RATE (0x28) /* SSP DDS Clock Rate Register (Intel Quark) */
  36. #define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
  37. #define SSTSA (0x30) /* SSP Tx Timeslot Active */
  38. #define SSRSA (0x34) /* SSP Rx Timeslot Active */
  39. #define SSTSS (0x38) /* SSP Timeslot Status */
  40. #define SSACD (0x3C) /* SSP Audio Clock Divider */
  41. #define SSACDD (0x40) /* SSP Audio Clock Dither Divider */
  42. /* Common PXA2xx bits first */
  43. #define SSCR0_DSS GENMASK(3, 0) /* Data Size Select (mask) */
  44. #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
  45. #define SSCR0_FRF GENMASK(5, 4) /* FRame Format (mask) */
  46. #define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
  47. #define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
  48. #define SSCR0_National (0x2 << 4) /* National Microwire */
  49. #define SSCR0_ECS BIT(6) /* External clock select */
  50. #define SSCR0_SSE BIT(7) /* Synchronous Serial Port Enable */
  51. #define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */
  52. /* PXA27x, PXA3xx */
  53. #define SSCR0_EDSS BIT(20) /* Extended data size select */
  54. #define SSCR0_NCS BIT(21) /* Network clock select */
  55. #define SSCR0_RIM BIT(22) /* Receive FIFO overrrun interrupt mask */
  56. #define SSCR0_TUM BIT(23) /* Transmit FIFO underrun interrupt mask */
  57. #define SSCR0_FRDC GENMASK(26, 24) /* Frame rate divider control (mask) */
  58. #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
  59. #define SSCR0_FPCKE BIT(29) /* FIFO packing enable */
  60. #define SSCR0_ACS BIT(30) /* Audio clock select */
  61. #define SSCR0_MOD BIT(31) /* Mode (normal or network) */
  62. #define SSCR1_RIE BIT(0) /* Receive FIFO Interrupt Enable */
  63. #define SSCR1_TIE BIT(1) /* Transmit FIFO Interrupt Enable */
  64. #define SSCR1_LBM BIT(2) /* Loop-Back Mode */
  65. #define SSCR1_SPO BIT(3) /* Motorola SPI SSPSCLK polarity setting */
  66. #define SSCR1_SPH BIT(4) /* Motorola SPI SSPSCLK phase setting */
  67. #define SSCR1_MWDS BIT(5) /* Microwire Transmit Data Size */
  68. #define SSSR_ALT_FRM_MASK GENMASK(1, 0) /* Masks the SFRM signal number */
  69. #define SSSR_TNF BIT(2) /* Transmit FIFO Not Full */
  70. #define SSSR_RNE BIT(3) /* Receive FIFO Not Empty */
  71. #define SSSR_BSY BIT(4) /* SSP Busy */
  72. #define SSSR_TFS BIT(5) /* Transmit FIFO Service Request */
  73. #define SSSR_RFS BIT(6) /* Receive FIFO Service Request */
  74. #define SSSR_ROR BIT(7) /* Receive FIFO Overrun */
  75. #define RX_THRESH_DFLT 8
  76. #define TX_THRESH_DFLT 8
  77. #define SSSR_TFL_MASK GENMASK(11, 8) /* Transmit FIFO Level mask */
  78. #define SSSR_RFL_MASK GENMASK(15, 12) /* Receive FIFO Level mask */
  79. #define SSCR1_TFT GENMASK(9, 6) /* Transmit FIFO Threshold (mask) */
  80. #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
  81. #define SSCR1_RFT GENMASK(13, 10) /* Receive FIFO Threshold (mask) */
  82. #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
  83. #define RX_THRESH_CE4100_DFLT 2
  84. #define TX_THRESH_CE4100_DFLT 2
  85. #define CE4100_SSSR_TFL_MASK GENMASK(9, 8) /* Transmit FIFO Level mask */
  86. #define CE4100_SSSR_RFL_MASK GENMASK(13, 12) /* Receive FIFO Level mask */
  87. #define CE4100_SSCR1_TFT GENMASK(7, 6) /* Transmit FIFO Threshold (mask) */
  88. #define CE4100_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..4] */
  89. #define CE4100_SSCR1_RFT GENMASK(11, 10) /* Receive FIFO Threshold (mask) */
  90. #define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */
  91. /* QUARK_X1000 SSCR0 bit definition */
  92. #define QUARK_X1000_SSCR0_DSS GENMASK(4, 0) /* Data Size Select (mask) */
  93. #define QUARK_X1000_SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..32] */
  94. #define QUARK_X1000_SSCR0_FRF GENMASK(6, 5) /* FRame Format (mask) */
  95. #define QUARK_X1000_SSCR0_Motorola (0x0 << 5) /* Motorola's Serial Peripheral Interface (SPI) */
  96. #define RX_THRESH_QUARK_X1000_DFLT 1
  97. #define TX_THRESH_QUARK_X1000_DFLT 16
  98. #define QUARK_X1000_SSSR_TFL_MASK GENMASK(12, 8) /* Transmit FIFO Level mask */
  99. #define QUARK_X1000_SSSR_RFL_MASK GENMASK(17, 13) /* Receive FIFO Level mask */
  100. #define QUARK_X1000_SSCR1_TFT GENMASK(10, 6) /* Transmit FIFO Threshold (mask) */
  101. #define QUARK_X1000_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..32] */
  102. #define QUARK_X1000_SSCR1_RFT GENMASK(15, 11) /* Receive FIFO Threshold (mask) */
  103. #define QUARK_X1000_SSCR1_RxTresh(x) (((x) - 1) << 11) /* level [1..32] */
  104. #define QUARK_X1000_SSCR1_EFWR BIT(16) /* Enable FIFO Write/Read */
  105. #define QUARK_X1000_SSCR1_STRF BIT(17) /* Select FIFO or EFWR */
  106. /* extra bits in PXA255, PXA26x and PXA27x SSP ports */
  107. #define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
  108. #define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
  109. #define SSCR1_EFWR BIT(14) /* Enable FIFO Write/Read */
  110. #define SSCR1_STRF BIT(15) /* Select FIFO or EFWR */
  111. #define SSCR1_IFS BIT(16) /* Invert Frame Signal */
  112. #define SSCR1_PINTE BIT(18) /* Peripheral Trailing Byte Interrupt Enable */
  113. #define SSCR1_TINTE BIT(19) /* Receiver Time-out Interrupt enable */
  114. #define SSCR1_RSRE BIT(20) /* Receive Service Request Enable */
  115. #define SSCR1_TSRE BIT(21) /* Transmit Service Request Enable */
  116. #define SSCR1_TRAIL BIT(22) /* Trailing Byte */
  117. #define SSCR1_RWOT BIT(23) /* Receive Without Transmit */
  118. #define SSCR1_SFRMDIR BIT(24) /* Frame Direction */
  119. #define SSCR1_SCLKDIR BIT(25) /* Serial Bit Rate Clock Direction */
  120. #define SSCR1_ECRB BIT(26) /* Enable Clock request B */
  121. #define SSCR1_ECRA BIT(27) /* Enable Clock Request A */
  122. #define SSCR1_SCFR BIT(28) /* Slave Clock free Running */
  123. #define SSCR1_EBCEI BIT(29) /* Enable Bit Count Error interrupt */
  124. #define SSCR1_TTE BIT(30) /* TXD Tristate Enable */
  125. #define SSCR1_TTELP BIT(31) /* TXD Tristate Enable Last Phase */
  126. #define SSSR_PINT BIT(18) /* Peripheral Trailing Byte Interrupt */
  127. #define SSSR_TINT BIT(19) /* Receiver Time-out Interrupt */
  128. #define SSSR_EOC BIT(20) /* End Of Chain */
  129. #define SSSR_TUR BIT(21) /* Transmit FIFO Under Run */
  130. #define SSSR_CSS BIT(22) /* Clock Synchronisation Status */
  131. #define SSSR_BCE BIT(23) /* Bit Count Error */
  132. #define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
  133. #define SSPSP_SFRMP BIT(2) /* Serial Frame Polarity */
  134. #define SSPSP_ETDS BIT(3) /* End of Transfer data State */
  135. #define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
  136. #define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
  137. #define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
  138. #define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
  139. #define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
  140. #define SSPSP_FSRT BIT(25) /* Frame Sync Relative Timing */
  141. /* PXA3xx */
  142. #define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */
  143. #define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */
  144. #define SSPSP_TIMING_MASK (0x7f8001f0)
  145. #define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
  146. #define SSACD_ACDS_1 (0)
  147. #define SSACD_ACDS_2 (1)
  148. #define SSACD_ACDS_4 (2)
  149. #define SSACD_ACDS_8 (3)
  150. #define SSACD_ACDS_16 (4)
  151. #define SSACD_ACDS_32 (5)
  152. #define SSACD_SCDB BIT(3) /* SSPSYSCLK Divider Bypass */
  153. #define SSACD_SCDB_4X (0)
  154. #define SSACD_SCDB_1X (1)
  155. #define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
  156. #define SSACD_SCDX8 BIT(7) /* SYSCLK division ratio select */
  157. /* LPSS SSP */
  158. #define SSITF 0x44 /* TX FIFO trigger level */
  159. #define SSITF_TxHiThresh(x) (((x) - 1) << 0)
  160. #define SSITF_TxLoThresh(x) (((x) - 1) << 8)
  161. #define SSIRF 0x48 /* RX FIFO trigger level */
  162. #define SSIRF_RxThresh(x) ((x) - 1)
  163. /* LPT/WPT SSP */
  164. #define SSCR2 (0x40) /* SSP Command / Status 2 */
  165. #define SSPSP2 (0x44) /* SSP Programmable Serial Protocol 2 */
  166. enum pxa_ssp_type {
  167. SSP_UNDEFINED = 0,
  168. PXA25x_SSP, /* pxa 210, 250, 255, 26x */
  169. PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
  170. PXA27x_SSP,
  171. PXA3xx_SSP,
  172. PXA168_SSP,
  173. MMP2_SSP,
  174. PXA910_SSP,
  175. CE4100_SSP,
  176. QUARK_X1000_SSP,
  177. LPSS_LPT_SSP, /* Keep LPSS types sorted with lpss_platforms[] */
  178. LPSS_BYT_SSP,
  179. LPSS_BSW_SSP,
  180. LPSS_SPT_SSP,
  181. LPSS_BXT_SSP,
  182. LPSS_CNL_SSP,
  183. };
  184. struct ssp_device {
  185. struct device *dev;
  186. struct list_head node;
  187. struct clk *clk;
  188. void __iomem *mmio_base;
  189. unsigned long phys_base;
  190. const char *label;
  191. int port_id;
  192. enum pxa_ssp_type type;
  193. int use_count;
  194. int irq;
  195. struct device_node *of_node;
  196. };
  197. /**
  198. * pxa_ssp_write_reg - Write to a SSP register
  199. *
  200. * @dev: SSP device to access
  201. * @reg: Register to write to
  202. * @val: Value to be written.
  203. */
  204. static inline void pxa_ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val)
  205. {
  206. __raw_writel(val, dev->mmio_base + reg);
  207. }
  208. /**
  209. * pxa_ssp_read_reg - Read from a SSP register
  210. *
  211. * @dev: SSP device to access
  212. * @reg: Register to read from
  213. */
  214. static inline u32 pxa_ssp_read_reg(struct ssp_device *dev, u32 reg)
  215. {
  216. return __raw_readl(dev->mmio_base + reg);
  217. }
  218. #if IS_ENABLED(CONFIG_PXA_SSP)
  219. struct ssp_device *pxa_ssp_request(int port, const char *label);
  220. void pxa_ssp_free(struct ssp_device *);
  221. struct ssp_device *pxa_ssp_request_of(const struct device_node *of_node,
  222. const char *label);
  223. #else
  224. static inline struct ssp_device *pxa_ssp_request(int port, const char *label)
  225. {
  226. return NULL;
  227. }
  228. static inline struct ssp_device *pxa_ssp_request_of(const struct device_node *n,
  229. const char *name)
  230. {
  231. return NULL;
  232. }
  233. static inline void pxa_ssp_free(struct ssp_device *ssp) {}
  234. #endif
  235. #endif