arm_pmu.h 4.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * linux/arch/arm/include/asm/pmu.h
  4. *
  5. * Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
  6. */
  7. #ifndef __ARM_PMU_H__
  8. #define __ARM_PMU_H__
  9. #include <linux/interrupt.h>
  10. #include <linux/perf_event.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/sysfs.h>
  13. #include <asm/cputype.h>
  14. #ifdef CONFIG_ARM_PMU
  15. /*
  16. * The ARMv7 CPU PMU supports up to 32 event counters.
  17. */
  18. #define ARMPMU_MAX_HWEVENTS 32
  19. /*
  20. * ARM PMU hw_event flags
  21. */
  22. /* Event uses a 64bit counter */
  23. #define ARMPMU_EVT_64BIT 1
  24. #define HW_OP_UNSUPPORTED 0xFFFF
  25. #define C(_x) PERF_COUNT_HW_CACHE_##_x
  26. #define CACHE_OP_UNSUPPORTED 0xFFFF
  27. #define PERF_MAP_ALL_UNSUPPORTED \
  28. [0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
  29. #define PERF_CACHE_MAP_ALL_UNSUPPORTED \
  30. [0 ... C(MAX) - 1] = { \
  31. [0 ... C(OP_MAX) - 1] = { \
  32. [0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \
  33. }, \
  34. }
  35. /* The events for a given PMU register set. */
  36. struct pmu_hw_events {
  37. /*
  38. * The events that are active on the PMU for the given index.
  39. */
  40. struct perf_event *events[ARMPMU_MAX_HWEVENTS];
  41. /*
  42. * A 1 bit for an index indicates that the counter is being used for
  43. * an event. A 0 means that the counter can be used.
  44. */
  45. DECLARE_BITMAP(used_mask, ARMPMU_MAX_HWEVENTS);
  46. /*
  47. * Hardware lock to serialize accesses to PMU registers. Needed for the
  48. * read/modify/write sequences.
  49. */
  50. raw_spinlock_t pmu_lock;
  51. /*
  52. * When using percpu IRQs, we need a percpu dev_id. Place it here as we
  53. * already have to allocate this struct per cpu.
  54. */
  55. struct arm_pmu *percpu_pmu;
  56. int irq;
  57. };
  58. enum armpmu_attr_groups {
  59. ARMPMU_ATTR_GROUP_COMMON,
  60. ARMPMU_ATTR_GROUP_EVENTS,
  61. ARMPMU_ATTR_GROUP_FORMATS,
  62. ARMPMU_ATTR_GROUP_CAPS,
  63. ARMPMU_NR_ATTR_GROUPS
  64. };
  65. struct arm_pmu {
  66. struct pmu pmu;
  67. cpumask_t supported_cpus;
  68. char *name;
  69. int pmuver;
  70. irqreturn_t (*handle_irq)(struct arm_pmu *pmu);
  71. void (*enable)(struct perf_event *event);
  72. void (*disable)(struct perf_event *event);
  73. int (*get_event_idx)(struct pmu_hw_events *hw_events,
  74. struct perf_event *event);
  75. void (*clear_event_idx)(struct pmu_hw_events *hw_events,
  76. struct perf_event *event);
  77. int (*set_event_filter)(struct hw_perf_event *evt,
  78. struct perf_event_attr *attr);
  79. u64 (*read_counter)(struct perf_event *event);
  80. void (*write_counter)(struct perf_event *event, u64 val);
  81. void (*start)(struct arm_pmu *);
  82. void (*stop)(struct arm_pmu *);
  83. void (*reset)(void *);
  84. int (*map_event)(struct perf_event *event);
  85. int (*filter_match)(struct perf_event *event);
  86. int num_events;
  87. bool secure_access; /* 32-bit ARM only */
  88. #define ARMV8_PMUV3_MAX_COMMON_EVENTS 0x40
  89. DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
  90. #define ARMV8_PMUV3_EXT_COMMON_EVENT_BASE 0x4000
  91. DECLARE_BITMAP(pmceid_ext_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
  92. struct platform_device *plat_device;
  93. struct pmu_hw_events __percpu *hw_events;
  94. struct hlist_node node;
  95. struct notifier_block cpu_pm_nb;
  96. /* the attr_groups array must be NULL-terminated */
  97. const struct attribute_group *attr_groups[ARMPMU_NR_ATTR_GROUPS + 1];
  98. /* store the PMMIR_EL1 to expose slots */
  99. u64 reg_pmmir;
  100. /* Only to be used by ACPI probing code */
  101. unsigned long acpi_cpuid;
  102. };
  103. #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
  104. u64 armpmu_event_update(struct perf_event *event);
  105. int armpmu_event_set_period(struct perf_event *event);
  106. int armpmu_map_event(struct perf_event *event,
  107. const unsigned (*event_map)[PERF_COUNT_HW_MAX],
  108. const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
  109. [PERF_COUNT_HW_CACHE_OP_MAX]
  110. [PERF_COUNT_HW_CACHE_RESULT_MAX],
  111. u32 raw_event_mask);
  112. typedef int (*armpmu_init_fn)(struct arm_pmu *);
  113. struct pmu_probe_info {
  114. unsigned int cpuid;
  115. unsigned int mask;
  116. armpmu_init_fn init;
  117. };
  118. #define PMU_PROBE(_cpuid, _mask, _fn) \
  119. { \
  120. .cpuid = (_cpuid), \
  121. .mask = (_mask), \
  122. .init = (_fn), \
  123. }
  124. #define ARM_PMU_PROBE(_cpuid, _fn) \
  125. PMU_PROBE(_cpuid, ARM_CPU_PART_MASK, _fn)
  126. #define ARM_PMU_XSCALE_MASK ((0xff << 24) | ARM_CPU_XSCALE_ARCH_MASK)
  127. #define XSCALE_PMU_PROBE(_version, _fn) \
  128. PMU_PROBE(ARM_CPU_IMP_INTEL << 24 | _version, ARM_PMU_XSCALE_MASK, _fn)
  129. int arm_pmu_device_probe(struct platform_device *pdev,
  130. const struct of_device_id *of_table,
  131. const struct pmu_probe_info *probe_table);
  132. #ifdef CONFIG_ACPI
  133. int arm_pmu_acpi_probe(armpmu_init_fn init_fn);
  134. #else
  135. static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; }
  136. #endif
  137. /* Internal functions only for core arm_pmu code */
  138. struct arm_pmu *armpmu_alloc(void);
  139. struct arm_pmu *armpmu_alloc_atomic(void);
  140. void armpmu_free(struct arm_pmu *pmu);
  141. int armpmu_register(struct arm_pmu *pmu);
  142. int armpmu_request_irq(int irq, int cpu);
  143. void armpmu_free_irq(int irq, int cpu);
  144. #define ARMV8_PMU_PDEV_NAME "armv8-pmu"
  145. #endif /* CONFIG_ARM_PMU */
  146. #define ARMV8_SPE_PDEV_NAME "arm,spe-v1"
  147. #endif /* __ARM_PMU_H__ */