pci.h 87 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * pci.h
  4. *
  5. * PCI defines and function prototypes
  6. * Copyright 1994, Drew Eckhardt
  7. * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
  8. *
  9. * PCI Express ASPM defines and function prototypes
  10. * Copyright (c) 2007 Intel Corp.
  11. * Zhang Yanmin (yanmin.zhang@intel.com)
  12. * Shaohua Li (shaohua.li@intel.com)
  13. *
  14. * For more information, please consult the following manuals (look at
  15. * http://www.pcisig.com/ for how to get them):
  16. *
  17. * PCI BIOS Specification
  18. * PCI Local Bus Specification
  19. * PCI to PCI Bridge Specification
  20. * PCI Express Specification
  21. * PCI System Design Guide
  22. */
  23. #ifndef LINUX_PCI_H
  24. #define LINUX_PCI_H
  25. #include <linux/mod_devicetable.h>
  26. #include <linux/types.h>
  27. #include <linux/init.h>
  28. #include <linux/ioport.h>
  29. #include <linux/list.h>
  30. #include <linux/compiler.h>
  31. #include <linux/errno.h>
  32. #include <linux/kobject.h>
  33. #include <linux/atomic.h>
  34. #include <linux/device.h>
  35. #include <linux/interrupt.h>
  36. #include <linux/io.h>
  37. #include <linux/resource_ext.h>
  38. #include <uapi/linux/pci.h>
  39. #include <linux/pci_ids.h>
  40. #include <linux/android_kabi.h>
  41. #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
  42. PCI_STATUS_SIG_SYSTEM_ERROR | \
  43. PCI_STATUS_REC_MASTER_ABORT | \
  44. PCI_STATUS_REC_TARGET_ABORT | \
  45. PCI_STATUS_SIG_TARGET_ABORT | \
  46. PCI_STATUS_PARITY)
  47. /*
  48. * The PCI interface treats multi-function devices as independent
  49. * devices. The slot/function address of each device is encoded
  50. * in a single byte as follows:
  51. *
  52. * 7:3 = slot
  53. * 2:0 = function
  54. *
  55. * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
  56. * In the interest of not exposing interfaces to user-space unnecessarily,
  57. * the following kernel-only defines are being added here.
  58. */
  59. #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
  60. /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
  61. #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
  62. /* pci_slot represents a physical slot */
  63. struct pci_slot {
  64. struct pci_bus *bus; /* Bus this slot is on */
  65. struct list_head list; /* Node in list of slots */
  66. struct hotplug_slot *hotplug; /* Hotplug info (move here) */
  67. unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
  68. struct kobject kobj;
  69. };
  70. static inline const char *pci_slot_name(const struct pci_slot *slot)
  71. {
  72. return kobject_name(&slot->kobj);
  73. }
  74. /* File state for mmap()s on /proc/bus/pci/X/Y */
  75. enum pci_mmap_state {
  76. pci_mmap_io,
  77. pci_mmap_mem
  78. };
  79. /* For PCI devices, the region numbers are assigned this way: */
  80. enum {
  81. /* #0-5: standard PCI resources */
  82. PCI_STD_RESOURCES,
  83. PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
  84. /* #6: expansion ROM resource */
  85. PCI_ROM_RESOURCE,
  86. /* Device-specific resources */
  87. #ifdef CONFIG_PCI_IOV
  88. PCI_IOV_RESOURCES,
  89. PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
  90. #endif
  91. /* PCI-to-PCI (P2P) bridge windows */
  92. #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
  93. #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
  94. #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
  95. /* CardBus bridge windows */
  96. #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
  97. #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
  98. #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
  99. #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
  100. /* Total number of bridge resources for P2P and CardBus */
  101. #define PCI_BRIDGE_RESOURCE_NUM 4
  102. /* Resources assigned to buses behind the bridge */
  103. PCI_BRIDGE_RESOURCES,
  104. PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
  105. PCI_BRIDGE_RESOURCE_NUM - 1,
  106. /* Total resources associated with a PCI device */
  107. PCI_NUM_RESOURCES,
  108. /* Preserve this for compatibility */
  109. DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
  110. };
  111. /**
  112. * enum pci_interrupt_pin - PCI INTx interrupt values
  113. * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
  114. * @PCI_INTERRUPT_INTA: PCI INTA pin
  115. * @PCI_INTERRUPT_INTB: PCI INTB pin
  116. * @PCI_INTERRUPT_INTC: PCI INTC pin
  117. * @PCI_INTERRUPT_INTD: PCI INTD pin
  118. *
  119. * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
  120. * PCI_INTERRUPT_PIN register.
  121. */
  122. enum pci_interrupt_pin {
  123. PCI_INTERRUPT_UNKNOWN,
  124. PCI_INTERRUPT_INTA,
  125. PCI_INTERRUPT_INTB,
  126. PCI_INTERRUPT_INTC,
  127. PCI_INTERRUPT_INTD,
  128. };
  129. /* The number of legacy PCI INTx interrupts */
  130. #define PCI_NUM_INTX 4
  131. /*
  132. * pci_power_t values must match the bits in the Capabilities PME_Support
  133. * and Control/Status PowerState fields in the Power Management capability.
  134. */
  135. typedef int __bitwise pci_power_t;
  136. #define PCI_D0 ((pci_power_t __force) 0)
  137. #define PCI_D1 ((pci_power_t __force) 1)
  138. #define PCI_D2 ((pci_power_t __force) 2)
  139. #define PCI_D3hot ((pci_power_t __force) 3)
  140. #define PCI_D3cold ((pci_power_t __force) 4)
  141. #define PCI_UNKNOWN ((pci_power_t __force) 5)
  142. #define PCI_POWER_ERROR ((pci_power_t __force) -1)
  143. /* Remember to update this when the list above changes! */
  144. extern const char *pci_power_names[];
  145. static inline const char *pci_power_name(pci_power_t state)
  146. {
  147. return pci_power_names[1 + (__force int) state];
  148. }
  149. /**
  150. * typedef pci_channel_state_t
  151. *
  152. * The pci_channel state describes connectivity between the CPU and
  153. * the PCI device. If some PCI bus between here and the PCI device
  154. * has crashed or locked up, this info is reflected here.
  155. */
  156. typedef unsigned int __bitwise pci_channel_state_t;
  157. enum {
  158. /* I/O channel is in normal state */
  159. pci_channel_io_normal = (__force pci_channel_state_t) 1,
  160. /* I/O to channel is blocked */
  161. pci_channel_io_frozen = (__force pci_channel_state_t) 2,
  162. /* PCI card is dead */
  163. pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
  164. };
  165. typedef unsigned int __bitwise pcie_reset_state_t;
  166. enum pcie_reset_state {
  167. /* Reset is NOT asserted (Use to deassert reset) */
  168. pcie_deassert_reset = (__force pcie_reset_state_t) 1,
  169. /* Use #PERST to reset PCIe device */
  170. pcie_warm_reset = (__force pcie_reset_state_t) 2,
  171. /* Use PCIe Hot Reset to reset device */
  172. pcie_hot_reset = (__force pcie_reset_state_t) 3
  173. };
  174. typedef unsigned short __bitwise pci_dev_flags_t;
  175. enum pci_dev_flags {
  176. /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
  177. PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
  178. /* Device configuration is irrevocably lost if disabled into D3 */
  179. PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
  180. /* Provide indication device is assigned by a Virtual Machine Manager */
  181. PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
  182. /* Flag for quirk use to store if quirk-specific ACS is enabled */
  183. PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
  184. /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
  185. PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
  186. /* Do not use bus resets for device */
  187. PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
  188. /* Do not use PM reset even if device advertises NoSoftRst- */
  189. PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
  190. /* Get VPD from function 0 VPD */
  191. PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
  192. /* A non-root bridge where translation occurs, stop alias search here */
  193. PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
  194. /* Do not use FLR even if device advertises PCI_AF_CAP */
  195. PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
  196. /* Don't use Relaxed Ordering for TLPs directed at this device */
  197. PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
  198. /* Device does honor MSI masking despite saying otherwise */
  199. PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
  200. };
  201. enum pci_irq_reroute_variant {
  202. INTEL_IRQ_REROUTE_VARIANT = 1,
  203. MAX_IRQ_REROUTE_VARIANTS = 3
  204. };
  205. typedef unsigned short __bitwise pci_bus_flags_t;
  206. enum pci_bus_flags {
  207. PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
  208. PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
  209. PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
  210. PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
  211. };
  212. /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
  213. enum pcie_link_width {
  214. PCIE_LNK_WIDTH_RESRV = 0x00,
  215. PCIE_LNK_X1 = 0x01,
  216. PCIE_LNK_X2 = 0x02,
  217. PCIE_LNK_X4 = 0x04,
  218. PCIE_LNK_X8 = 0x08,
  219. PCIE_LNK_X12 = 0x0c,
  220. PCIE_LNK_X16 = 0x10,
  221. PCIE_LNK_X32 = 0x20,
  222. PCIE_LNK_WIDTH_UNKNOWN = 0xff,
  223. };
  224. /* See matching string table in pci_speed_string() */
  225. enum pci_bus_speed {
  226. PCI_SPEED_33MHz = 0x00,
  227. PCI_SPEED_66MHz = 0x01,
  228. PCI_SPEED_66MHz_PCIX = 0x02,
  229. PCI_SPEED_100MHz_PCIX = 0x03,
  230. PCI_SPEED_133MHz_PCIX = 0x04,
  231. PCI_SPEED_66MHz_PCIX_ECC = 0x05,
  232. PCI_SPEED_100MHz_PCIX_ECC = 0x06,
  233. PCI_SPEED_133MHz_PCIX_ECC = 0x07,
  234. PCI_SPEED_66MHz_PCIX_266 = 0x09,
  235. PCI_SPEED_100MHz_PCIX_266 = 0x0a,
  236. PCI_SPEED_133MHz_PCIX_266 = 0x0b,
  237. AGP_UNKNOWN = 0x0c,
  238. AGP_1X = 0x0d,
  239. AGP_2X = 0x0e,
  240. AGP_4X = 0x0f,
  241. AGP_8X = 0x10,
  242. PCI_SPEED_66MHz_PCIX_533 = 0x11,
  243. PCI_SPEED_100MHz_PCIX_533 = 0x12,
  244. PCI_SPEED_133MHz_PCIX_533 = 0x13,
  245. PCIE_SPEED_2_5GT = 0x14,
  246. PCIE_SPEED_5_0GT = 0x15,
  247. PCIE_SPEED_8_0GT = 0x16,
  248. PCIE_SPEED_16_0GT = 0x17,
  249. PCIE_SPEED_32_0GT = 0x18,
  250. PCI_SPEED_UNKNOWN = 0xff,
  251. };
  252. enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
  253. enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
  254. struct pci_cap_saved_data {
  255. u16 cap_nr;
  256. bool cap_extended;
  257. unsigned int size;
  258. u32 data[];
  259. };
  260. struct pci_cap_saved_state {
  261. struct hlist_node next;
  262. struct pci_cap_saved_data cap;
  263. };
  264. struct irq_affinity;
  265. struct pcie_link_state;
  266. struct pci_vpd;
  267. struct pci_sriov;
  268. struct pci_p2pdma;
  269. /* The pci_dev structure describes PCI devices */
  270. struct pci_dev {
  271. struct list_head bus_list; /* Node in per-bus list */
  272. struct pci_bus *bus; /* Bus this device is on */
  273. struct pci_bus *subordinate; /* Bus this device bridges to */
  274. void *sysdata; /* Hook for sys-specific extension */
  275. struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
  276. struct pci_slot *slot; /* Physical slot this device is in */
  277. unsigned int devfn; /* Encoded device & function index */
  278. unsigned short vendor;
  279. unsigned short device;
  280. unsigned short subsystem_vendor;
  281. unsigned short subsystem_device;
  282. unsigned int class; /* 3 bytes: (base,sub,prog-if) */
  283. u8 revision; /* PCI revision, low byte of class word */
  284. u8 hdr_type; /* PCI header type (`multi' flag masked out) */
  285. #ifdef CONFIG_PCIEAER
  286. u16 aer_cap; /* AER capability offset */
  287. struct aer_stats *aer_stats; /* AER stats for this device */
  288. #endif
  289. u8 pcie_cap; /* PCIe capability offset */
  290. u8 msi_cap; /* MSI capability offset */
  291. u8 msix_cap; /* MSI-X capability offset */
  292. u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
  293. u8 rom_base_reg; /* Config register controlling ROM */
  294. u8 pin; /* Interrupt pin this device uses */
  295. u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
  296. unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
  297. struct pci_driver *driver; /* Driver bound to this device */
  298. u64 dma_mask; /* Mask of the bits of bus address this
  299. device implements. Normally this is
  300. 0xffffffff. You only need to change
  301. this if your device has broken DMA
  302. or supports 64-bit transfers. */
  303. struct device_dma_parameters dma_parms;
  304. pci_power_t current_state; /* Current operating state. In ACPI,
  305. this is D0-D3, D0 being fully
  306. functional, and D3 being off. */
  307. unsigned int imm_ready:1; /* Supports Immediate Readiness */
  308. u8 pm_cap; /* PM capability offset */
  309. unsigned int pme_support:5; /* Bitmask of states from which PME#
  310. can be generated */
  311. unsigned int pme_poll:1; /* Poll device's PME status bit */
  312. unsigned int d1_support:1; /* Low power state D1 is supported */
  313. unsigned int d2_support:1; /* Low power state D2 is supported */
  314. unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
  315. unsigned int no_d3cold:1; /* D3cold is forbidden */
  316. unsigned int bridge_d3:1; /* Allow D3 for bridge */
  317. unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
  318. unsigned int mmio_always_on:1; /* Disallow turning off io/mem
  319. decoding during BAR sizing */
  320. unsigned int wakeup_prepared:1;
  321. unsigned int runtime_d3cold:1; /* Whether go through runtime
  322. D3cold, not set for devices
  323. powered on/off by the
  324. corresponding bridge */
  325. unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
  326. unsigned int ignore_hotplug:1; /* Ignore hotplug events */
  327. unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
  328. controlled exclusively by
  329. user sysfs */
  330. unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
  331. bit manually */
  332. unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
  333. unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
  334. #ifdef CONFIG_PCIEASPM
  335. struct pcie_link_state *link_state; /* ASPM link state */
  336. unsigned int ltr_path:1; /* Latency Tolerance Reporting
  337. supported from root to here */
  338. int l1ss; /* L1SS Capability pointer */
  339. #endif
  340. unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
  341. pci_channel_state_t error_state; /* Current connectivity state */
  342. struct device dev; /* Generic device interface */
  343. int cfg_size; /* Size of config space */
  344. /*
  345. * Instead of touching interrupt line and base address registers
  346. * directly, use the values stored here. They might be different!
  347. */
  348. unsigned int irq;
  349. struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
  350. bool match_driver; /* Skip attaching driver */
  351. unsigned int transparent:1; /* Subtractive decode bridge */
  352. unsigned int io_window:1; /* Bridge has I/O window */
  353. unsigned int pref_window:1; /* Bridge has pref mem window */
  354. unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
  355. unsigned int multifunction:1; /* Multi-function device */
  356. unsigned int is_busmaster:1; /* Is busmaster */
  357. unsigned int no_msi:1; /* May not use MSI */
  358. unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
  359. unsigned int block_cfg_access:1; /* Config space access blocked */
  360. unsigned int broken_parity_status:1; /* Generates false positive parity */
  361. unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
  362. unsigned int msi_enabled:1;
  363. unsigned int msix_enabled:1;
  364. unsigned int ari_enabled:1; /* ARI forwarding */
  365. unsigned int ats_enabled:1; /* Address Translation Svc */
  366. unsigned int pasid_enabled:1; /* Process Address Space ID */
  367. unsigned int pri_enabled:1; /* Page Request Interface */
  368. unsigned int is_managed:1;
  369. unsigned int needs_freset:1; /* Requires fundamental reset */
  370. unsigned int state_saved:1;
  371. unsigned int is_physfn:1;
  372. unsigned int is_virtfn:1;
  373. unsigned int reset_fn:1;
  374. unsigned int is_hotplug_bridge:1;
  375. unsigned int shpc_managed:1; /* SHPC owned by shpchp */
  376. unsigned int is_thunderbolt:1; /* Thunderbolt controller */
  377. /*
  378. * Devices marked being untrusted are the ones that can potentially
  379. * execute DMA attacks and similar. They are typically connected
  380. * through external ports such as Thunderbolt but not limited to
  381. * that. When an IOMMU is enabled they should be getting full
  382. * mappings to make sure they cannot access arbitrary memory.
  383. */
  384. unsigned int untrusted:1;
  385. /*
  386. * Info from the platform, e.g., ACPI or device tree, may mark a
  387. * device as "external-facing". An external-facing device is
  388. * itself internal but devices downstream from it are external.
  389. */
  390. unsigned int external_facing:1;
  391. unsigned int broken_intx_masking:1; /* INTx masking can't be used */
  392. unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
  393. unsigned int irq_managed:1;
  394. unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
  395. unsigned int is_probed:1; /* Device probing in progress */
  396. unsigned int link_active_reporting:1;/* Device capable of reporting link active */
  397. unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
  398. unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
  399. pci_dev_flags_t dev_flags;
  400. atomic_t enable_cnt; /* pci_enable_device has been called */
  401. u32 saved_config_space[16]; /* Config space saved at suspend time */
  402. struct hlist_head saved_cap_space;
  403. struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
  404. int rom_attr_enabled; /* Display of ROM attribute enabled? */
  405. struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
  406. struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
  407. #ifdef CONFIG_HOTPLUG_PCI_PCIE
  408. unsigned int broken_cmd_compl:1; /* No compl for some cmds */
  409. #endif
  410. #ifdef CONFIG_PCIE_PTM
  411. unsigned int ptm_root:1;
  412. unsigned int ptm_enabled:1;
  413. u8 ptm_granularity;
  414. #endif
  415. #ifdef CONFIG_PCI_MSI
  416. const struct attribute_group **msi_irq_groups;
  417. #endif
  418. struct pci_vpd *vpd;
  419. #ifdef CONFIG_PCIE_DPC
  420. u16 dpc_cap;
  421. unsigned int dpc_rp_extensions:1;
  422. u8 dpc_rp_log_size;
  423. #endif
  424. #ifdef CONFIG_PCI_ATS
  425. union {
  426. struct pci_sriov *sriov; /* PF: SR-IOV info */
  427. struct pci_dev *physfn; /* VF: related PF */
  428. };
  429. u16 ats_cap; /* ATS Capability offset */
  430. u8 ats_stu; /* ATS Smallest Translation Unit */
  431. #endif
  432. #ifdef CONFIG_PCI_PRI
  433. u16 pri_cap; /* PRI Capability offset */
  434. u32 pri_reqs_alloc; /* Number of PRI requests allocated */
  435. unsigned int pasid_required:1; /* PRG Response PASID Required */
  436. #endif
  437. #ifdef CONFIG_PCI_PASID
  438. u16 pasid_cap; /* PASID Capability offset */
  439. u16 pasid_features;
  440. #endif
  441. #ifdef CONFIG_PCI_P2PDMA
  442. struct pci_p2pdma *p2pdma;
  443. #endif
  444. u16 acs_cap; /* ACS Capability offset */
  445. phys_addr_t rom; /* Physical address if not from BAR */
  446. size_t romlen; /* Length if not from BAR */
  447. char *driver_override; /* Driver name to force a match */
  448. unsigned long priv_flags; /* Private flags for the PCI driver */
  449. ANDROID_KABI_RESERVE(1);
  450. ANDROID_KABI_RESERVE(2);
  451. ANDROID_KABI_RESERVE(3);
  452. ANDROID_KABI_RESERVE(4);
  453. };
  454. static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
  455. {
  456. #ifdef CONFIG_PCI_IOV
  457. if (dev->is_virtfn)
  458. dev = dev->physfn;
  459. #endif
  460. return dev;
  461. }
  462. struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
  463. #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
  464. #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
  465. static inline int pci_channel_offline(struct pci_dev *pdev)
  466. {
  467. return (pdev->error_state != pci_channel_io_normal);
  468. }
  469. struct pci_host_bridge {
  470. struct device dev;
  471. struct pci_bus *bus; /* Root bus */
  472. struct pci_ops *ops;
  473. struct pci_ops *child_ops;
  474. void *sysdata;
  475. int busnr;
  476. struct list_head windows; /* resource_entry */
  477. struct list_head dma_ranges; /* dma ranges resource list */
  478. u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
  479. int (*map_irq)(const struct pci_dev *, u8, u8);
  480. void (*release_fn)(struct pci_host_bridge *);
  481. void *release_data;
  482. struct msi_controller *msi;
  483. unsigned int ignore_reset_delay:1; /* For entire hierarchy */
  484. unsigned int no_ext_tags:1; /* No Extended Tags */
  485. unsigned int native_aer:1; /* OS may use PCIe AER */
  486. unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
  487. unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
  488. unsigned int native_pme:1; /* OS may use PCIe PME */
  489. unsigned int native_ltr:1; /* OS may use PCIe LTR */
  490. unsigned int native_dpc:1; /* OS may use PCIe DPC */
  491. unsigned int preserve_config:1; /* Preserve FW resource setup */
  492. unsigned int size_windows:1; /* Enable root bus sizing */
  493. /* Resource alignment requirements */
  494. resource_size_t (*align_resource)(struct pci_dev *dev,
  495. const struct resource *res,
  496. resource_size_t start,
  497. resource_size_t size,
  498. resource_size_t align);
  499. ANDROID_KABI_RESERVE(1);
  500. ANDROID_KABI_RESERVE(2);
  501. unsigned long private[] ____cacheline_aligned;
  502. };
  503. #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
  504. static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
  505. {
  506. return (void *)bridge->private;
  507. }
  508. static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
  509. {
  510. return container_of(priv, struct pci_host_bridge, private);
  511. }
  512. struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
  513. struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
  514. size_t priv);
  515. void pci_free_host_bridge(struct pci_host_bridge *bridge);
  516. struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
  517. void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
  518. void (*release_fn)(struct pci_host_bridge *),
  519. void *release_data);
  520. int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
  521. /*
  522. * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
  523. * to P2P or CardBus bridge windows) go in a table. Additional ones (for
  524. * buses below host bridges or subtractive decode bridges) go in the list.
  525. * Use pci_bus_for_each_resource() to iterate through all the resources.
  526. */
  527. /*
  528. * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
  529. * and there's no way to program the bridge with the details of the window.
  530. * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
  531. * decode bit set, because they are explicit and can be programmed with _SRS.
  532. */
  533. #define PCI_SUBTRACTIVE_DECODE 0x1
  534. struct pci_bus_resource {
  535. struct list_head list;
  536. struct resource *res;
  537. unsigned int flags;
  538. };
  539. #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
  540. struct pci_bus {
  541. struct list_head node; /* Node in list of buses */
  542. struct pci_bus *parent; /* Parent bus this bridge is on */
  543. struct list_head children; /* List of child buses */
  544. struct list_head devices; /* List of devices on this bus */
  545. struct pci_dev *self; /* Bridge device as seen by parent */
  546. struct list_head slots; /* List of slots on this bus;
  547. protected by pci_slot_mutex */
  548. struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
  549. struct list_head resources; /* Address space routed to this bus */
  550. struct resource busn_res; /* Bus numbers routed to this bus */
  551. struct pci_ops *ops; /* Configuration access functions */
  552. struct msi_controller *msi; /* MSI controller */
  553. void *sysdata; /* Hook for sys-specific extension */
  554. struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
  555. unsigned char number; /* Bus number */
  556. unsigned char primary; /* Number of primary bridge */
  557. unsigned char max_bus_speed; /* enum pci_bus_speed */
  558. unsigned char cur_bus_speed; /* enum pci_bus_speed */
  559. #ifdef CONFIG_PCI_DOMAINS_GENERIC
  560. int domain_nr;
  561. #endif
  562. char name[48];
  563. unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
  564. pci_bus_flags_t bus_flags; /* Inherited by child buses */
  565. struct device *bridge;
  566. struct device dev;
  567. struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
  568. struct bin_attribute *legacy_mem; /* Legacy mem */
  569. unsigned int is_added:1;
  570. ANDROID_KABI_RESERVE(1);
  571. ANDROID_KABI_RESERVE(2);
  572. ANDROID_KABI_RESERVE(3);
  573. ANDROID_KABI_RESERVE(4);
  574. };
  575. #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
  576. static inline u16 pci_dev_id(struct pci_dev *dev)
  577. {
  578. return PCI_DEVID(dev->bus->number, dev->devfn);
  579. }
  580. /*
  581. * Returns true if the PCI bus is root (behind host-PCI bridge),
  582. * false otherwise
  583. *
  584. * Some code assumes that "bus->self == NULL" means that bus is a root bus.
  585. * This is incorrect because "virtual" buses added for SR-IOV (via
  586. * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
  587. */
  588. static inline bool pci_is_root_bus(struct pci_bus *pbus)
  589. {
  590. return !(pbus->parent);
  591. }
  592. /**
  593. * pci_is_bridge - check if the PCI device is a bridge
  594. * @dev: PCI device
  595. *
  596. * Return true if the PCI device is bridge whether it has subordinate
  597. * or not.
  598. */
  599. static inline bool pci_is_bridge(struct pci_dev *dev)
  600. {
  601. return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
  602. dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
  603. }
  604. #define for_each_pci_bridge(dev, bus) \
  605. list_for_each_entry(dev, &bus->devices, bus_list) \
  606. if (!pci_is_bridge(dev)) {} else
  607. static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
  608. {
  609. dev = pci_physfn(dev);
  610. if (pci_is_root_bus(dev->bus))
  611. return NULL;
  612. return dev->bus->self;
  613. }
  614. #ifdef CONFIG_PCI_MSI
  615. static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
  616. {
  617. return pci_dev->msi_enabled || pci_dev->msix_enabled;
  618. }
  619. #else
  620. static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
  621. #endif
  622. /* Error values that may be returned by PCI functions */
  623. #define PCIBIOS_SUCCESSFUL 0x00
  624. #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
  625. #define PCIBIOS_BAD_VENDOR_ID 0x83
  626. #define PCIBIOS_DEVICE_NOT_FOUND 0x86
  627. #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
  628. #define PCIBIOS_SET_FAILED 0x88
  629. #define PCIBIOS_BUFFER_TOO_SMALL 0x89
  630. /* Translate above to generic errno for passing back through non-PCI code */
  631. static inline int pcibios_err_to_errno(int err)
  632. {
  633. if (err <= PCIBIOS_SUCCESSFUL)
  634. return err; /* Assume already errno */
  635. switch (err) {
  636. case PCIBIOS_FUNC_NOT_SUPPORTED:
  637. return -ENOENT;
  638. case PCIBIOS_BAD_VENDOR_ID:
  639. return -ENOTTY;
  640. case PCIBIOS_DEVICE_NOT_FOUND:
  641. return -ENODEV;
  642. case PCIBIOS_BAD_REGISTER_NUMBER:
  643. return -EFAULT;
  644. case PCIBIOS_SET_FAILED:
  645. return -EIO;
  646. case PCIBIOS_BUFFER_TOO_SMALL:
  647. return -ENOSPC;
  648. }
  649. return -ERANGE;
  650. }
  651. /* Low-level architecture-dependent routines */
  652. struct pci_ops {
  653. int (*add_bus)(struct pci_bus *bus);
  654. void (*remove_bus)(struct pci_bus *bus);
  655. void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
  656. int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
  657. int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
  658. ANDROID_KABI_RESERVE(1);
  659. };
  660. /*
  661. * ACPI needs to be able to access PCI config space before we've done a
  662. * PCI bus scan and created pci_bus structures.
  663. */
  664. int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
  665. int reg, int len, u32 *val);
  666. int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
  667. int reg, int len, u32 val);
  668. #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
  669. typedef u64 pci_bus_addr_t;
  670. #else
  671. typedef u32 pci_bus_addr_t;
  672. #endif
  673. struct pci_bus_region {
  674. pci_bus_addr_t start;
  675. pci_bus_addr_t end;
  676. };
  677. struct pci_dynids {
  678. spinlock_t lock; /* Protects list, index */
  679. struct list_head list; /* For IDs added at runtime */
  680. };
  681. /*
  682. * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
  683. * a set of callbacks in struct pci_error_handlers, that device driver
  684. * will be notified of PCI bus errors, and will be driven to recovery
  685. * when an error occurs.
  686. */
  687. typedef unsigned int __bitwise pci_ers_result_t;
  688. enum pci_ers_result {
  689. /* No result/none/not supported in device driver */
  690. PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
  691. /* Device driver can recover without slot reset */
  692. PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
  693. /* Device driver wants slot to be reset */
  694. PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
  695. /* Device has completely failed, is unrecoverable */
  696. PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
  697. /* Device driver is fully recovered and operational */
  698. PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
  699. /* No AER capabilities registered for the driver */
  700. PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
  701. };
  702. /* PCI bus error event callbacks */
  703. struct pci_error_handlers {
  704. /* PCI bus error detected on this device */
  705. pci_ers_result_t (*error_detected)(struct pci_dev *dev,
  706. pci_channel_state_t error);
  707. /* MMIO has been re-enabled, but not DMA */
  708. pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
  709. /* PCI slot has been reset */
  710. pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
  711. /* PCI function reset prepare or completed */
  712. void (*reset_prepare)(struct pci_dev *dev);
  713. void (*reset_done)(struct pci_dev *dev);
  714. /* Device driver may resume normal operations */
  715. void (*resume)(struct pci_dev *dev);
  716. ANDROID_KABI_RESERVE(1);
  717. };
  718. struct module;
  719. /**
  720. * struct pci_driver - PCI driver structure
  721. * @node: List of driver structures.
  722. * @name: Driver name.
  723. * @id_table: Pointer to table of device IDs the driver is
  724. * interested in. Most drivers should export this
  725. * table using MODULE_DEVICE_TABLE(pci,...).
  726. * @probe: This probing function gets called (during execution
  727. * of pci_register_driver() for already existing
  728. * devices or later if a new device gets inserted) for
  729. * all PCI devices which match the ID table and are not
  730. * "owned" by the other drivers yet. This function gets
  731. * passed a "struct pci_dev \*" for each device whose
  732. * entry in the ID table matches the device. The probe
  733. * function returns zero when the driver chooses to
  734. * take "ownership" of the device or an error code
  735. * (negative number) otherwise.
  736. * The probe function always gets called from process
  737. * context, so it can sleep.
  738. * @remove: The remove() function gets called whenever a device
  739. * being handled by this driver is removed (either during
  740. * deregistration of the driver or when it's manually
  741. * pulled out of a hot-pluggable slot).
  742. * The remove function always gets called from process
  743. * context, so it can sleep.
  744. * @suspend: Put device into low power state.
  745. * @resume: Wake device from low power state.
  746. * (Please see Documentation/power/pci.rst for descriptions
  747. * of PCI Power Management and the related functions.)
  748. * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
  749. * Intended to stop any idling DMA operations.
  750. * Useful for enabling wake-on-lan (NIC) or changing
  751. * the power state of a device before reboot.
  752. * e.g. drivers/net/e100.c.
  753. * @sriov_configure: Optional driver callback to allow configuration of
  754. * number of VFs to enable via sysfs "sriov_numvfs" file.
  755. * @err_handler: See Documentation/PCI/pci-error-recovery.rst
  756. * @groups: Sysfs attribute groups.
  757. * @driver: Driver model structure.
  758. * @dynids: List of dynamically added device IDs.
  759. */
  760. struct pci_driver {
  761. struct list_head node;
  762. const char *name;
  763. const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
  764. int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
  765. void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
  766. int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
  767. int (*resume)(struct pci_dev *dev); /* Device woken up */
  768. void (*shutdown)(struct pci_dev *dev);
  769. int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
  770. const struct pci_error_handlers *err_handler;
  771. const struct attribute_group **groups;
  772. struct device_driver driver;
  773. struct pci_dynids dynids;
  774. ANDROID_KABI_RESERVE(1);
  775. ANDROID_KABI_RESERVE(2);
  776. ANDROID_KABI_RESERVE(3);
  777. ANDROID_KABI_RESERVE(4);
  778. };
  779. #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
  780. /**
  781. * PCI_DEVICE - macro used to describe a specific PCI device
  782. * @vend: the 16 bit PCI Vendor ID
  783. * @dev: the 16 bit PCI Device ID
  784. *
  785. * This macro is used to create a struct pci_device_id that matches a
  786. * specific device. The subvendor and subdevice fields will be set to
  787. * PCI_ANY_ID.
  788. */
  789. #define PCI_DEVICE(vend,dev) \
  790. .vendor = (vend), .device = (dev), \
  791. .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
  792. /**
  793. * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
  794. * @vend: the 16 bit PCI Vendor ID
  795. * @dev: the 16 bit PCI Device ID
  796. * @subvend: the 16 bit PCI Subvendor ID
  797. * @subdev: the 16 bit PCI Subdevice ID
  798. *
  799. * This macro is used to create a struct pci_device_id that matches a
  800. * specific device with subsystem information.
  801. */
  802. #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
  803. .vendor = (vend), .device = (dev), \
  804. .subvendor = (subvend), .subdevice = (subdev)
  805. /**
  806. * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
  807. * @dev_class: the class, subclass, prog-if triple for this device
  808. * @dev_class_mask: the class mask for this device
  809. *
  810. * This macro is used to create a struct pci_device_id that matches a
  811. * specific PCI class. The vendor, device, subvendor, and subdevice
  812. * fields will be set to PCI_ANY_ID.
  813. */
  814. #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
  815. .class = (dev_class), .class_mask = (dev_class_mask), \
  816. .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
  817. .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
  818. /**
  819. * PCI_VDEVICE - macro used to describe a specific PCI device in short form
  820. * @vend: the vendor name
  821. * @dev: the 16 bit PCI Device ID
  822. *
  823. * This macro is used to create a struct pci_device_id that matches a
  824. * specific PCI device. The subvendor, and subdevice fields will be set
  825. * to PCI_ANY_ID. The macro allows the next field to follow as the device
  826. * private data.
  827. */
  828. #define PCI_VDEVICE(vend, dev) \
  829. .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
  830. .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
  831. /**
  832. * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
  833. * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
  834. * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
  835. * @data: the driver data to be filled
  836. *
  837. * This macro is used to create a struct pci_device_id that matches a
  838. * specific PCI device. The subvendor, and subdevice fields will be set
  839. * to PCI_ANY_ID.
  840. */
  841. #define PCI_DEVICE_DATA(vend, dev, data) \
  842. .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
  843. .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
  844. .driver_data = (kernel_ulong_t)(data)
  845. enum {
  846. PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
  847. PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
  848. PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
  849. PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
  850. PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
  851. PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
  852. PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
  853. };
  854. #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
  855. #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
  856. #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
  857. #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
  858. /* These external functions are only available when PCI support is enabled */
  859. #ifdef CONFIG_PCI
  860. extern unsigned int pci_flags;
  861. static inline void pci_set_flags(int flags) { pci_flags = flags; }
  862. static inline void pci_add_flags(int flags) { pci_flags |= flags; }
  863. static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
  864. static inline int pci_has_flag(int flag) { return pci_flags & flag; }
  865. void pcie_bus_configure_settings(struct pci_bus *bus);
  866. enum pcie_bus_config_types {
  867. PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
  868. PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
  869. PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
  870. PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
  871. PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
  872. };
  873. extern enum pcie_bus_config_types pcie_bus_config;
  874. extern struct bus_type pci_bus_type;
  875. /* Do NOT directly access these two variables, unless you are arch-specific PCI
  876. * code, or PCI core code. */
  877. extern struct list_head pci_root_buses; /* List of all known PCI buses */
  878. /* Some device drivers need know if PCI is initiated */
  879. int no_pci_devices(void);
  880. void pcibios_resource_survey_bus(struct pci_bus *bus);
  881. void pcibios_bus_add_device(struct pci_dev *pdev);
  882. void pcibios_add_bus(struct pci_bus *bus);
  883. void pcibios_remove_bus(struct pci_bus *bus);
  884. void pcibios_fixup_bus(struct pci_bus *);
  885. int __must_check pcibios_enable_device(struct pci_dev *, int mask);
  886. /* Architecture-specific versions may override this (weak) */
  887. char *pcibios_setup(char *str);
  888. /* Used only when drivers/pci/setup.c is used */
  889. resource_size_t pcibios_align_resource(void *, const struct resource *,
  890. resource_size_t,
  891. resource_size_t);
  892. /* Weak but can be overridden by arch */
  893. void pci_fixup_cardbus(struct pci_bus *);
  894. /* Generic PCI functions used internally */
  895. void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
  896. struct resource *res);
  897. void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
  898. struct pci_bus_region *region);
  899. void pcibios_scan_specific_bus(int busn);
  900. struct pci_bus *pci_find_bus(int domain, int busnr);
  901. void pci_bus_add_devices(const struct pci_bus *bus);
  902. struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
  903. struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
  904. struct pci_ops *ops, void *sysdata,
  905. struct list_head *resources);
  906. int pci_host_probe(struct pci_host_bridge *bridge);
  907. int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
  908. int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
  909. void pci_bus_release_busn_res(struct pci_bus *b);
  910. struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
  911. struct pci_ops *ops, void *sysdata,
  912. struct list_head *resources);
  913. int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
  914. struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
  915. int busnr);
  916. struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
  917. const char *name,
  918. struct hotplug_slot *hotplug);
  919. void pci_destroy_slot(struct pci_slot *slot);
  920. #ifdef CONFIG_SYSFS
  921. void pci_dev_assign_slot(struct pci_dev *dev);
  922. #else
  923. static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
  924. #endif
  925. int pci_scan_slot(struct pci_bus *bus, int devfn);
  926. struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
  927. void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
  928. unsigned int pci_scan_child_bus(struct pci_bus *bus);
  929. void pci_bus_add_device(struct pci_dev *dev);
  930. void pci_read_bridge_bases(struct pci_bus *child);
  931. struct resource *pci_find_parent_resource(const struct pci_dev *dev,
  932. struct resource *res);
  933. u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
  934. int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
  935. u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
  936. struct pci_dev *pci_dev_get(struct pci_dev *dev);
  937. void pci_dev_put(struct pci_dev *dev);
  938. void pci_remove_bus(struct pci_bus *b);
  939. void pci_stop_and_remove_bus_device(struct pci_dev *dev);
  940. void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
  941. void pci_stop_root_bus(struct pci_bus *bus);
  942. void pci_remove_root_bus(struct pci_bus *bus);
  943. void pci_setup_cardbus(struct pci_bus *bus);
  944. void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
  945. void pci_sort_breadthfirst(void);
  946. #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
  947. #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
  948. /* Generic PCI functions exported to card drivers */
  949. int pci_find_capability(struct pci_dev *dev, int cap);
  950. int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
  951. int pci_find_ext_capability(struct pci_dev *dev, int cap);
  952. int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
  953. int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
  954. int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
  955. struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
  956. u64 pci_get_dsn(struct pci_dev *dev);
  957. struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
  958. struct pci_dev *from);
  959. struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
  960. unsigned int ss_vendor, unsigned int ss_device,
  961. struct pci_dev *from);
  962. struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
  963. struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
  964. unsigned int devfn);
  965. struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
  966. int pci_dev_present(const struct pci_device_id *ids);
  967. int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
  968. int where, u8 *val);
  969. int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
  970. int where, u16 *val);
  971. int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
  972. int where, u32 *val);
  973. int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
  974. int where, u8 val);
  975. int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
  976. int where, u16 val);
  977. int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
  978. int where, u32 val);
  979. int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
  980. int where, int size, u32 *val);
  981. int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
  982. int where, int size, u32 val);
  983. int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
  984. int where, int size, u32 *val);
  985. int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
  986. int where, int size, u32 val);
  987. struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
  988. int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
  989. int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
  990. int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
  991. int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
  992. int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
  993. int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
  994. int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
  995. int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
  996. int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
  997. int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
  998. int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
  999. u16 clear, u16 set);
  1000. int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
  1001. u32 clear, u32 set);
  1002. static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
  1003. u16 set)
  1004. {
  1005. return pcie_capability_clear_and_set_word(dev, pos, 0, set);
  1006. }
  1007. static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
  1008. u32 set)
  1009. {
  1010. return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
  1011. }
  1012. static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
  1013. u16 clear)
  1014. {
  1015. return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
  1016. }
  1017. static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
  1018. u32 clear)
  1019. {
  1020. return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
  1021. }
  1022. /* User-space driven config access */
  1023. int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
  1024. int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
  1025. int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
  1026. int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
  1027. int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
  1028. int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
  1029. int __must_check pci_enable_device(struct pci_dev *dev);
  1030. int __must_check pci_enable_device_io(struct pci_dev *dev);
  1031. int __must_check pci_enable_device_mem(struct pci_dev *dev);
  1032. int __must_check pci_reenable_device(struct pci_dev *);
  1033. int __must_check pcim_enable_device(struct pci_dev *pdev);
  1034. void pcim_pin_device(struct pci_dev *pdev);
  1035. static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
  1036. {
  1037. /*
  1038. * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
  1039. * writable and no quirk has marked the feature broken.
  1040. */
  1041. return !pdev->broken_intx_masking;
  1042. }
  1043. static inline int pci_is_enabled(struct pci_dev *pdev)
  1044. {
  1045. return (atomic_read(&pdev->enable_cnt) > 0);
  1046. }
  1047. static inline int pci_is_managed(struct pci_dev *pdev)
  1048. {
  1049. return pdev->is_managed;
  1050. }
  1051. void pci_disable_device(struct pci_dev *dev);
  1052. extern unsigned int pcibios_max_latency;
  1053. void pci_set_master(struct pci_dev *dev);
  1054. void pci_clear_master(struct pci_dev *dev);
  1055. int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
  1056. int pci_set_cacheline_size(struct pci_dev *dev);
  1057. #define HAVE_PCI_SET_MWI
  1058. int __must_check pci_set_mwi(struct pci_dev *dev);
  1059. int __must_check pcim_set_mwi(struct pci_dev *dev);
  1060. int pci_try_set_mwi(struct pci_dev *dev);
  1061. void pci_clear_mwi(struct pci_dev *dev);
  1062. void pci_intx(struct pci_dev *dev, int enable);
  1063. bool pci_check_and_mask_intx(struct pci_dev *dev);
  1064. bool pci_check_and_unmask_intx(struct pci_dev *dev);
  1065. int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
  1066. int pci_wait_for_pending_transaction(struct pci_dev *dev);
  1067. int pcix_get_max_mmrbc(struct pci_dev *dev);
  1068. int pcix_get_mmrbc(struct pci_dev *dev);
  1069. int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
  1070. int pcie_get_readrq(struct pci_dev *dev);
  1071. int pcie_set_readrq(struct pci_dev *dev, int rq);
  1072. int pcie_get_mps(struct pci_dev *dev);
  1073. int pcie_set_mps(struct pci_dev *dev, int mps);
  1074. u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
  1075. enum pci_bus_speed *speed,
  1076. enum pcie_link_width *width);
  1077. void pcie_print_link_status(struct pci_dev *dev);
  1078. bool pcie_has_flr(struct pci_dev *dev);
  1079. int pcie_flr(struct pci_dev *dev);
  1080. int __pci_reset_function_locked(struct pci_dev *dev);
  1081. int pci_reset_function(struct pci_dev *dev);
  1082. int pci_reset_function_locked(struct pci_dev *dev);
  1083. int pci_try_reset_function(struct pci_dev *dev);
  1084. int pci_probe_reset_slot(struct pci_slot *slot);
  1085. int pci_probe_reset_bus(struct pci_bus *bus);
  1086. int pci_reset_bus(struct pci_dev *dev);
  1087. void pci_reset_secondary_bus(struct pci_dev *dev);
  1088. void pcibios_reset_secondary_bus(struct pci_dev *dev);
  1089. void pci_update_resource(struct pci_dev *dev, int resno);
  1090. int __must_check pci_assign_resource(struct pci_dev *dev, int i);
  1091. int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
  1092. void pci_release_resource(struct pci_dev *dev, int resno);
  1093. int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
  1094. int pci_select_bars(struct pci_dev *dev, unsigned long flags);
  1095. bool pci_device_is_present(struct pci_dev *pdev);
  1096. void pci_ignore_hotplug(struct pci_dev *dev);
  1097. struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
  1098. int pci_status_get_and_clear_errors(struct pci_dev *pdev);
  1099. int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
  1100. irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
  1101. const char *fmt, ...);
  1102. void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
  1103. /* ROM control related routines */
  1104. int pci_enable_rom(struct pci_dev *pdev);
  1105. void pci_disable_rom(struct pci_dev *pdev);
  1106. void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
  1107. void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
  1108. /* Power management related routines */
  1109. int pci_save_state(struct pci_dev *dev);
  1110. void pci_restore_state(struct pci_dev *dev);
  1111. struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
  1112. int pci_load_saved_state(struct pci_dev *dev,
  1113. struct pci_saved_state *state);
  1114. int pci_load_and_free_saved_state(struct pci_dev *dev,
  1115. struct pci_saved_state **state);
  1116. struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
  1117. struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
  1118. u16 cap);
  1119. int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
  1120. int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
  1121. u16 cap, unsigned int size);
  1122. int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
  1123. int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
  1124. pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
  1125. bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
  1126. void pci_pme_active(struct pci_dev *dev, bool enable);
  1127. int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
  1128. int pci_wake_from_d3(struct pci_dev *dev, bool enable);
  1129. int pci_prepare_to_sleep(struct pci_dev *dev);
  1130. int pci_back_from_sleep(struct pci_dev *dev);
  1131. bool pci_dev_run_wake(struct pci_dev *dev);
  1132. void pci_d3cold_enable(struct pci_dev *dev);
  1133. void pci_d3cold_disable(struct pci_dev *dev);
  1134. bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
  1135. void pci_wakeup_bus(struct pci_bus *bus);
  1136. void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
  1137. /* For use by arch with custom probe code */
  1138. void set_pcie_port_type(struct pci_dev *pdev);
  1139. void set_pcie_hotplug_bridge(struct pci_dev *pdev);
  1140. /* Functions for PCI Hotplug drivers to use */
  1141. int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
  1142. unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
  1143. unsigned int pci_rescan_bus(struct pci_bus *bus);
  1144. void pci_lock_rescan_remove(void);
  1145. void pci_unlock_rescan_remove(void);
  1146. /* Vital Product Data routines */
  1147. ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
  1148. ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
  1149. int pci_set_vpd_size(struct pci_dev *dev, size_t len);
  1150. /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
  1151. resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
  1152. void pci_bus_assign_resources(const struct pci_bus *bus);
  1153. void pci_bus_claim_resources(struct pci_bus *bus);
  1154. void pci_bus_size_bridges(struct pci_bus *bus);
  1155. int pci_claim_resource(struct pci_dev *, int);
  1156. int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
  1157. void pci_assign_unassigned_resources(void);
  1158. void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
  1159. void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
  1160. void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
  1161. int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
  1162. void pdev_enable_device(struct pci_dev *);
  1163. int pci_enable_resources(struct pci_dev *, int mask);
  1164. void pci_assign_irq(struct pci_dev *dev);
  1165. struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
  1166. #define HAVE_PCI_REQ_REGIONS 2
  1167. int __must_check pci_request_regions(struct pci_dev *, const char *);
  1168. int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
  1169. void pci_release_regions(struct pci_dev *);
  1170. int __must_check pci_request_region(struct pci_dev *, int, const char *);
  1171. void pci_release_region(struct pci_dev *, int);
  1172. int pci_request_selected_regions(struct pci_dev *, int, const char *);
  1173. int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
  1174. void pci_release_selected_regions(struct pci_dev *, int);
  1175. /* drivers/pci/bus.c */
  1176. void pci_add_resource(struct list_head *resources, struct resource *res);
  1177. void pci_add_resource_offset(struct list_head *resources, struct resource *res,
  1178. resource_size_t offset);
  1179. void pci_free_resource_list(struct list_head *resources);
  1180. void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
  1181. unsigned int flags);
  1182. struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
  1183. void pci_bus_remove_resources(struct pci_bus *bus);
  1184. int devm_request_pci_bus_resources(struct device *dev,
  1185. struct list_head *resources);
  1186. /* Temporary until new and working PCI SBR API in place */
  1187. int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
  1188. #define pci_bus_for_each_resource(bus, res, i) \
  1189. for (i = 0; \
  1190. (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
  1191. i++)
  1192. int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
  1193. struct resource *res, resource_size_t size,
  1194. resource_size_t align, resource_size_t min,
  1195. unsigned long type_mask,
  1196. resource_size_t (*alignf)(void *,
  1197. const struct resource *,
  1198. resource_size_t,
  1199. resource_size_t),
  1200. void *alignf_data);
  1201. int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
  1202. resource_size_t size);
  1203. unsigned long pci_address_to_pio(phys_addr_t addr);
  1204. phys_addr_t pci_pio_to_address(unsigned long pio);
  1205. int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
  1206. int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
  1207. phys_addr_t phys_addr);
  1208. void pci_unmap_iospace(struct resource *res);
  1209. void __iomem *devm_pci_remap_cfgspace(struct device *dev,
  1210. resource_size_t offset,
  1211. resource_size_t size);
  1212. void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
  1213. struct resource *res);
  1214. static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
  1215. {
  1216. struct pci_bus_region region;
  1217. pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]);
  1218. return region.start;
  1219. }
  1220. /* Proper probing supporting hot-pluggable devices */
  1221. int __must_check __pci_register_driver(struct pci_driver *, struct module *,
  1222. const char *mod_name);
  1223. /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
  1224. #define pci_register_driver(driver) \
  1225. __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
  1226. void pci_unregister_driver(struct pci_driver *dev);
  1227. /**
  1228. * module_pci_driver() - Helper macro for registering a PCI driver
  1229. * @__pci_driver: pci_driver struct
  1230. *
  1231. * Helper macro for PCI drivers which do not do anything special in module
  1232. * init/exit. This eliminates a lot of boilerplate. Each module may only
  1233. * use this macro once, and calling it replaces module_init() and module_exit()
  1234. */
  1235. #define module_pci_driver(__pci_driver) \
  1236. module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
  1237. /**
  1238. * builtin_pci_driver() - Helper macro for registering a PCI driver
  1239. * @__pci_driver: pci_driver struct
  1240. *
  1241. * Helper macro for PCI drivers which do not do anything special in their
  1242. * init code. This eliminates a lot of boilerplate. Each driver may only
  1243. * use this macro once, and calling it replaces device_initcall(...)
  1244. */
  1245. #define builtin_pci_driver(__pci_driver) \
  1246. builtin_driver(__pci_driver, pci_register_driver)
  1247. struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
  1248. int pci_add_dynid(struct pci_driver *drv,
  1249. unsigned int vendor, unsigned int device,
  1250. unsigned int subvendor, unsigned int subdevice,
  1251. unsigned int class, unsigned int class_mask,
  1252. unsigned long driver_data);
  1253. const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
  1254. struct pci_dev *dev);
  1255. int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
  1256. int pass);
  1257. void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
  1258. void *userdata);
  1259. int pci_cfg_space_size(struct pci_dev *dev);
  1260. unsigned char pci_bus_max_busnr(struct pci_bus *bus);
  1261. void pci_setup_bridge(struct pci_bus *bus);
  1262. resource_size_t pcibios_window_alignment(struct pci_bus *bus,
  1263. unsigned long type);
  1264. #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
  1265. #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
  1266. int pci_set_vga_state(struct pci_dev *pdev, bool decode,
  1267. unsigned int command_bits, u32 flags);
  1268. /*
  1269. * Virtual interrupts allow for more interrupts to be allocated
  1270. * than the device has interrupts for. These are not programmed
  1271. * into the device's MSI-X table and must be handled by some
  1272. * other driver means.
  1273. */
  1274. #define PCI_IRQ_VIRTUAL (1 << 4)
  1275. #define PCI_IRQ_ALL_TYPES \
  1276. (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
  1277. /* kmem_cache style wrapper around pci_alloc_consistent() */
  1278. #include <linux/dmapool.h>
  1279. #define pci_pool dma_pool
  1280. #define pci_pool_create(name, pdev, size, align, allocation) \
  1281. dma_pool_create(name, &pdev->dev, size, align, allocation)
  1282. #define pci_pool_destroy(pool) dma_pool_destroy(pool)
  1283. #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
  1284. #define pci_pool_zalloc(pool, flags, handle) \
  1285. dma_pool_zalloc(pool, flags, handle)
  1286. #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
  1287. struct msix_entry {
  1288. u32 vector; /* Kernel uses to write allocated vector */
  1289. u16 entry; /* Driver uses to specify entry, OS writes */
  1290. };
  1291. #ifdef CONFIG_PCI_MSI
  1292. int pci_msi_vec_count(struct pci_dev *dev);
  1293. void pci_disable_msi(struct pci_dev *dev);
  1294. int pci_msix_vec_count(struct pci_dev *dev);
  1295. void pci_disable_msix(struct pci_dev *dev);
  1296. void pci_restore_msi_state(struct pci_dev *dev);
  1297. int pci_msi_enabled(void);
  1298. int pci_enable_msi(struct pci_dev *dev);
  1299. int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
  1300. int minvec, int maxvec);
  1301. static inline int pci_enable_msix_exact(struct pci_dev *dev,
  1302. struct msix_entry *entries, int nvec)
  1303. {
  1304. int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
  1305. if (rc < 0)
  1306. return rc;
  1307. return 0;
  1308. }
  1309. int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
  1310. unsigned int max_vecs, unsigned int flags,
  1311. struct irq_affinity *affd);
  1312. void pci_free_irq_vectors(struct pci_dev *dev);
  1313. int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
  1314. const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
  1315. #else
  1316. static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
  1317. static inline void pci_disable_msi(struct pci_dev *dev) { }
  1318. static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
  1319. static inline void pci_disable_msix(struct pci_dev *dev) { }
  1320. static inline void pci_restore_msi_state(struct pci_dev *dev) { }
  1321. static inline int pci_msi_enabled(void) { return 0; }
  1322. static inline int pci_enable_msi(struct pci_dev *dev)
  1323. { return -ENOSYS; }
  1324. static inline int pci_enable_msix_range(struct pci_dev *dev,
  1325. struct msix_entry *entries, int minvec, int maxvec)
  1326. { return -ENOSYS; }
  1327. static inline int pci_enable_msix_exact(struct pci_dev *dev,
  1328. struct msix_entry *entries, int nvec)
  1329. { return -ENOSYS; }
  1330. static inline int
  1331. pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
  1332. unsigned int max_vecs, unsigned int flags,
  1333. struct irq_affinity *aff_desc)
  1334. {
  1335. if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
  1336. return 1;
  1337. return -ENOSPC;
  1338. }
  1339. static inline void pci_free_irq_vectors(struct pci_dev *dev)
  1340. {
  1341. }
  1342. static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
  1343. {
  1344. if (WARN_ON_ONCE(nr > 0))
  1345. return -EINVAL;
  1346. return dev->irq;
  1347. }
  1348. static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
  1349. int vec)
  1350. {
  1351. return cpu_possible_mask;
  1352. }
  1353. #endif
  1354. /**
  1355. * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
  1356. * @d: the INTx IRQ domain
  1357. * @node: the DT node for the device whose interrupt we're translating
  1358. * @intspec: the interrupt specifier data from the DT
  1359. * @intsize: the number of entries in @intspec
  1360. * @out_hwirq: pointer at which to write the hwirq number
  1361. * @out_type: pointer at which to write the interrupt type
  1362. *
  1363. * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
  1364. * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
  1365. * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
  1366. * INTx value to obtain the hwirq number.
  1367. *
  1368. * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
  1369. */
  1370. static inline int pci_irqd_intx_xlate(struct irq_domain *d,
  1371. struct device_node *node,
  1372. const u32 *intspec,
  1373. unsigned int intsize,
  1374. unsigned long *out_hwirq,
  1375. unsigned int *out_type)
  1376. {
  1377. const u32 intx = intspec[0];
  1378. if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
  1379. return -EINVAL;
  1380. *out_hwirq = intx - PCI_INTERRUPT_INTA;
  1381. return 0;
  1382. }
  1383. #ifdef CONFIG_PCIEPORTBUS
  1384. extern bool pcie_ports_disabled;
  1385. extern bool pcie_ports_native;
  1386. #else
  1387. #define pcie_ports_disabled true
  1388. #define pcie_ports_native false
  1389. #endif
  1390. #define PCIE_LINK_STATE_L0S BIT(0)
  1391. #define PCIE_LINK_STATE_L1 BIT(1)
  1392. #define PCIE_LINK_STATE_CLKPM BIT(2)
  1393. #define PCIE_LINK_STATE_L1_1 BIT(3)
  1394. #define PCIE_LINK_STATE_L1_2 BIT(4)
  1395. #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
  1396. #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
  1397. #ifdef CONFIG_PCIEASPM
  1398. int pci_disable_link_state(struct pci_dev *pdev, int state);
  1399. int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
  1400. void pcie_no_aspm(void);
  1401. bool pcie_aspm_support_enabled(void);
  1402. bool pcie_aspm_enabled(struct pci_dev *pdev);
  1403. #else
  1404. static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
  1405. { return 0; }
  1406. static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
  1407. { return 0; }
  1408. static inline void pcie_no_aspm(void) { }
  1409. static inline bool pcie_aspm_support_enabled(void) { return false; }
  1410. static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
  1411. #endif
  1412. #ifdef CONFIG_PCIEAER
  1413. bool pci_aer_available(void);
  1414. #else
  1415. static inline bool pci_aer_available(void) { return false; }
  1416. #endif
  1417. bool pci_ats_disabled(void);
  1418. void pci_cfg_access_lock(struct pci_dev *dev);
  1419. bool pci_cfg_access_trylock(struct pci_dev *dev);
  1420. void pci_cfg_access_unlock(struct pci_dev *dev);
  1421. /*
  1422. * PCI domain support. Sometimes called PCI segment (eg by ACPI),
  1423. * a PCI domain is defined to be a set of PCI buses which share
  1424. * configuration space.
  1425. */
  1426. #ifdef CONFIG_PCI_DOMAINS
  1427. extern int pci_domains_supported;
  1428. #else
  1429. enum { pci_domains_supported = 0 };
  1430. static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
  1431. static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
  1432. #endif /* CONFIG_PCI_DOMAINS */
  1433. /*
  1434. * Generic implementation for PCI domain support. If your
  1435. * architecture does not need custom management of PCI
  1436. * domains then this implementation will be used
  1437. */
  1438. #ifdef CONFIG_PCI_DOMAINS_GENERIC
  1439. static inline int pci_domain_nr(struct pci_bus *bus)
  1440. {
  1441. return bus->domain_nr;
  1442. }
  1443. #ifdef CONFIG_ACPI
  1444. int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
  1445. #else
  1446. static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
  1447. { return 0; }
  1448. #endif
  1449. int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
  1450. #endif
  1451. /* Some architectures require additional setup to direct VGA traffic */
  1452. typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
  1453. unsigned int command_bits, u32 flags);
  1454. void pci_register_set_vga_state(arch_set_vga_state_t func);
  1455. static inline int
  1456. pci_request_io_regions(struct pci_dev *pdev, const char *name)
  1457. {
  1458. return pci_request_selected_regions(pdev,
  1459. pci_select_bars(pdev, IORESOURCE_IO), name);
  1460. }
  1461. static inline void
  1462. pci_release_io_regions(struct pci_dev *pdev)
  1463. {
  1464. return pci_release_selected_regions(pdev,
  1465. pci_select_bars(pdev, IORESOURCE_IO));
  1466. }
  1467. static inline int
  1468. pci_request_mem_regions(struct pci_dev *pdev, const char *name)
  1469. {
  1470. return pci_request_selected_regions(pdev,
  1471. pci_select_bars(pdev, IORESOURCE_MEM), name);
  1472. }
  1473. static inline void
  1474. pci_release_mem_regions(struct pci_dev *pdev)
  1475. {
  1476. return pci_release_selected_regions(pdev,
  1477. pci_select_bars(pdev, IORESOURCE_MEM));
  1478. }
  1479. #else /* CONFIG_PCI is not enabled */
  1480. static inline void pci_set_flags(int flags) { }
  1481. static inline void pci_add_flags(int flags) { }
  1482. static inline void pci_clear_flags(int flags) { }
  1483. static inline int pci_has_flag(int flag) { return 0; }
  1484. /*
  1485. * If the system does not have PCI, clearly these return errors. Define
  1486. * these as simple inline functions to avoid hair in drivers.
  1487. */
  1488. #define _PCI_NOP(o, s, t) \
  1489. static inline int pci_##o##_config_##s(struct pci_dev *dev, \
  1490. int where, t val) \
  1491. { return PCIBIOS_FUNC_NOT_SUPPORTED; }
  1492. #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
  1493. _PCI_NOP(o, word, u16 x) \
  1494. _PCI_NOP(o, dword, u32 x)
  1495. _PCI_NOP_ALL(read, *)
  1496. _PCI_NOP_ALL(write,)
  1497. static inline struct pci_dev *pci_get_device(unsigned int vendor,
  1498. unsigned int device,
  1499. struct pci_dev *from)
  1500. { return NULL; }
  1501. static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
  1502. unsigned int device,
  1503. unsigned int ss_vendor,
  1504. unsigned int ss_device,
  1505. struct pci_dev *from)
  1506. { return NULL; }
  1507. static inline struct pci_dev *pci_get_class(unsigned int class,
  1508. struct pci_dev *from)
  1509. { return NULL; }
  1510. #define pci_dev_present(ids) (0)
  1511. #define no_pci_devices() (1)
  1512. #define pci_dev_put(dev) do { } while (0)
  1513. static inline void pci_set_master(struct pci_dev *dev) { }
  1514. static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
  1515. static inline void pci_disable_device(struct pci_dev *dev) { }
  1516. static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
  1517. static inline int pci_assign_resource(struct pci_dev *dev, int i)
  1518. { return -EBUSY; }
  1519. static inline int __must_check __pci_register_driver(struct pci_driver *drv,
  1520. struct module *owner,
  1521. const char *mod_name)
  1522. { return 0; }
  1523. static inline int pci_register_driver(struct pci_driver *drv)
  1524. { return 0; }
  1525. static inline void pci_unregister_driver(struct pci_driver *drv) { }
  1526. static inline int pci_find_capability(struct pci_dev *dev, int cap)
  1527. { return 0; }
  1528. static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
  1529. int cap)
  1530. { return 0; }
  1531. static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
  1532. { return 0; }
  1533. static inline u64 pci_get_dsn(struct pci_dev *dev)
  1534. { return 0; }
  1535. /* Power management related routines */
  1536. static inline int pci_save_state(struct pci_dev *dev) { return 0; }
  1537. static inline void pci_restore_state(struct pci_dev *dev) { }
  1538. static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
  1539. { return 0; }
  1540. static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
  1541. { return 0; }
  1542. static inline pci_power_t pci_choose_state(struct pci_dev *dev,
  1543. pm_message_t state)
  1544. { return PCI_D0; }
  1545. static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
  1546. int enable)
  1547. { return 0; }
  1548. static inline struct resource *pci_find_resource(struct pci_dev *dev,
  1549. struct resource *res)
  1550. { return NULL; }
  1551. static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
  1552. { return -EIO; }
  1553. static inline void pci_release_regions(struct pci_dev *dev) { }
  1554. static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
  1555. static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
  1556. { return NULL; }
  1557. static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
  1558. unsigned int devfn)
  1559. { return NULL; }
  1560. static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
  1561. unsigned int bus, unsigned int devfn)
  1562. { return NULL; }
  1563. static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
  1564. static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
  1565. #define dev_is_pci(d) (false)
  1566. #define dev_is_pf(d) (false)
  1567. static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
  1568. { return false; }
  1569. static inline int pci_irqd_intx_xlate(struct irq_domain *d,
  1570. struct device_node *node,
  1571. const u32 *intspec,
  1572. unsigned int intsize,
  1573. unsigned long *out_hwirq,
  1574. unsigned int *out_type)
  1575. { return -EINVAL; }
  1576. static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
  1577. struct pci_dev *dev)
  1578. { return NULL; }
  1579. static inline bool pci_ats_disabled(void) { return true; }
  1580. static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
  1581. {
  1582. return -EINVAL;
  1583. }
  1584. static inline int
  1585. pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
  1586. unsigned int max_vecs, unsigned int flags,
  1587. struct irq_affinity *aff_desc)
  1588. {
  1589. return -ENOSPC;
  1590. }
  1591. #endif /* CONFIG_PCI */
  1592. static inline int
  1593. pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
  1594. unsigned int max_vecs, unsigned int flags)
  1595. {
  1596. return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
  1597. NULL);
  1598. }
  1599. /* Include architecture-dependent settings and functions */
  1600. #include <asm/pci.h>
  1601. /* These two functions provide almost identical functionality. Depending
  1602. * on the architecture, one will be implemented as a wrapper around the
  1603. * other (in drivers/pci/mmap.c).
  1604. *
  1605. * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
  1606. * is expected to be an offset within that region.
  1607. *
  1608. * pci_mmap_page_range() is the legacy architecture-specific interface,
  1609. * which accepts a "user visible" resource address converted by
  1610. * pci_resource_to_user(), as used in the legacy mmap() interface in
  1611. * /proc/bus/pci/.
  1612. */
  1613. int pci_mmap_resource_range(struct pci_dev *dev, int bar,
  1614. struct vm_area_struct *vma,
  1615. enum pci_mmap_state mmap_state, int write_combine);
  1616. int pci_mmap_page_range(struct pci_dev *pdev, int bar,
  1617. struct vm_area_struct *vma,
  1618. enum pci_mmap_state mmap_state, int write_combine);
  1619. #ifndef arch_can_pci_mmap_wc
  1620. #define arch_can_pci_mmap_wc() 0
  1621. #endif
  1622. #ifndef arch_can_pci_mmap_io
  1623. #define arch_can_pci_mmap_io() 0
  1624. #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
  1625. #else
  1626. int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
  1627. #endif
  1628. #ifndef pci_root_bus_fwnode
  1629. #define pci_root_bus_fwnode(bus) NULL
  1630. #endif
  1631. /*
  1632. * These helpers provide future and backwards compatibility
  1633. * for accessing popular PCI BAR info
  1634. */
  1635. #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
  1636. #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
  1637. #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
  1638. #define pci_resource_len(dev,bar) \
  1639. ((pci_resource_start((dev), (bar)) == 0 && \
  1640. pci_resource_end((dev), (bar)) == \
  1641. pci_resource_start((dev), (bar))) ? 0 : \
  1642. \
  1643. (pci_resource_end((dev), (bar)) - \
  1644. pci_resource_start((dev), (bar)) + 1))
  1645. /*
  1646. * Similar to the helpers above, these manipulate per-pci_dev
  1647. * driver-specific data. They are really just a wrapper around
  1648. * the generic device structure functions of these calls.
  1649. */
  1650. static inline void *pci_get_drvdata(struct pci_dev *pdev)
  1651. {
  1652. return dev_get_drvdata(&pdev->dev);
  1653. }
  1654. static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
  1655. {
  1656. dev_set_drvdata(&pdev->dev, data);
  1657. }
  1658. static inline const char *pci_name(const struct pci_dev *pdev)
  1659. {
  1660. return dev_name(&pdev->dev);
  1661. }
  1662. void pci_resource_to_user(const struct pci_dev *dev, int bar,
  1663. const struct resource *rsrc,
  1664. resource_size_t *start, resource_size_t *end);
  1665. /*
  1666. * The world is not perfect and supplies us with broken PCI devices.
  1667. * For at least a part of these bugs we need a work-around, so both
  1668. * generic (drivers/pci/quirks.c) and per-architecture code can define
  1669. * fixup hooks to be called for particular buggy devices.
  1670. */
  1671. struct pci_fixup {
  1672. u16 vendor; /* Or PCI_ANY_ID */
  1673. u16 device; /* Or PCI_ANY_ID */
  1674. u32 class; /* Or PCI_ANY_ID */
  1675. unsigned int class_shift; /* should be 0, 8, 16 */
  1676. #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
  1677. int hook_offset;
  1678. #else
  1679. void (*hook)(struct pci_dev *dev);
  1680. #endif
  1681. };
  1682. enum pci_fixup_pass {
  1683. pci_fixup_early, /* Before probing BARs */
  1684. pci_fixup_header, /* After reading configuration header */
  1685. pci_fixup_final, /* Final phase of device fixups */
  1686. pci_fixup_enable, /* pci_enable_device() time */
  1687. pci_fixup_resume, /* pci_device_resume() */
  1688. pci_fixup_suspend, /* pci_device_suspend() */
  1689. pci_fixup_resume_early, /* pci_device_resume_early() */
  1690. pci_fixup_suspend_late, /* pci_device_suspend_late() */
  1691. };
  1692. #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
  1693. #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
  1694. class_shift, hook, stub) \
  1695. void __cficanonical stub(struct pci_dev *dev); \
  1696. void __cficanonical stub(struct pci_dev *dev) \
  1697. { \
  1698. hook(dev); \
  1699. } \
  1700. asm(".section " #sec ", \"a\" \n" \
  1701. ".balign 16 \n" \
  1702. ".short " #vendor ", " #device " \n" \
  1703. ".long " #class ", " #class_shift " \n" \
  1704. ".long " #stub " - . \n" \
  1705. ".previous \n");
  1706. #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
  1707. class_shift, hook, stub) \
  1708. ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
  1709. class_shift, hook, stub)
  1710. #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
  1711. class_shift, hook) \
  1712. __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
  1713. class_shift, hook, __UNIQUE_ID(hook))
  1714. #else
  1715. /* Anonymous variables would be nice... */
  1716. #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
  1717. class_shift, hook) \
  1718. static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
  1719. __attribute__((__section__(#section), aligned((sizeof(void *))))) \
  1720. = { vendor, device, class, class_shift, hook };
  1721. #endif
  1722. #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
  1723. class_shift, hook) \
  1724. DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
  1725. hook, vendor, device, class, class_shift, hook)
  1726. #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
  1727. class_shift, hook) \
  1728. DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
  1729. hook, vendor, device, class, class_shift, hook)
  1730. #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
  1731. class_shift, hook) \
  1732. DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
  1733. hook, vendor, device, class, class_shift, hook)
  1734. #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
  1735. class_shift, hook) \
  1736. DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
  1737. hook, vendor, device, class, class_shift, hook)
  1738. #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
  1739. class_shift, hook) \
  1740. DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
  1741. resume##hook, vendor, device, class, class_shift, hook)
  1742. #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
  1743. class_shift, hook) \
  1744. DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
  1745. resume_early##hook, vendor, device, class, class_shift, hook)
  1746. #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
  1747. class_shift, hook) \
  1748. DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
  1749. suspend##hook, vendor, device, class, class_shift, hook)
  1750. #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
  1751. class_shift, hook) \
  1752. DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
  1753. suspend_late##hook, vendor, device, class, class_shift, hook)
  1754. #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
  1755. DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
  1756. hook, vendor, device, PCI_ANY_ID, 0, hook)
  1757. #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
  1758. DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
  1759. hook, vendor, device, PCI_ANY_ID, 0, hook)
  1760. #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
  1761. DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
  1762. hook, vendor, device, PCI_ANY_ID, 0, hook)
  1763. #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
  1764. DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
  1765. hook, vendor, device, PCI_ANY_ID, 0, hook)
  1766. #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
  1767. DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
  1768. resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
  1769. #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
  1770. DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
  1771. resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
  1772. #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
  1773. DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
  1774. suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
  1775. #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
  1776. DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
  1777. suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
  1778. #ifdef CONFIG_PCI_QUIRKS
  1779. void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
  1780. #else
  1781. static inline void pci_fixup_device(enum pci_fixup_pass pass,
  1782. struct pci_dev *dev) { }
  1783. #endif
  1784. void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
  1785. void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
  1786. void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
  1787. int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
  1788. int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
  1789. const char *name);
  1790. void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
  1791. extern int pci_pci_problems;
  1792. #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
  1793. #define PCIPCI_TRITON 2
  1794. #define PCIPCI_NATOMA 4
  1795. #define PCIPCI_VIAETBF 8
  1796. #define PCIPCI_VSFX 16
  1797. #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
  1798. #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
  1799. extern unsigned long pci_cardbus_io_size;
  1800. extern unsigned long pci_cardbus_mem_size;
  1801. extern u8 pci_dfl_cache_line_size;
  1802. extern u8 pci_cache_line_size;
  1803. /* Architecture-specific versions may override these (weak) */
  1804. void pcibios_disable_device(struct pci_dev *dev);
  1805. void pcibios_set_master(struct pci_dev *dev);
  1806. int pcibios_set_pcie_reset_state(struct pci_dev *dev,
  1807. enum pcie_reset_state state);
  1808. int pcibios_add_device(struct pci_dev *dev);
  1809. void pcibios_release_device(struct pci_dev *dev);
  1810. #ifdef CONFIG_PCI
  1811. void pcibios_penalize_isa_irq(int irq, int active);
  1812. #else
  1813. static inline void pcibios_penalize_isa_irq(int irq, int active) {}
  1814. #endif
  1815. int pcibios_alloc_irq(struct pci_dev *dev);
  1816. void pcibios_free_irq(struct pci_dev *dev);
  1817. resource_size_t pcibios_default_alignment(void);
  1818. #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
  1819. void __init pci_mmcfg_early_init(void);
  1820. void __init pci_mmcfg_late_init(void);
  1821. #else
  1822. static inline void pci_mmcfg_early_init(void) { }
  1823. static inline void pci_mmcfg_late_init(void) { }
  1824. #endif
  1825. int pci_ext_cfg_avail(void);
  1826. void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
  1827. void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
  1828. #ifdef CONFIG_PCI_IOV
  1829. int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
  1830. int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
  1831. int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
  1832. void pci_disable_sriov(struct pci_dev *dev);
  1833. int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
  1834. int pci_iov_add_virtfn(struct pci_dev *dev, int id);
  1835. void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
  1836. int pci_num_vf(struct pci_dev *dev);
  1837. int pci_vfs_assigned(struct pci_dev *dev);
  1838. int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
  1839. int pci_sriov_get_totalvfs(struct pci_dev *dev);
  1840. int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
  1841. resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
  1842. void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
  1843. /* Arch may override these (weak) */
  1844. int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
  1845. int pcibios_sriov_disable(struct pci_dev *pdev);
  1846. resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
  1847. #else
  1848. static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
  1849. {
  1850. return -ENOSYS;
  1851. }
  1852. static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
  1853. {
  1854. return -ENOSYS;
  1855. }
  1856. static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
  1857. { return -ENODEV; }
  1858. static inline int pci_iov_sysfs_link(struct pci_dev *dev,
  1859. struct pci_dev *virtfn, int id)
  1860. {
  1861. return -ENODEV;
  1862. }
  1863. static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
  1864. {
  1865. return -ENOSYS;
  1866. }
  1867. static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
  1868. int id) { }
  1869. static inline void pci_disable_sriov(struct pci_dev *dev) { }
  1870. static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
  1871. static inline int pci_vfs_assigned(struct pci_dev *dev)
  1872. { return 0; }
  1873. static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
  1874. { return 0; }
  1875. static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
  1876. { return 0; }
  1877. #define pci_sriov_configure_simple NULL
  1878. static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
  1879. { return 0; }
  1880. static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
  1881. #endif
  1882. #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
  1883. void pci_hp_create_module_link(struct pci_slot *pci_slot);
  1884. void pci_hp_remove_module_link(struct pci_slot *pci_slot);
  1885. #endif
  1886. /**
  1887. * pci_pcie_cap - get the saved PCIe capability offset
  1888. * @dev: PCI device
  1889. *
  1890. * PCIe capability offset is calculated at PCI device initialization
  1891. * time and saved in the data structure. This function returns saved
  1892. * PCIe capability offset. Using this instead of pci_find_capability()
  1893. * reduces unnecessary search in the PCI configuration space. If you
  1894. * need to calculate PCIe capability offset from raw device for some
  1895. * reasons, please use pci_find_capability() instead.
  1896. */
  1897. static inline int pci_pcie_cap(struct pci_dev *dev)
  1898. {
  1899. return dev->pcie_cap;
  1900. }
  1901. /**
  1902. * pci_is_pcie - check if the PCI device is PCI Express capable
  1903. * @dev: PCI device
  1904. *
  1905. * Returns: true if the PCI device is PCI Express capable, false otherwise.
  1906. */
  1907. static inline bool pci_is_pcie(struct pci_dev *dev)
  1908. {
  1909. return pci_pcie_cap(dev);
  1910. }
  1911. /**
  1912. * pcie_caps_reg - get the PCIe Capabilities Register
  1913. * @dev: PCI device
  1914. */
  1915. static inline u16 pcie_caps_reg(const struct pci_dev *dev)
  1916. {
  1917. return dev->pcie_flags_reg;
  1918. }
  1919. /**
  1920. * pci_pcie_type - get the PCIe device/port type
  1921. * @dev: PCI device
  1922. */
  1923. static inline int pci_pcie_type(const struct pci_dev *dev)
  1924. {
  1925. return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
  1926. }
  1927. /**
  1928. * pcie_find_root_port - Get the PCIe root port device
  1929. * @dev: PCI device
  1930. *
  1931. * Traverse up the parent chain and return the PCIe Root Port PCI Device
  1932. * for a given PCI/PCIe Device.
  1933. */
  1934. static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
  1935. {
  1936. while (dev) {
  1937. if (pci_is_pcie(dev) &&
  1938. pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
  1939. return dev;
  1940. dev = pci_upstream_bridge(dev);
  1941. }
  1942. return NULL;
  1943. }
  1944. void pci_request_acs(void);
  1945. bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
  1946. bool pci_acs_path_enabled(struct pci_dev *start,
  1947. struct pci_dev *end, u16 acs_flags);
  1948. int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
  1949. #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
  1950. #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
  1951. /* Large Resource Data Type Tag Item Names */
  1952. #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
  1953. #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
  1954. #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
  1955. #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
  1956. #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
  1957. #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
  1958. /* Small Resource Data Type Tag Item Names */
  1959. #define PCI_VPD_STIN_END 0x0f /* End */
  1960. #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
  1961. #define PCI_VPD_SRDT_TIN_MASK 0x78
  1962. #define PCI_VPD_SRDT_LEN_MASK 0x07
  1963. #define PCI_VPD_LRDT_TIN_MASK 0x7f
  1964. #define PCI_VPD_LRDT_TAG_SIZE 3
  1965. #define PCI_VPD_SRDT_TAG_SIZE 1
  1966. #define PCI_VPD_INFO_FLD_HDR_SIZE 3
  1967. #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
  1968. #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
  1969. #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
  1970. #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
  1971. #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
  1972. /**
  1973. * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
  1974. * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
  1975. *
  1976. * Returns the extracted Large Resource Data Type length.
  1977. */
  1978. static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
  1979. {
  1980. return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
  1981. }
  1982. /**
  1983. * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
  1984. * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
  1985. *
  1986. * Returns the extracted Large Resource Data Type Tag item.
  1987. */
  1988. static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
  1989. {
  1990. return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
  1991. }
  1992. /**
  1993. * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
  1994. * @srdt: Pointer to the beginning of the Small Resource Data Type tag
  1995. *
  1996. * Returns the extracted Small Resource Data Type length.
  1997. */
  1998. static inline u8 pci_vpd_srdt_size(const u8 *srdt)
  1999. {
  2000. return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
  2001. }
  2002. /**
  2003. * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
  2004. * @srdt: Pointer to the beginning of the Small Resource Data Type tag
  2005. *
  2006. * Returns the extracted Small Resource Data Type Tag Item.
  2007. */
  2008. static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
  2009. {
  2010. return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
  2011. }
  2012. /**
  2013. * pci_vpd_info_field_size - Extracts the information field length
  2014. * @info_field: Pointer to the beginning of an information field header
  2015. *
  2016. * Returns the extracted information field length.
  2017. */
  2018. static inline u8 pci_vpd_info_field_size(const u8 *info_field)
  2019. {
  2020. return info_field[2];
  2021. }
  2022. /**
  2023. * pci_vpd_find_tag - Locates the Resource Data Type tag provided
  2024. * @buf: Pointer to buffered vpd data
  2025. * @off: The offset into the buffer at which to begin the search
  2026. * @len: The length of the vpd buffer
  2027. * @rdt: The Resource Data Type to search for
  2028. *
  2029. * Returns the index where the Resource Data Type was found or
  2030. * -ENOENT otherwise.
  2031. */
  2032. int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
  2033. /**
  2034. * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
  2035. * @buf: Pointer to buffered vpd data
  2036. * @off: The offset into the buffer at which to begin the search
  2037. * @len: The length of the buffer area, relative to off, in which to search
  2038. * @kw: The keyword to search for
  2039. *
  2040. * Returns the index where the information field keyword was found or
  2041. * -ENOENT otherwise.
  2042. */
  2043. int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
  2044. unsigned int len, const char *kw);
  2045. /* PCI <-> OF binding helpers */
  2046. #ifdef CONFIG_OF
  2047. struct device_node;
  2048. struct irq_domain;
  2049. struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
  2050. /* Arch may override this (weak) */
  2051. struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
  2052. #else /* CONFIG_OF */
  2053. static inline struct irq_domain *
  2054. pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
  2055. #endif /* CONFIG_OF */
  2056. static inline struct device_node *
  2057. pci_device_to_OF_node(const struct pci_dev *pdev)
  2058. {
  2059. return pdev ? pdev->dev.of_node : NULL;
  2060. }
  2061. static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
  2062. {
  2063. return bus ? bus->dev.of_node : NULL;
  2064. }
  2065. #ifdef CONFIG_ACPI
  2066. struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
  2067. void
  2068. pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
  2069. bool pci_pr3_present(struct pci_dev *pdev);
  2070. #else
  2071. static inline struct irq_domain *
  2072. pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
  2073. static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
  2074. #endif
  2075. #ifdef CONFIG_EEH
  2076. static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
  2077. {
  2078. return pdev->dev.archdata.edev;
  2079. }
  2080. #endif
  2081. void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
  2082. bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
  2083. int pci_for_each_dma_alias(struct pci_dev *pdev,
  2084. int (*fn)(struct pci_dev *pdev,
  2085. u16 alias, void *data), void *data);
  2086. /* Helper functions for operation of device flag */
  2087. static inline void pci_set_dev_assigned(struct pci_dev *pdev)
  2088. {
  2089. pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
  2090. }
  2091. static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
  2092. {
  2093. pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
  2094. }
  2095. static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
  2096. {
  2097. return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
  2098. }
  2099. /**
  2100. * pci_ari_enabled - query ARI forwarding status
  2101. * @bus: the PCI bus
  2102. *
  2103. * Returns true if ARI forwarding is enabled.
  2104. */
  2105. static inline bool pci_ari_enabled(struct pci_bus *bus)
  2106. {
  2107. return bus->self && bus->self->ari_enabled;
  2108. }
  2109. /**
  2110. * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
  2111. * @pdev: PCI device to check
  2112. *
  2113. * Walk upwards from @pdev and check for each encountered bridge if it's part
  2114. * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
  2115. * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
  2116. */
  2117. static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
  2118. {
  2119. struct pci_dev *parent = pdev;
  2120. if (pdev->is_thunderbolt)
  2121. return true;
  2122. while ((parent = pci_upstream_bridge(parent)))
  2123. if (parent->is_thunderbolt)
  2124. return true;
  2125. return false;
  2126. }
  2127. #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
  2128. void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
  2129. #endif
  2130. /* Provide the legacy pci_dma_* API */
  2131. #include <linux/pci-dma-compat.h>
  2132. #define pci_printk(level, pdev, fmt, arg...) \
  2133. dev_printk(level, &(pdev)->dev, fmt, ##arg)
  2134. #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
  2135. #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
  2136. #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
  2137. #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
  2138. #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
  2139. #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
  2140. #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
  2141. #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
  2142. #define pci_notice_ratelimited(pdev, fmt, arg...) \
  2143. dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
  2144. #define pci_info_ratelimited(pdev, fmt, arg...) \
  2145. dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
  2146. #define pci_WARN(pdev, condition, fmt, arg...) \
  2147. WARN(condition, "%s %s: " fmt, \
  2148. dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
  2149. #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
  2150. WARN_ONCE(condition, "%s %s: " fmt, \
  2151. dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
  2152. #endif /* LINUX_PCI_H */