omap-dma.h 9.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef __LINUX_OMAP_DMA_H
  3. #define __LINUX_OMAP_DMA_H
  4. /*
  5. * Legacy OMAP DMA handling defines and functions
  6. *
  7. * NOTE: Do not use these any longer.
  8. *
  9. * Use the generic dmaengine functions as defined in
  10. * include/linux/dmaengine.h.
  11. *
  12. * Copyright (C) 2003 Nokia Corporation
  13. * Author: Juha Yrjölä <juha.yrjola@nokia.com>
  14. *
  15. */
  16. #include <linux/platform_device.h>
  17. #define INT_DMA_LCD (NR_IRQS_LEGACY + 25)
  18. #define OMAP1_DMA_TOUT_IRQ (1 << 0)
  19. #define OMAP_DMA_DROP_IRQ (1 << 1)
  20. #define OMAP_DMA_HALF_IRQ (1 << 2)
  21. #define OMAP_DMA_FRAME_IRQ (1 << 3)
  22. #define OMAP_DMA_LAST_IRQ (1 << 4)
  23. #define OMAP_DMA_BLOCK_IRQ (1 << 5)
  24. #define OMAP1_DMA_SYNC_IRQ (1 << 6)
  25. #define OMAP2_DMA_PKT_IRQ (1 << 7)
  26. #define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8)
  27. #define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9)
  28. #define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
  29. #define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
  30. #define OMAP_DMA_CCR_EN (1 << 7)
  31. #define OMAP_DMA_CCR_RD_ACTIVE (1 << 9)
  32. #define OMAP_DMA_CCR_WR_ACTIVE (1 << 10)
  33. #define OMAP_DMA_CCR_SEL_SRC_DST_SYNC (1 << 24)
  34. #define OMAP_DMA_CCR_BUFFERING_DISABLE (1 << 25)
  35. #define OMAP_DMA_DATA_TYPE_S8 0x00
  36. #define OMAP_DMA_DATA_TYPE_S16 0x01
  37. #define OMAP_DMA_DATA_TYPE_S32 0x02
  38. #define OMAP_DMA_SYNC_ELEMENT 0x00
  39. #define OMAP_DMA_SYNC_FRAME 0x01
  40. #define OMAP_DMA_SYNC_BLOCK 0x02
  41. #define OMAP_DMA_SYNC_PACKET 0x03
  42. #define OMAP_DMA_DST_SYNC_PREFETCH 0x02
  43. #define OMAP_DMA_SRC_SYNC 0x01
  44. #define OMAP_DMA_DST_SYNC 0x00
  45. #define OMAP_DMA_PORT_EMIFF 0x00
  46. #define OMAP_DMA_PORT_EMIFS 0x01
  47. #define OMAP_DMA_PORT_OCP_T1 0x02
  48. #define OMAP_DMA_PORT_TIPB 0x03
  49. #define OMAP_DMA_PORT_OCP_T2 0x04
  50. #define OMAP_DMA_PORT_MPUI 0x05
  51. #define OMAP_DMA_AMODE_CONSTANT 0x00
  52. #define OMAP_DMA_AMODE_POST_INC 0x01
  53. #define OMAP_DMA_AMODE_SINGLE_IDX 0x02
  54. #define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
  55. #define DMA_DEFAULT_FIFO_DEPTH 0x10
  56. #define DMA_DEFAULT_ARB_RATE 0x01
  57. /* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
  58. #define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */
  59. #define DMA_THREAD_RESERVE_ONET (0x01 << 12)
  60. #define DMA_THREAD_RESERVE_TWOT (0x02 << 12)
  61. #define DMA_THREAD_RESERVE_THREET (0x03 << 12)
  62. #define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */
  63. #define DMA_THREAD_FIFO_75 (0x01 << 14)
  64. #define DMA_THREAD_FIFO_25 (0x02 << 14)
  65. #define DMA_THREAD_FIFO_50 (0x03 << 14)
  66. /* DMA4_OCP_SYSCONFIG bits */
  67. #define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12)
  68. #define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8)
  69. #define DMA_SYSCONFIG_EMUFREE (1 << 5)
  70. #define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3)
  71. #define DMA_SYSCONFIG_SOFTRESET (1 << 2)
  72. #define DMA_SYSCONFIG_AUTOIDLE (1 << 0)
  73. #define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12)
  74. #define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3)
  75. #define DMA_IDLEMODE_SMARTIDLE 0x2
  76. #define DMA_IDLEMODE_NO_IDLE 0x1
  77. #define DMA_IDLEMODE_FORCE_IDLE 0x0
  78. /* Chaining modes*/
  79. #ifndef CONFIG_ARCH_OMAP1
  80. #define OMAP_DMA_STATIC_CHAIN 0x1
  81. #define OMAP_DMA_DYNAMIC_CHAIN 0x2
  82. #define OMAP_DMA_CHAIN_ACTIVE 0x1
  83. #define OMAP_DMA_CHAIN_INACTIVE 0x0
  84. #endif
  85. #define DMA_CH_PRIO_HIGH 0x1
  86. #define DMA_CH_PRIO_LOW 0x0 /* Def */
  87. /* Errata handling */
  88. #define IS_DMA_ERRATA(id) (errata & (id))
  89. #define SET_DMA_ERRATA(id) (errata |= (id))
  90. #define DMA_ERRATA_IFRAME_BUFFERING BIT(0x0)
  91. #define DMA_ERRATA_PARALLEL_CHANNELS BIT(0x1)
  92. #define DMA_ERRATA_i378 BIT(0x2)
  93. #define DMA_ERRATA_i541 BIT(0x3)
  94. #define DMA_ERRATA_i88 BIT(0x4)
  95. #define DMA_ERRATA_3_3 BIT(0x5)
  96. #define DMA_ROMCODE_BUG BIT(0x6)
  97. /* Attributes for OMAP DMA Contrller */
  98. #define DMA_LINKED_LCH BIT(0x0)
  99. #define GLOBAL_PRIORITY BIT(0x1)
  100. #define RESERVE_CHANNEL BIT(0x2)
  101. #define IS_CSSA_32 BIT(0x3)
  102. #define IS_CDSA_32 BIT(0x4)
  103. #define IS_RW_PRIORITY BIT(0x5)
  104. #define ENABLE_1510_MODE BIT(0x6)
  105. #define SRC_PORT BIT(0x7)
  106. #define DST_PORT BIT(0x8)
  107. #define SRC_INDEX BIT(0x9)
  108. #define DST_INDEX BIT(0xa)
  109. #define IS_BURST_ONLY4 BIT(0xb)
  110. #define CLEAR_CSR_ON_READ BIT(0xc)
  111. #define IS_WORD_16 BIT(0xd)
  112. #define ENABLE_16XX_MODE BIT(0xe)
  113. #define HS_CHANNELS_RESERVED BIT(0xf)
  114. /* Defines for DMA Capabilities */
  115. #define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18)
  116. #define DMA_HAS_CONSTANT_FILL_CAPS (0x1 << 19)
  117. #define DMA_HAS_DESCRIPTOR_CAPS (0x3 << 20)
  118. enum omap_reg_offsets {
  119. GCR, GSCR, GRST1, HW_ID,
  120. PCH2_ID, PCH0_ID, PCH1_ID, PCHG_ID,
  121. PCHD_ID, CAPS_0, CAPS_1, CAPS_2,
  122. CAPS_3, CAPS_4, PCH2_SR, PCH0_SR,
  123. PCH1_SR, PCHD_SR, REVISION, IRQSTATUS_L0,
  124. IRQSTATUS_L1, IRQSTATUS_L2, IRQSTATUS_L3, IRQENABLE_L0,
  125. IRQENABLE_L1, IRQENABLE_L2, IRQENABLE_L3, SYSSTATUS,
  126. OCP_SYSCONFIG,
  127. /* omap1+ specific */
  128. CPC, CCR2, LCH_CTRL,
  129. /* Common registers for all omap's */
  130. CSDP, CCR, CICR, CSR,
  131. CEN, CFN, CSFI, CSEI,
  132. CSAC, CDAC, CDEI,
  133. CDFI, CLNK_CTRL,
  134. /* Channel specific registers */
  135. CSSA, CDSA, COLOR,
  136. CCEN, CCFN,
  137. /* omap3630 and omap4 specific */
  138. CDP, CNDP, CCDN,
  139. };
  140. enum omap_dma_burst_mode {
  141. OMAP_DMA_DATA_BURST_DIS = 0,
  142. OMAP_DMA_DATA_BURST_4,
  143. OMAP_DMA_DATA_BURST_8,
  144. OMAP_DMA_DATA_BURST_16,
  145. };
  146. enum end_type {
  147. OMAP_DMA_LITTLE_ENDIAN = 0,
  148. OMAP_DMA_BIG_ENDIAN
  149. };
  150. enum omap_dma_color_mode {
  151. OMAP_DMA_COLOR_DIS = 0,
  152. OMAP_DMA_CONSTANT_FILL,
  153. OMAP_DMA_TRANSPARENT_COPY
  154. };
  155. enum omap_dma_write_mode {
  156. OMAP_DMA_WRITE_NON_POSTED = 0,
  157. OMAP_DMA_WRITE_POSTED,
  158. OMAP_DMA_WRITE_LAST_NON_POSTED
  159. };
  160. enum omap_dma_channel_mode {
  161. OMAP_DMA_LCH_2D = 0,
  162. OMAP_DMA_LCH_G,
  163. OMAP_DMA_LCH_P,
  164. OMAP_DMA_LCH_PD
  165. };
  166. struct omap_dma_channel_params {
  167. int data_type; /* data type 8,16,32 */
  168. int elem_count; /* number of elements in a frame */
  169. int frame_count; /* number of frames in a element */
  170. int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
  171. int src_amode; /* constant, post increment, indexed,
  172. double indexed */
  173. unsigned long src_start; /* source address : physical */
  174. int src_ei; /* source element index */
  175. int src_fi; /* source frame index */
  176. int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
  177. int dst_amode; /* constant, post increment, indexed,
  178. double indexed */
  179. unsigned long dst_start; /* source address : physical */
  180. int dst_ei; /* source element index */
  181. int dst_fi; /* source frame index */
  182. int trigger; /* trigger attached if the channel is
  183. synchronized */
  184. int sync_mode; /* sycn on element, frame , block or packet */
  185. int src_or_dst_synch; /* source synch(1) or destination synch(0) */
  186. int ie; /* interrupt enabled */
  187. unsigned char read_prio;/* read priority */
  188. unsigned char write_prio;/* write priority */
  189. #ifndef CONFIG_ARCH_OMAP1
  190. enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
  191. #endif
  192. };
  193. struct omap_dma_lch {
  194. int next_lch;
  195. int dev_id;
  196. u16 saved_csr;
  197. u16 enabled_irqs;
  198. const char *dev_name;
  199. void (*callback)(int lch, u16 ch_status, void *data);
  200. void *data;
  201. long flags;
  202. int state;
  203. int chain_id;
  204. int status;
  205. };
  206. struct omap_dma_dev_attr {
  207. u32 dev_caps;
  208. u16 lch_count;
  209. u16 chan_count;
  210. };
  211. enum {
  212. OMAP_DMA_REG_NONE,
  213. OMAP_DMA_REG_16BIT,
  214. OMAP_DMA_REG_2X16BIT,
  215. OMAP_DMA_REG_32BIT,
  216. };
  217. struct omap_dma_reg {
  218. u16 offset;
  219. u8 stride;
  220. u8 type;
  221. };
  222. #define SDMA_FILTER_PARAM(hw_req) ((int[]) { (hw_req) })
  223. struct dma_slave_map;
  224. /* System DMA platform data structure */
  225. struct omap_system_dma_plat_info {
  226. const struct omap_dma_reg *reg_map;
  227. unsigned channel_stride;
  228. struct omap_dma_dev_attr *dma_attr;
  229. u32 errata;
  230. void (*show_dma_caps)(void);
  231. void (*clear_lch_regs)(int lch);
  232. void (*clear_dma)(int lch);
  233. void (*dma_write)(u32 val, int reg, int lch);
  234. u32 (*dma_read)(int reg, int lch);
  235. const struct dma_slave_map *slave_map;
  236. int slavecnt;
  237. };
  238. #ifdef CONFIG_ARCH_OMAP2PLUS
  239. #define dma_omap2plus() 1
  240. #else
  241. #define dma_omap2plus() 0
  242. #endif
  243. #define dma_omap1() (!dma_omap2plus())
  244. #define __dma_omap15xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_1510_MODE)
  245. #define __dma_omap16xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_16XX_MODE)
  246. #define dma_omap15xx() __dma_omap15xx(d)
  247. #define dma_omap16xx() __dma_omap16xx(d)
  248. #if defined(CONFIG_ARCH_OMAP)
  249. extern struct omap_system_dma_plat_info *omap_get_plat_info(void);
  250. extern void omap_set_dma_priority(int lch, int dst_port, int priority);
  251. extern int omap_request_dma(int dev_id, const char *dev_name,
  252. void (*callback)(int lch, u16 ch_status, void *data),
  253. void *data, int *dma_ch);
  254. extern void omap_disable_dma_irq(int ch, u16 irq_bits);
  255. extern void omap_free_dma(int ch);
  256. extern void omap_start_dma(int lch);
  257. extern void omap_stop_dma(int lch);
  258. extern void omap_set_dma_transfer_params(int lch, int data_type,
  259. int elem_count, int frame_count,
  260. int sync_mode,
  261. int dma_trigger, int src_or_dst_synch);
  262. extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
  263. extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
  264. unsigned long src_start,
  265. int src_ei, int src_fi);
  266. extern void omap_set_dma_src_data_pack(int lch, int enable);
  267. extern void omap_set_dma_src_burst_mode(int lch,
  268. enum omap_dma_burst_mode burst_mode);
  269. extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
  270. unsigned long dest_start,
  271. int dst_ei, int dst_fi);
  272. extern void omap_set_dma_dest_data_pack(int lch, int enable);
  273. extern void omap_set_dma_dest_burst_mode(int lch,
  274. enum omap_dma_burst_mode burst_mode);
  275. extern dma_addr_t omap_get_dma_src_pos(int lch);
  276. extern dma_addr_t omap_get_dma_dst_pos(int lch);
  277. extern int omap_get_dma_active_status(int lch);
  278. extern int omap_dma_running(void);
  279. #if defined(CONFIG_ARCH_OMAP1) && IS_ENABLED(CONFIG_FB_OMAP)
  280. #include <mach/lcd_dma.h>
  281. #else
  282. static inline int omap_lcd_dma_running(void)
  283. {
  284. return 0;
  285. }
  286. #endif
  287. #else /* CONFIG_ARCH_OMAP */
  288. static inline struct omap_system_dma_plat_info *omap_get_plat_info(void)
  289. {
  290. return NULL;
  291. }
  292. static inline int omap_request_dma(int dev_id, const char *dev_name,
  293. void (*callback)(int lch, u16 ch_status, void *data),
  294. void *data, int *dma_ch)
  295. {
  296. return -ENODEV;
  297. }
  298. static inline void omap_free_dma(int ch) { }
  299. #endif /* CONFIG_ARCH_OMAP */
  300. #endif /* __LINUX_OMAP_DMA_H */