nvme.h 36 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Definitions for the NVM Express interface
  4. * Copyright (c) 2011-2014, Intel Corporation.
  5. */
  6. #ifndef _LINUX_NVME_H
  7. #define _LINUX_NVME_H
  8. #include <linux/types.h>
  9. #include <linux/uuid.h>
  10. /* NQN names in commands fields specified one size */
  11. #define NVMF_NQN_FIELD_LEN 256
  12. /* However the max length of a qualified name is another size */
  13. #define NVMF_NQN_SIZE 223
  14. #define NVMF_TRSVCID_SIZE 32
  15. #define NVMF_TRADDR_SIZE 256
  16. #define NVMF_TSAS_SIZE 256
  17. #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
  18. #define NVME_RDMA_IP_PORT 4420
  19. #define NVME_NSID_ALL 0xffffffff
  20. enum nvme_subsys_type {
  21. NVME_NQN_DISC = 1, /* Discovery type target subsystem */
  22. NVME_NQN_NVME = 2, /* NVME type target subsystem */
  23. };
  24. /* Address Family codes for Discovery Log Page entry ADRFAM field */
  25. enum {
  26. NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
  27. NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
  28. NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
  29. NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
  30. NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
  31. NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */
  32. NVMF_ADDR_FAMILY_MAX,
  33. };
  34. /* Transport Type codes for Discovery Log Page entry TRTYPE field */
  35. enum {
  36. NVMF_TRTYPE_RDMA = 1, /* RDMA */
  37. NVMF_TRTYPE_FC = 2, /* Fibre Channel */
  38. NVMF_TRTYPE_TCP = 3, /* TCP/IP */
  39. NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
  40. NVMF_TRTYPE_MAX,
  41. };
  42. /* Transport Requirements codes for Discovery Log Page entry TREQ field */
  43. enum {
  44. NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
  45. NVMF_TREQ_REQUIRED = 1, /* Required */
  46. NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
  47. #define NVME_TREQ_SECURE_CHANNEL_MASK \
  48. (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
  49. NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
  50. };
  51. /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  52. * RDMA_QPTYPE field
  53. */
  54. enum {
  55. NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
  56. NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
  57. };
  58. /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  59. * RDMA_QPTYPE field
  60. */
  61. enum {
  62. NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
  63. NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
  64. NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
  65. NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
  66. NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
  67. };
  68. /* RDMA Connection Management Service Type codes for Discovery Log Page
  69. * entry TSAS RDMA_CMS field
  70. */
  71. enum {
  72. NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
  73. };
  74. #define NVME_AQ_DEPTH 32
  75. #define NVME_NR_AEN_COMMANDS 1
  76. #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
  77. /*
  78. * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
  79. * NVM-Express 1.2 specification, section 4.1.2.
  80. */
  81. #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
  82. enum {
  83. NVME_REG_CAP = 0x0000, /* Controller Capabilities */
  84. NVME_REG_VS = 0x0008, /* Version */
  85. NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
  86. NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
  87. NVME_REG_CC = 0x0014, /* Controller Configuration */
  88. NVME_REG_CSTS = 0x001c, /* Controller Status */
  89. NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
  90. NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
  91. NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
  92. NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
  93. NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
  94. NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
  95. NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
  96. NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
  97. NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
  98. * Location
  99. */
  100. NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory
  101. * Space Control
  102. */
  103. NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
  104. NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
  105. NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
  106. NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
  107. * Buffer Size
  108. */
  109. NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
  110. * Write Throughput
  111. */
  112. NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
  113. };
  114. #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
  115. #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
  116. #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
  117. #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
  118. #define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff)
  119. #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
  120. #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
  121. #define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1)
  122. #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
  123. #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
  124. enum {
  125. NVME_CMBSZ_SQS = 1 << 0,
  126. NVME_CMBSZ_CQS = 1 << 1,
  127. NVME_CMBSZ_LISTS = 1 << 2,
  128. NVME_CMBSZ_RDS = 1 << 3,
  129. NVME_CMBSZ_WDS = 1 << 4,
  130. NVME_CMBSZ_SZ_SHIFT = 12,
  131. NVME_CMBSZ_SZ_MASK = 0xfffff,
  132. NVME_CMBSZ_SZU_SHIFT = 8,
  133. NVME_CMBSZ_SZU_MASK = 0xf,
  134. };
  135. /*
  136. * Submission and Completion Queue Entry Sizes for the NVM command set.
  137. * (In bytes and specified as a power of two (2^n)).
  138. */
  139. #define NVME_ADM_SQES 6
  140. #define NVME_NVM_IOSQES 6
  141. #define NVME_NVM_IOCQES 4
  142. enum {
  143. NVME_CC_ENABLE = 1 << 0,
  144. NVME_CC_EN_SHIFT = 0,
  145. NVME_CC_CSS_SHIFT = 4,
  146. NVME_CC_MPS_SHIFT = 7,
  147. NVME_CC_AMS_SHIFT = 11,
  148. NVME_CC_SHN_SHIFT = 14,
  149. NVME_CC_IOSQES_SHIFT = 16,
  150. NVME_CC_IOCQES_SHIFT = 20,
  151. NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT,
  152. NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT,
  153. NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT,
  154. NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
  155. NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
  156. NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
  157. NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
  158. NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
  159. NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
  160. NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
  161. NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
  162. NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
  163. NVME_CAP_CSS_NVM = 1 << 0,
  164. NVME_CAP_CSS_CSI = 1 << 6,
  165. NVME_CSTS_RDY = 1 << 0,
  166. NVME_CSTS_CFS = 1 << 1,
  167. NVME_CSTS_NSSRO = 1 << 4,
  168. NVME_CSTS_PP = 1 << 5,
  169. NVME_CSTS_SHST_NORMAL = 0 << 2,
  170. NVME_CSTS_SHST_OCCUR = 1 << 2,
  171. NVME_CSTS_SHST_CMPLT = 2 << 2,
  172. NVME_CSTS_SHST_MASK = 3 << 2,
  173. NVME_CMBMSC_CRE = 1 << 0,
  174. NVME_CMBMSC_CMSE = 1 << 1,
  175. };
  176. struct nvme_id_power_state {
  177. __le16 max_power; /* centiwatts */
  178. __u8 rsvd2;
  179. __u8 flags;
  180. __le32 entry_lat; /* microseconds */
  181. __le32 exit_lat; /* microseconds */
  182. __u8 read_tput;
  183. __u8 read_lat;
  184. __u8 write_tput;
  185. __u8 write_lat;
  186. __le16 idle_power;
  187. __u8 idle_scale;
  188. __u8 rsvd19;
  189. __le16 active_power;
  190. __u8 active_work_scale;
  191. __u8 rsvd23[9];
  192. };
  193. enum {
  194. NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
  195. NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
  196. };
  197. enum nvme_ctrl_attr {
  198. NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
  199. NVME_CTRL_ATTR_TBKAS = (1 << 6),
  200. };
  201. struct nvme_id_ctrl {
  202. __le16 vid;
  203. __le16 ssvid;
  204. char sn[20];
  205. char mn[40];
  206. char fr[8];
  207. __u8 rab;
  208. __u8 ieee[3];
  209. __u8 cmic;
  210. __u8 mdts;
  211. __le16 cntlid;
  212. __le32 ver;
  213. __le32 rtd3r;
  214. __le32 rtd3e;
  215. __le32 oaes;
  216. __le32 ctratt;
  217. __u8 rsvd100[28];
  218. __le16 crdt1;
  219. __le16 crdt2;
  220. __le16 crdt3;
  221. __u8 rsvd134[122];
  222. __le16 oacs;
  223. __u8 acl;
  224. __u8 aerl;
  225. __u8 frmw;
  226. __u8 lpa;
  227. __u8 elpe;
  228. __u8 npss;
  229. __u8 avscc;
  230. __u8 apsta;
  231. __le16 wctemp;
  232. __le16 cctemp;
  233. __le16 mtfa;
  234. __le32 hmpre;
  235. __le32 hmmin;
  236. __u8 tnvmcap[16];
  237. __u8 unvmcap[16];
  238. __le32 rpmbs;
  239. __le16 edstt;
  240. __u8 dsto;
  241. __u8 fwug;
  242. __le16 kas;
  243. __le16 hctma;
  244. __le16 mntmt;
  245. __le16 mxtmt;
  246. __le32 sanicap;
  247. __le32 hmminds;
  248. __le16 hmmaxd;
  249. __u8 rsvd338[4];
  250. __u8 anatt;
  251. __u8 anacap;
  252. __le32 anagrpmax;
  253. __le32 nanagrpid;
  254. __u8 rsvd352[160];
  255. __u8 sqes;
  256. __u8 cqes;
  257. __le16 maxcmd;
  258. __le32 nn;
  259. __le16 oncs;
  260. __le16 fuses;
  261. __u8 fna;
  262. __u8 vwc;
  263. __le16 awun;
  264. __le16 awupf;
  265. __u8 nvscc;
  266. __u8 nwpc;
  267. __le16 acwu;
  268. __u8 rsvd534[2];
  269. __le32 sgls;
  270. __le32 mnan;
  271. __u8 rsvd544[224];
  272. char subnqn[256];
  273. __u8 rsvd1024[768];
  274. __le32 ioccsz;
  275. __le32 iorcsz;
  276. __le16 icdoff;
  277. __u8 ctrattr;
  278. __u8 msdbd;
  279. __u8 rsvd1804[244];
  280. struct nvme_id_power_state psd[32];
  281. __u8 vs[1024];
  282. };
  283. enum {
  284. NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1,
  285. NVME_CTRL_CMIC_ANA = 1 << 3,
  286. NVME_CTRL_ONCS_COMPARE = 1 << 0,
  287. NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
  288. NVME_CTRL_ONCS_DSM = 1 << 2,
  289. NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
  290. NVME_CTRL_ONCS_RESERVATIONS = 1 << 5,
  291. NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
  292. NVME_CTRL_VWC_PRESENT = 1 << 0,
  293. NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
  294. NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
  295. NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
  296. NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
  297. NVME_CTRL_CTRATT_128_ID = 1 << 0,
  298. NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
  299. NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
  300. NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
  301. NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
  302. NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
  303. NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
  304. NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
  305. };
  306. struct nvme_lbaf {
  307. __le16 ms;
  308. __u8 ds;
  309. __u8 rp;
  310. };
  311. struct nvme_id_ns {
  312. __le64 nsze;
  313. __le64 ncap;
  314. __le64 nuse;
  315. __u8 nsfeat;
  316. __u8 nlbaf;
  317. __u8 flbas;
  318. __u8 mc;
  319. __u8 dpc;
  320. __u8 dps;
  321. __u8 nmic;
  322. __u8 rescap;
  323. __u8 fpi;
  324. __u8 dlfeat;
  325. __le16 nawun;
  326. __le16 nawupf;
  327. __le16 nacwu;
  328. __le16 nabsn;
  329. __le16 nabo;
  330. __le16 nabspf;
  331. __le16 noiob;
  332. __u8 nvmcap[16];
  333. __le16 npwg;
  334. __le16 npwa;
  335. __le16 npdg;
  336. __le16 npda;
  337. __le16 nows;
  338. __u8 rsvd74[18];
  339. __le32 anagrpid;
  340. __u8 rsvd96[3];
  341. __u8 nsattr;
  342. __le16 nvmsetid;
  343. __le16 endgid;
  344. __u8 nguid[16];
  345. __u8 eui64[8];
  346. struct nvme_lbaf lbaf[16];
  347. __u8 rsvd192[192];
  348. __u8 vs[3712];
  349. };
  350. struct nvme_zns_lbafe {
  351. __le64 zsze;
  352. __u8 zdes;
  353. __u8 rsvd9[7];
  354. };
  355. struct nvme_id_ns_zns {
  356. __le16 zoc;
  357. __le16 ozcs;
  358. __le32 mar;
  359. __le32 mor;
  360. __le32 rrl;
  361. __le32 frl;
  362. __u8 rsvd20[2796];
  363. struct nvme_zns_lbafe lbafe[16];
  364. __u8 rsvd3072[768];
  365. __u8 vs[256];
  366. };
  367. struct nvme_id_ctrl_zns {
  368. __u8 zasl;
  369. __u8 rsvd1[4095];
  370. };
  371. enum {
  372. NVME_ID_CNS_NS = 0x00,
  373. NVME_ID_CNS_CTRL = 0x01,
  374. NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
  375. NVME_ID_CNS_NS_DESC_LIST = 0x03,
  376. NVME_ID_CNS_CS_NS = 0x05,
  377. NVME_ID_CNS_CS_CTRL = 0x06,
  378. NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
  379. NVME_ID_CNS_NS_PRESENT = 0x11,
  380. NVME_ID_CNS_CTRL_NS_LIST = 0x12,
  381. NVME_ID_CNS_CTRL_LIST = 0x13,
  382. NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
  383. NVME_ID_CNS_NS_GRANULARITY = 0x16,
  384. NVME_ID_CNS_UUID_LIST = 0x17,
  385. };
  386. enum {
  387. NVME_CSI_NVM = 0,
  388. NVME_CSI_ZNS = 2,
  389. };
  390. enum {
  391. NVME_DIR_IDENTIFY = 0x00,
  392. NVME_DIR_STREAMS = 0x01,
  393. NVME_DIR_SND_ID_OP_ENABLE = 0x01,
  394. NVME_DIR_SND_ST_OP_REL_ID = 0x01,
  395. NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
  396. NVME_DIR_RCV_ID_OP_PARAM = 0x01,
  397. NVME_DIR_RCV_ST_OP_PARAM = 0x01,
  398. NVME_DIR_RCV_ST_OP_STATUS = 0x02,
  399. NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
  400. NVME_DIR_ENDIR = 0x01,
  401. };
  402. enum {
  403. NVME_NS_FEAT_THIN = 1 << 0,
  404. NVME_NS_FEAT_ATOMICS = 1 << 1,
  405. NVME_NS_FEAT_IO_OPT = 1 << 4,
  406. NVME_NS_ATTR_RO = 1 << 0,
  407. NVME_NS_FLBAS_LBA_MASK = 0xf,
  408. NVME_NS_FLBAS_META_EXT = 0x10,
  409. NVME_NS_NMIC_SHARED = 1 << 0,
  410. NVME_LBAF_RP_BEST = 0,
  411. NVME_LBAF_RP_BETTER = 1,
  412. NVME_LBAF_RP_GOOD = 2,
  413. NVME_LBAF_RP_DEGRADED = 3,
  414. NVME_NS_DPC_PI_LAST = 1 << 4,
  415. NVME_NS_DPC_PI_FIRST = 1 << 3,
  416. NVME_NS_DPC_PI_TYPE3 = 1 << 2,
  417. NVME_NS_DPC_PI_TYPE2 = 1 << 1,
  418. NVME_NS_DPC_PI_TYPE1 = 1 << 0,
  419. NVME_NS_DPS_PI_FIRST = 1 << 3,
  420. NVME_NS_DPS_PI_MASK = 0x7,
  421. NVME_NS_DPS_PI_TYPE1 = 1,
  422. NVME_NS_DPS_PI_TYPE2 = 2,
  423. NVME_NS_DPS_PI_TYPE3 = 3,
  424. };
  425. /* Identify Namespace Metadata Capabilities (MC): */
  426. enum {
  427. NVME_MC_EXTENDED_LBA = (1 << 0),
  428. NVME_MC_METADATA_PTR = (1 << 1),
  429. };
  430. struct nvme_ns_id_desc {
  431. __u8 nidt;
  432. __u8 nidl;
  433. __le16 reserved;
  434. };
  435. #define NVME_NIDT_EUI64_LEN 8
  436. #define NVME_NIDT_NGUID_LEN 16
  437. #define NVME_NIDT_UUID_LEN 16
  438. #define NVME_NIDT_CSI_LEN 1
  439. enum {
  440. NVME_NIDT_EUI64 = 0x01,
  441. NVME_NIDT_NGUID = 0x02,
  442. NVME_NIDT_UUID = 0x03,
  443. NVME_NIDT_CSI = 0x04,
  444. };
  445. struct nvme_smart_log {
  446. __u8 critical_warning;
  447. __u8 temperature[2];
  448. __u8 avail_spare;
  449. __u8 spare_thresh;
  450. __u8 percent_used;
  451. __u8 endu_grp_crit_warn_sumry;
  452. __u8 rsvd7[25];
  453. __u8 data_units_read[16];
  454. __u8 data_units_written[16];
  455. __u8 host_reads[16];
  456. __u8 host_writes[16];
  457. __u8 ctrl_busy_time[16];
  458. __u8 power_cycles[16];
  459. __u8 power_on_hours[16];
  460. __u8 unsafe_shutdowns[16];
  461. __u8 media_errors[16];
  462. __u8 num_err_log_entries[16];
  463. __le32 warning_temp_time;
  464. __le32 critical_comp_time;
  465. __le16 temp_sensor[8];
  466. __le32 thm_temp1_trans_count;
  467. __le32 thm_temp2_trans_count;
  468. __le32 thm_temp1_total_time;
  469. __le32 thm_temp2_total_time;
  470. __u8 rsvd232[280];
  471. };
  472. struct nvme_fw_slot_info_log {
  473. __u8 afi;
  474. __u8 rsvd1[7];
  475. __le64 frs[7];
  476. __u8 rsvd64[448];
  477. };
  478. enum {
  479. NVME_CMD_EFFECTS_CSUPP = 1 << 0,
  480. NVME_CMD_EFFECTS_LBCC = 1 << 1,
  481. NVME_CMD_EFFECTS_NCC = 1 << 2,
  482. NVME_CMD_EFFECTS_NIC = 1 << 3,
  483. NVME_CMD_EFFECTS_CCC = 1 << 4,
  484. NVME_CMD_EFFECTS_CSE_MASK = 3 << 16,
  485. NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
  486. };
  487. struct nvme_effects_log {
  488. __le32 acs[256];
  489. __le32 iocs[256];
  490. __u8 resv[2048];
  491. };
  492. enum nvme_ana_state {
  493. NVME_ANA_OPTIMIZED = 0x01,
  494. NVME_ANA_NONOPTIMIZED = 0x02,
  495. NVME_ANA_INACCESSIBLE = 0x03,
  496. NVME_ANA_PERSISTENT_LOSS = 0x04,
  497. NVME_ANA_CHANGE = 0x0f,
  498. };
  499. struct nvme_ana_group_desc {
  500. __le32 grpid;
  501. __le32 nnsids;
  502. __le64 chgcnt;
  503. __u8 state;
  504. __u8 rsvd17[15];
  505. __le32 nsids[];
  506. };
  507. /* flag for the log specific field of the ANA log */
  508. #define NVME_ANA_LOG_RGO (1 << 0)
  509. struct nvme_ana_rsp_hdr {
  510. __le64 chgcnt;
  511. __le16 ngrps;
  512. __le16 rsvd10[3];
  513. };
  514. struct nvme_zone_descriptor {
  515. __u8 zt;
  516. __u8 zs;
  517. __u8 za;
  518. __u8 rsvd3[5];
  519. __le64 zcap;
  520. __le64 zslba;
  521. __le64 wp;
  522. __u8 rsvd32[32];
  523. };
  524. enum {
  525. NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2,
  526. };
  527. struct nvme_zone_report {
  528. __le64 nr_zones;
  529. __u8 resv8[56];
  530. struct nvme_zone_descriptor entries[];
  531. };
  532. enum {
  533. NVME_SMART_CRIT_SPARE = 1 << 0,
  534. NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
  535. NVME_SMART_CRIT_RELIABILITY = 1 << 2,
  536. NVME_SMART_CRIT_MEDIA = 1 << 3,
  537. NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
  538. };
  539. enum {
  540. NVME_AER_ERROR = 0,
  541. NVME_AER_SMART = 1,
  542. NVME_AER_NOTICE = 2,
  543. NVME_AER_CSS = 6,
  544. NVME_AER_VS = 7,
  545. };
  546. enum {
  547. NVME_AER_NOTICE_NS_CHANGED = 0x00,
  548. NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
  549. NVME_AER_NOTICE_ANA = 0x03,
  550. NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
  551. };
  552. enum {
  553. NVME_AEN_BIT_NS_ATTR = 8,
  554. NVME_AEN_BIT_FW_ACT = 9,
  555. NVME_AEN_BIT_ANA_CHANGE = 11,
  556. NVME_AEN_BIT_DISC_CHANGE = 31,
  557. };
  558. enum {
  559. NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
  560. NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
  561. NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
  562. NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
  563. };
  564. struct nvme_lba_range_type {
  565. __u8 type;
  566. __u8 attributes;
  567. __u8 rsvd2[14];
  568. __u64 slba;
  569. __u64 nlb;
  570. __u8 guid[16];
  571. __u8 rsvd48[16];
  572. };
  573. enum {
  574. NVME_LBART_TYPE_FS = 0x01,
  575. NVME_LBART_TYPE_RAID = 0x02,
  576. NVME_LBART_TYPE_CACHE = 0x03,
  577. NVME_LBART_TYPE_SWAP = 0x04,
  578. NVME_LBART_ATTRIB_TEMP = 1 << 0,
  579. NVME_LBART_ATTRIB_HIDE = 1 << 1,
  580. };
  581. struct nvme_reservation_status {
  582. __le32 gen;
  583. __u8 rtype;
  584. __u8 regctl[2];
  585. __u8 resv5[2];
  586. __u8 ptpls;
  587. __u8 resv10[13];
  588. struct {
  589. __le16 cntlid;
  590. __u8 rcsts;
  591. __u8 resv3[5];
  592. __le64 hostid;
  593. __le64 rkey;
  594. } regctl_ds[];
  595. };
  596. enum nvme_async_event_type {
  597. NVME_AER_TYPE_ERROR = 0,
  598. NVME_AER_TYPE_SMART = 1,
  599. NVME_AER_TYPE_NOTICE = 2,
  600. };
  601. /* I/O commands */
  602. enum nvme_opcode {
  603. nvme_cmd_flush = 0x00,
  604. nvme_cmd_write = 0x01,
  605. nvme_cmd_read = 0x02,
  606. nvme_cmd_write_uncor = 0x04,
  607. nvme_cmd_compare = 0x05,
  608. nvme_cmd_write_zeroes = 0x08,
  609. nvme_cmd_dsm = 0x09,
  610. nvme_cmd_verify = 0x0c,
  611. nvme_cmd_resv_register = 0x0d,
  612. nvme_cmd_resv_report = 0x0e,
  613. nvme_cmd_resv_acquire = 0x11,
  614. nvme_cmd_resv_release = 0x15,
  615. nvme_cmd_zone_mgmt_send = 0x79,
  616. nvme_cmd_zone_mgmt_recv = 0x7a,
  617. nvme_cmd_zone_append = 0x7d,
  618. };
  619. #define nvme_opcode_name(opcode) { opcode, #opcode }
  620. #define show_nvm_opcode_name(val) \
  621. __print_symbolic(val, \
  622. nvme_opcode_name(nvme_cmd_flush), \
  623. nvme_opcode_name(nvme_cmd_write), \
  624. nvme_opcode_name(nvme_cmd_read), \
  625. nvme_opcode_name(nvme_cmd_write_uncor), \
  626. nvme_opcode_name(nvme_cmd_compare), \
  627. nvme_opcode_name(nvme_cmd_write_zeroes), \
  628. nvme_opcode_name(nvme_cmd_dsm), \
  629. nvme_opcode_name(nvme_cmd_resv_register), \
  630. nvme_opcode_name(nvme_cmd_resv_report), \
  631. nvme_opcode_name(nvme_cmd_resv_acquire), \
  632. nvme_opcode_name(nvme_cmd_resv_release))
  633. /*
  634. * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
  635. *
  636. * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
  637. * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
  638. * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
  639. * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
  640. * request subtype
  641. */
  642. enum {
  643. NVME_SGL_FMT_ADDRESS = 0x00,
  644. NVME_SGL_FMT_OFFSET = 0x01,
  645. NVME_SGL_FMT_TRANSPORT_A = 0x0A,
  646. NVME_SGL_FMT_INVALIDATE = 0x0f,
  647. };
  648. /*
  649. * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
  650. *
  651. * For struct nvme_sgl_desc:
  652. * @NVME_SGL_FMT_DATA_DESC: data block descriptor
  653. * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
  654. * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
  655. *
  656. * For struct nvme_keyed_sgl_desc:
  657. * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
  658. *
  659. * Transport-specific SGL types:
  660. * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
  661. */
  662. enum {
  663. NVME_SGL_FMT_DATA_DESC = 0x00,
  664. NVME_SGL_FMT_SEG_DESC = 0x02,
  665. NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
  666. NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
  667. NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
  668. };
  669. struct nvme_sgl_desc {
  670. __le64 addr;
  671. __le32 length;
  672. __u8 rsvd[3];
  673. __u8 type;
  674. };
  675. struct nvme_keyed_sgl_desc {
  676. __le64 addr;
  677. __u8 length[3];
  678. __u8 key[4];
  679. __u8 type;
  680. };
  681. union nvme_data_ptr {
  682. struct {
  683. __le64 prp1;
  684. __le64 prp2;
  685. };
  686. struct nvme_sgl_desc sgl;
  687. struct nvme_keyed_sgl_desc ksgl;
  688. };
  689. /*
  690. * Lowest two bits of our flags field (FUSE field in the spec):
  691. *
  692. * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
  693. * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
  694. *
  695. * Highest two bits in our flags field (PSDT field in the spec):
  696. *
  697. * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
  698. * If used, MPTR contains addr of single physical buffer (byte aligned).
  699. * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
  700. * If used, MPTR contains an address of an SGL segment containing
  701. * exactly 1 SGL descriptor (qword aligned).
  702. */
  703. enum {
  704. NVME_CMD_FUSE_FIRST = (1 << 0),
  705. NVME_CMD_FUSE_SECOND = (1 << 1),
  706. NVME_CMD_SGL_METABUF = (1 << 6),
  707. NVME_CMD_SGL_METASEG = (1 << 7),
  708. NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
  709. };
  710. struct nvme_common_command {
  711. __u8 opcode;
  712. __u8 flags;
  713. __u16 command_id;
  714. __le32 nsid;
  715. __le32 cdw2[2];
  716. __le64 metadata;
  717. union nvme_data_ptr dptr;
  718. __le32 cdw10;
  719. __le32 cdw11;
  720. __le32 cdw12;
  721. __le32 cdw13;
  722. __le32 cdw14;
  723. __le32 cdw15;
  724. };
  725. struct nvme_rw_command {
  726. __u8 opcode;
  727. __u8 flags;
  728. __u16 command_id;
  729. __le32 nsid;
  730. __u64 rsvd2;
  731. __le64 metadata;
  732. union nvme_data_ptr dptr;
  733. __le64 slba;
  734. __le16 length;
  735. __le16 control;
  736. __le32 dsmgmt;
  737. __le32 reftag;
  738. __le16 apptag;
  739. __le16 appmask;
  740. };
  741. enum {
  742. NVME_RW_LR = 1 << 15,
  743. NVME_RW_FUA = 1 << 14,
  744. NVME_RW_APPEND_PIREMAP = 1 << 9,
  745. NVME_RW_DSM_FREQ_UNSPEC = 0,
  746. NVME_RW_DSM_FREQ_TYPICAL = 1,
  747. NVME_RW_DSM_FREQ_RARE = 2,
  748. NVME_RW_DSM_FREQ_READS = 3,
  749. NVME_RW_DSM_FREQ_WRITES = 4,
  750. NVME_RW_DSM_FREQ_RW = 5,
  751. NVME_RW_DSM_FREQ_ONCE = 6,
  752. NVME_RW_DSM_FREQ_PREFETCH = 7,
  753. NVME_RW_DSM_FREQ_TEMP = 8,
  754. NVME_RW_DSM_LATENCY_NONE = 0 << 4,
  755. NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
  756. NVME_RW_DSM_LATENCY_NORM = 2 << 4,
  757. NVME_RW_DSM_LATENCY_LOW = 3 << 4,
  758. NVME_RW_DSM_SEQ_REQ = 1 << 6,
  759. NVME_RW_DSM_COMPRESSED = 1 << 7,
  760. NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
  761. NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
  762. NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
  763. NVME_RW_PRINFO_PRACT = 1 << 13,
  764. NVME_RW_DTYPE_STREAMS = 1 << 4,
  765. };
  766. struct nvme_dsm_cmd {
  767. __u8 opcode;
  768. __u8 flags;
  769. __u16 command_id;
  770. __le32 nsid;
  771. __u64 rsvd2[2];
  772. union nvme_data_ptr dptr;
  773. __le32 nr;
  774. __le32 attributes;
  775. __u32 rsvd12[4];
  776. };
  777. enum {
  778. NVME_DSMGMT_IDR = 1 << 0,
  779. NVME_DSMGMT_IDW = 1 << 1,
  780. NVME_DSMGMT_AD = 1 << 2,
  781. };
  782. #define NVME_DSM_MAX_RANGES 256
  783. struct nvme_dsm_range {
  784. __le32 cattr;
  785. __le32 nlb;
  786. __le64 slba;
  787. };
  788. struct nvme_write_zeroes_cmd {
  789. __u8 opcode;
  790. __u8 flags;
  791. __u16 command_id;
  792. __le32 nsid;
  793. __u64 rsvd2;
  794. __le64 metadata;
  795. union nvme_data_ptr dptr;
  796. __le64 slba;
  797. __le16 length;
  798. __le16 control;
  799. __le32 dsmgmt;
  800. __le32 reftag;
  801. __le16 apptag;
  802. __le16 appmask;
  803. };
  804. enum nvme_zone_mgmt_action {
  805. NVME_ZONE_CLOSE = 0x1,
  806. NVME_ZONE_FINISH = 0x2,
  807. NVME_ZONE_OPEN = 0x3,
  808. NVME_ZONE_RESET = 0x4,
  809. NVME_ZONE_OFFLINE = 0x5,
  810. NVME_ZONE_SET_DESC_EXT = 0x10,
  811. };
  812. struct nvme_zone_mgmt_send_cmd {
  813. __u8 opcode;
  814. __u8 flags;
  815. __u16 command_id;
  816. __le32 nsid;
  817. __le32 cdw2[2];
  818. __le64 metadata;
  819. union nvme_data_ptr dptr;
  820. __le64 slba;
  821. __le32 cdw12;
  822. __u8 zsa;
  823. __u8 select_all;
  824. __u8 rsvd13[2];
  825. __le32 cdw14[2];
  826. };
  827. struct nvme_zone_mgmt_recv_cmd {
  828. __u8 opcode;
  829. __u8 flags;
  830. __u16 command_id;
  831. __le32 nsid;
  832. __le64 rsvd2[2];
  833. union nvme_data_ptr dptr;
  834. __le64 slba;
  835. __le32 numd;
  836. __u8 zra;
  837. __u8 zrasf;
  838. __u8 pr;
  839. __u8 rsvd13;
  840. __le32 cdw14[2];
  841. };
  842. enum {
  843. NVME_ZRA_ZONE_REPORT = 0,
  844. NVME_ZRASF_ZONE_REPORT_ALL = 0,
  845. NVME_REPORT_ZONE_PARTIAL = 1,
  846. };
  847. /* Features */
  848. enum {
  849. NVME_TEMP_THRESH_MASK = 0xffff,
  850. NVME_TEMP_THRESH_SELECT_SHIFT = 16,
  851. NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
  852. };
  853. struct nvme_feat_auto_pst {
  854. __le64 entries[32];
  855. };
  856. enum {
  857. NVME_HOST_MEM_ENABLE = (1 << 0),
  858. NVME_HOST_MEM_RETURN = (1 << 1),
  859. };
  860. struct nvme_feat_host_behavior {
  861. __u8 acre;
  862. __u8 resv1[511];
  863. };
  864. enum {
  865. NVME_ENABLE_ACRE = 1,
  866. };
  867. /* Admin commands */
  868. enum nvme_admin_opcode {
  869. nvme_admin_delete_sq = 0x00,
  870. nvme_admin_create_sq = 0x01,
  871. nvme_admin_get_log_page = 0x02,
  872. nvme_admin_delete_cq = 0x04,
  873. nvme_admin_create_cq = 0x05,
  874. nvme_admin_identify = 0x06,
  875. nvme_admin_abort_cmd = 0x08,
  876. nvme_admin_set_features = 0x09,
  877. nvme_admin_get_features = 0x0a,
  878. nvme_admin_async_event = 0x0c,
  879. nvme_admin_ns_mgmt = 0x0d,
  880. nvme_admin_activate_fw = 0x10,
  881. nvme_admin_download_fw = 0x11,
  882. nvme_admin_dev_self_test = 0x14,
  883. nvme_admin_ns_attach = 0x15,
  884. nvme_admin_keep_alive = 0x18,
  885. nvme_admin_directive_send = 0x19,
  886. nvme_admin_directive_recv = 0x1a,
  887. nvme_admin_virtual_mgmt = 0x1c,
  888. nvme_admin_nvme_mi_send = 0x1d,
  889. nvme_admin_nvme_mi_recv = 0x1e,
  890. nvme_admin_dbbuf = 0x7C,
  891. nvme_admin_format_nvm = 0x80,
  892. nvme_admin_security_send = 0x81,
  893. nvme_admin_security_recv = 0x82,
  894. nvme_admin_sanitize_nvm = 0x84,
  895. nvme_admin_get_lba_status = 0x86,
  896. nvme_admin_vendor_start = 0xC0,
  897. };
  898. #define nvme_admin_opcode_name(opcode) { opcode, #opcode }
  899. #define show_admin_opcode_name(val) \
  900. __print_symbolic(val, \
  901. nvme_admin_opcode_name(nvme_admin_delete_sq), \
  902. nvme_admin_opcode_name(nvme_admin_create_sq), \
  903. nvme_admin_opcode_name(nvme_admin_get_log_page), \
  904. nvme_admin_opcode_name(nvme_admin_delete_cq), \
  905. nvme_admin_opcode_name(nvme_admin_create_cq), \
  906. nvme_admin_opcode_name(nvme_admin_identify), \
  907. nvme_admin_opcode_name(nvme_admin_abort_cmd), \
  908. nvme_admin_opcode_name(nvme_admin_set_features), \
  909. nvme_admin_opcode_name(nvme_admin_get_features), \
  910. nvme_admin_opcode_name(nvme_admin_async_event), \
  911. nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
  912. nvme_admin_opcode_name(nvme_admin_activate_fw), \
  913. nvme_admin_opcode_name(nvme_admin_download_fw), \
  914. nvme_admin_opcode_name(nvme_admin_ns_attach), \
  915. nvme_admin_opcode_name(nvme_admin_keep_alive), \
  916. nvme_admin_opcode_name(nvme_admin_directive_send), \
  917. nvme_admin_opcode_name(nvme_admin_directive_recv), \
  918. nvme_admin_opcode_name(nvme_admin_dbbuf), \
  919. nvme_admin_opcode_name(nvme_admin_format_nvm), \
  920. nvme_admin_opcode_name(nvme_admin_security_send), \
  921. nvme_admin_opcode_name(nvme_admin_security_recv), \
  922. nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
  923. nvme_admin_opcode_name(nvme_admin_get_lba_status))
  924. enum {
  925. NVME_QUEUE_PHYS_CONTIG = (1 << 0),
  926. NVME_CQ_IRQ_ENABLED = (1 << 1),
  927. NVME_SQ_PRIO_URGENT = (0 << 1),
  928. NVME_SQ_PRIO_HIGH = (1 << 1),
  929. NVME_SQ_PRIO_MEDIUM = (2 << 1),
  930. NVME_SQ_PRIO_LOW = (3 << 1),
  931. NVME_FEAT_ARBITRATION = 0x01,
  932. NVME_FEAT_POWER_MGMT = 0x02,
  933. NVME_FEAT_LBA_RANGE = 0x03,
  934. NVME_FEAT_TEMP_THRESH = 0x04,
  935. NVME_FEAT_ERR_RECOVERY = 0x05,
  936. NVME_FEAT_VOLATILE_WC = 0x06,
  937. NVME_FEAT_NUM_QUEUES = 0x07,
  938. NVME_FEAT_IRQ_COALESCE = 0x08,
  939. NVME_FEAT_IRQ_CONFIG = 0x09,
  940. NVME_FEAT_WRITE_ATOMIC = 0x0a,
  941. NVME_FEAT_ASYNC_EVENT = 0x0b,
  942. NVME_FEAT_AUTO_PST = 0x0c,
  943. NVME_FEAT_HOST_MEM_BUF = 0x0d,
  944. NVME_FEAT_TIMESTAMP = 0x0e,
  945. NVME_FEAT_KATO = 0x0f,
  946. NVME_FEAT_HCTM = 0x10,
  947. NVME_FEAT_NOPSC = 0x11,
  948. NVME_FEAT_RRL = 0x12,
  949. NVME_FEAT_PLM_CONFIG = 0x13,
  950. NVME_FEAT_PLM_WINDOW = 0x14,
  951. NVME_FEAT_HOST_BEHAVIOR = 0x16,
  952. NVME_FEAT_SANITIZE = 0x17,
  953. NVME_FEAT_SW_PROGRESS = 0x80,
  954. NVME_FEAT_HOST_ID = 0x81,
  955. NVME_FEAT_RESV_MASK = 0x82,
  956. NVME_FEAT_RESV_PERSIST = 0x83,
  957. NVME_FEAT_WRITE_PROTECT = 0x84,
  958. NVME_FEAT_VENDOR_START = 0xC0,
  959. NVME_FEAT_VENDOR_END = 0xFF,
  960. NVME_LOG_ERROR = 0x01,
  961. NVME_LOG_SMART = 0x02,
  962. NVME_LOG_FW_SLOT = 0x03,
  963. NVME_LOG_CHANGED_NS = 0x04,
  964. NVME_LOG_CMD_EFFECTS = 0x05,
  965. NVME_LOG_DEVICE_SELF_TEST = 0x06,
  966. NVME_LOG_TELEMETRY_HOST = 0x07,
  967. NVME_LOG_TELEMETRY_CTRL = 0x08,
  968. NVME_LOG_ENDURANCE_GROUP = 0x09,
  969. NVME_LOG_ANA = 0x0c,
  970. NVME_LOG_DISC = 0x70,
  971. NVME_LOG_RESERVATION = 0x80,
  972. NVME_FWACT_REPL = (0 << 3),
  973. NVME_FWACT_REPL_ACTV = (1 << 3),
  974. NVME_FWACT_ACTV = (2 << 3),
  975. };
  976. /* NVMe Namespace Write Protect State */
  977. enum {
  978. NVME_NS_NO_WRITE_PROTECT = 0,
  979. NVME_NS_WRITE_PROTECT,
  980. NVME_NS_WRITE_PROTECT_POWER_CYCLE,
  981. NVME_NS_WRITE_PROTECT_PERMANENT,
  982. };
  983. #define NVME_MAX_CHANGED_NAMESPACES 1024
  984. struct nvme_identify {
  985. __u8 opcode;
  986. __u8 flags;
  987. __u16 command_id;
  988. __le32 nsid;
  989. __u64 rsvd2[2];
  990. union nvme_data_ptr dptr;
  991. __u8 cns;
  992. __u8 rsvd3;
  993. __le16 ctrlid;
  994. __u8 rsvd11[3];
  995. __u8 csi;
  996. __u32 rsvd12[4];
  997. };
  998. #define NVME_IDENTIFY_DATA_SIZE 4096
  999. struct nvme_features {
  1000. __u8 opcode;
  1001. __u8 flags;
  1002. __u16 command_id;
  1003. __le32 nsid;
  1004. __u64 rsvd2[2];
  1005. union nvme_data_ptr dptr;
  1006. __le32 fid;
  1007. __le32 dword11;
  1008. __le32 dword12;
  1009. __le32 dword13;
  1010. __le32 dword14;
  1011. __le32 dword15;
  1012. };
  1013. struct nvme_host_mem_buf_desc {
  1014. __le64 addr;
  1015. __le32 size;
  1016. __u32 rsvd;
  1017. };
  1018. struct nvme_create_cq {
  1019. __u8 opcode;
  1020. __u8 flags;
  1021. __u16 command_id;
  1022. __u32 rsvd1[5];
  1023. __le64 prp1;
  1024. __u64 rsvd8;
  1025. __le16 cqid;
  1026. __le16 qsize;
  1027. __le16 cq_flags;
  1028. __le16 irq_vector;
  1029. __u32 rsvd12[4];
  1030. };
  1031. struct nvme_create_sq {
  1032. __u8 opcode;
  1033. __u8 flags;
  1034. __u16 command_id;
  1035. __u32 rsvd1[5];
  1036. __le64 prp1;
  1037. __u64 rsvd8;
  1038. __le16 sqid;
  1039. __le16 qsize;
  1040. __le16 sq_flags;
  1041. __le16 cqid;
  1042. __u32 rsvd12[4];
  1043. };
  1044. struct nvme_delete_queue {
  1045. __u8 opcode;
  1046. __u8 flags;
  1047. __u16 command_id;
  1048. __u32 rsvd1[9];
  1049. __le16 qid;
  1050. __u16 rsvd10;
  1051. __u32 rsvd11[5];
  1052. };
  1053. struct nvme_abort_cmd {
  1054. __u8 opcode;
  1055. __u8 flags;
  1056. __u16 command_id;
  1057. __u32 rsvd1[9];
  1058. __le16 sqid;
  1059. __u16 cid;
  1060. __u32 rsvd11[5];
  1061. };
  1062. struct nvme_download_firmware {
  1063. __u8 opcode;
  1064. __u8 flags;
  1065. __u16 command_id;
  1066. __u32 rsvd1[5];
  1067. union nvme_data_ptr dptr;
  1068. __le32 numd;
  1069. __le32 offset;
  1070. __u32 rsvd12[4];
  1071. };
  1072. struct nvme_format_cmd {
  1073. __u8 opcode;
  1074. __u8 flags;
  1075. __u16 command_id;
  1076. __le32 nsid;
  1077. __u64 rsvd2[4];
  1078. __le32 cdw10;
  1079. __u32 rsvd11[5];
  1080. };
  1081. struct nvme_get_log_page_command {
  1082. __u8 opcode;
  1083. __u8 flags;
  1084. __u16 command_id;
  1085. __le32 nsid;
  1086. __u64 rsvd2[2];
  1087. union nvme_data_ptr dptr;
  1088. __u8 lid;
  1089. __u8 lsp; /* upper 4 bits reserved */
  1090. __le16 numdl;
  1091. __le16 numdu;
  1092. __u16 rsvd11;
  1093. union {
  1094. struct {
  1095. __le32 lpol;
  1096. __le32 lpou;
  1097. };
  1098. __le64 lpo;
  1099. };
  1100. __u8 rsvd14[3];
  1101. __u8 csi;
  1102. __u32 rsvd15;
  1103. };
  1104. struct nvme_directive_cmd {
  1105. __u8 opcode;
  1106. __u8 flags;
  1107. __u16 command_id;
  1108. __le32 nsid;
  1109. __u64 rsvd2[2];
  1110. union nvme_data_ptr dptr;
  1111. __le32 numd;
  1112. __u8 doper;
  1113. __u8 dtype;
  1114. __le16 dspec;
  1115. __u8 endir;
  1116. __u8 tdtype;
  1117. __u16 rsvd15;
  1118. __u32 rsvd16[3];
  1119. };
  1120. /*
  1121. * Fabrics subcommands.
  1122. */
  1123. enum nvmf_fabrics_opcode {
  1124. nvme_fabrics_command = 0x7f,
  1125. };
  1126. enum nvmf_capsule_command {
  1127. nvme_fabrics_type_property_set = 0x00,
  1128. nvme_fabrics_type_connect = 0x01,
  1129. nvme_fabrics_type_property_get = 0x04,
  1130. };
  1131. #define nvme_fabrics_type_name(type) { type, #type }
  1132. #define show_fabrics_type_name(type) \
  1133. __print_symbolic(type, \
  1134. nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
  1135. nvme_fabrics_type_name(nvme_fabrics_type_connect), \
  1136. nvme_fabrics_type_name(nvme_fabrics_type_property_get))
  1137. /*
  1138. * If not fabrics command, fctype will be ignored.
  1139. */
  1140. #define show_opcode_name(qid, opcode, fctype) \
  1141. ((opcode) == nvme_fabrics_command ? \
  1142. show_fabrics_type_name(fctype) : \
  1143. ((qid) ? \
  1144. show_nvm_opcode_name(opcode) : \
  1145. show_admin_opcode_name(opcode)))
  1146. struct nvmf_common_command {
  1147. __u8 opcode;
  1148. __u8 resv1;
  1149. __u16 command_id;
  1150. __u8 fctype;
  1151. __u8 resv2[35];
  1152. __u8 ts[24];
  1153. };
  1154. /*
  1155. * The legal cntlid range a NVMe Target will provide.
  1156. * Note that cntlid of value 0 is considered illegal in the fabrics world.
  1157. * Devices based on earlier specs did not have the subsystem concept;
  1158. * therefore, those devices had their cntlid value set to 0 as a result.
  1159. */
  1160. #define NVME_CNTLID_MIN 1
  1161. #define NVME_CNTLID_MAX 0xffef
  1162. #define NVME_CNTLID_DYNAMIC 0xffff
  1163. #define MAX_DISC_LOGS 255
  1164. /* Discovery log page entry */
  1165. struct nvmf_disc_rsp_page_entry {
  1166. __u8 trtype;
  1167. __u8 adrfam;
  1168. __u8 subtype;
  1169. __u8 treq;
  1170. __le16 portid;
  1171. __le16 cntlid;
  1172. __le16 asqsz;
  1173. __u8 resv8[22];
  1174. char trsvcid[NVMF_TRSVCID_SIZE];
  1175. __u8 resv64[192];
  1176. char subnqn[NVMF_NQN_FIELD_LEN];
  1177. char traddr[NVMF_TRADDR_SIZE];
  1178. union tsas {
  1179. char common[NVMF_TSAS_SIZE];
  1180. struct rdma {
  1181. __u8 qptype;
  1182. __u8 prtype;
  1183. __u8 cms;
  1184. __u8 resv3[5];
  1185. __u16 pkey;
  1186. __u8 resv10[246];
  1187. } rdma;
  1188. } tsas;
  1189. };
  1190. /* Discovery log page header */
  1191. struct nvmf_disc_rsp_page_hdr {
  1192. __le64 genctr;
  1193. __le64 numrec;
  1194. __le16 recfmt;
  1195. __u8 resv14[1006];
  1196. struct nvmf_disc_rsp_page_entry entries[];
  1197. };
  1198. enum {
  1199. NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
  1200. };
  1201. struct nvmf_connect_command {
  1202. __u8 opcode;
  1203. __u8 resv1;
  1204. __u16 command_id;
  1205. __u8 fctype;
  1206. __u8 resv2[19];
  1207. union nvme_data_ptr dptr;
  1208. __le16 recfmt;
  1209. __le16 qid;
  1210. __le16 sqsize;
  1211. __u8 cattr;
  1212. __u8 resv3;
  1213. __le32 kato;
  1214. __u8 resv4[12];
  1215. };
  1216. struct nvmf_connect_data {
  1217. uuid_t hostid;
  1218. __le16 cntlid;
  1219. char resv4[238];
  1220. char subsysnqn[NVMF_NQN_FIELD_LEN];
  1221. char hostnqn[NVMF_NQN_FIELD_LEN];
  1222. char resv5[256];
  1223. };
  1224. struct nvmf_property_set_command {
  1225. __u8 opcode;
  1226. __u8 resv1;
  1227. __u16 command_id;
  1228. __u8 fctype;
  1229. __u8 resv2[35];
  1230. __u8 attrib;
  1231. __u8 resv3[3];
  1232. __le32 offset;
  1233. __le64 value;
  1234. __u8 resv4[8];
  1235. };
  1236. struct nvmf_property_get_command {
  1237. __u8 opcode;
  1238. __u8 resv1;
  1239. __u16 command_id;
  1240. __u8 fctype;
  1241. __u8 resv2[35];
  1242. __u8 attrib;
  1243. __u8 resv3[3];
  1244. __le32 offset;
  1245. __u8 resv4[16];
  1246. };
  1247. struct nvme_dbbuf {
  1248. __u8 opcode;
  1249. __u8 flags;
  1250. __u16 command_id;
  1251. __u32 rsvd1[5];
  1252. __le64 prp1;
  1253. __le64 prp2;
  1254. __u32 rsvd12[6];
  1255. };
  1256. struct streams_directive_params {
  1257. __le16 msl;
  1258. __le16 nssa;
  1259. __le16 nsso;
  1260. __u8 rsvd[10];
  1261. __le32 sws;
  1262. __le16 sgs;
  1263. __le16 nsa;
  1264. __le16 nso;
  1265. __u8 rsvd2[6];
  1266. };
  1267. struct nvme_command {
  1268. union {
  1269. struct nvme_common_command common;
  1270. struct nvme_rw_command rw;
  1271. struct nvme_identify identify;
  1272. struct nvme_features features;
  1273. struct nvme_create_cq create_cq;
  1274. struct nvme_create_sq create_sq;
  1275. struct nvme_delete_queue delete_queue;
  1276. struct nvme_download_firmware dlfw;
  1277. struct nvme_format_cmd format;
  1278. struct nvme_dsm_cmd dsm;
  1279. struct nvme_write_zeroes_cmd write_zeroes;
  1280. struct nvme_zone_mgmt_send_cmd zms;
  1281. struct nvme_zone_mgmt_recv_cmd zmr;
  1282. struct nvme_abort_cmd abort;
  1283. struct nvme_get_log_page_command get_log_page;
  1284. struct nvmf_common_command fabrics;
  1285. struct nvmf_connect_command connect;
  1286. struct nvmf_property_set_command prop_set;
  1287. struct nvmf_property_get_command prop_get;
  1288. struct nvme_dbbuf dbbuf;
  1289. struct nvme_directive_cmd directive;
  1290. };
  1291. };
  1292. static inline bool nvme_is_fabrics(struct nvme_command *cmd)
  1293. {
  1294. return cmd->common.opcode == nvme_fabrics_command;
  1295. }
  1296. struct nvme_error_slot {
  1297. __le64 error_count;
  1298. __le16 sqid;
  1299. __le16 cmdid;
  1300. __le16 status_field;
  1301. __le16 param_error_location;
  1302. __le64 lba;
  1303. __le32 nsid;
  1304. __u8 vs;
  1305. __u8 resv[3];
  1306. __le64 cs;
  1307. __u8 resv2[24];
  1308. };
  1309. static inline bool nvme_is_write(struct nvme_command *cmd)
  1310. {
  1311. /*
  1312. * What a mess...
  1313. *
  1314. * Why can't we simply have a Fabrics In and Fabrics out command?
  1315. */
  1316. if (unlikely(nvme_is_fabrics(cmd)))
  1317. return cmd->fabrics.fctype & 1;
  1318. return cmd->common.opcode & 1;
  1319. }
  1320. enum {
  1321. /*
  1322. * Generic Command Status:
  1323. */
  1324. NVME_SC_SUCCESS = 0x0,
  1325. NVME_SC_INVALID_OPCODE = 0x1,
  1326. NVME_SC_INVALID_FIELD = 0x2,
  1327. NVME_SC_CMDID_CONFLICT = 0x3,
  1328. NVME_SC_DATA_XFER_ERROR = 0x4,
  1329. NVME_SC_POWER_LOSS = 0x5,
  1330. NVME_SC_INTERNAL = 0x6,
  1331. NVME_SC_ABORT_REQ = 0x7,
  1332. NVME_SC_ABORT_QUEUE = 0x8,
  1333. NVME_SC_FUSED_FAIL = 0x9,
  1334. NVME_SC_FUSED_MISSING = 0xa,
  1335. NVME_SC_INVALID_NS = 0xb,
  1336. NVME_SC_CMD_SEQ_ERROR = 0xc,
  1337. NVME_SC_SGL_INVALID_LAST = 0xd,
  1338. NVME_SC_SGL_INVALID_COUNT = 0xe,
  1339. NVME_SC_SGL_INVALID_DATA = 0xf,
  1340. NVME_SC_SGL_INVALID_METADATA = 0x10,
  1341. NVME_SC_SGL_INVALID_TYPE = 0x11,
  1342. NVME_SC_SGL_INVALID_OFFSET = 0x16,
  1343. NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
  1344. NVME_SC_SANITIZE_FAILED = 0x1C,
  1345. NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
  1346. NVME_SC_NS_WRITE_PROTECTED = 0x20,
  1347. NVME_SC_CMD_INTERRUPTED = 0x21,
  1348. NVME_SC_LBA_RANGE = 0x80,
  1349. NVME_SC_CAP_EXCEEDED = 0x81,
  1350. NVME_SC_NS_NOT_READY = 0x82,
  1351. NVME_SC_RESERVATION_CONFLICT = 0x83,
  1352. /*
  1353. * Command Specific Status:
  1354. */
  1355. NVME_SC_CQ_INVALID = 0x100,
  1356. NVME_SC_QID_INVALID = 0x101,
  1357. NVME_SC_QUEUE_SIZE = 0x102,
  1358. NVME_SC_ABORT_LIMIT = 0x103,
  1359. NVME_SC_ABORT_MISSING = 0x104,
  1360. NVME_SC_ASYNC_LIMIT = 0x105,
  1361. NVME_SC_FIRMWARE_SLOT = 0x106,
  1362. NVME_SC_FIRMWARE_IMAGE = 0x107,
  1363. NVME_SC_INVALID_VECTOR = 0x108,
  1364. NVME_SC_INVALID_LOG_PAGE = 0x109,
  1365. NVME_SC_INVALID_FORMAT = 0x10a,
  1366. NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
  1367. NVME_SC_INVALID_QUEUE = 0x10c,
  1368. NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
  1369. NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
  1370. NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
  1371. NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
  1372. NVME_SC_FW_NEEDS_RESET = 0x111,
  1373. NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
  1374. NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
  1375. NVME_SC_OVERLAPPING_RANGE = 0x114,
  1376. NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
  1377. NVME_SC_NS_ID_UNAVAILABLE = 0x116,
  1378. NVME_SC_NS_ALREADY_ATTACHED = 0x118,
  1379. NVME_SC_NS_IS_PRIVATE = 0x119,
  1380. NVME_SC_NS_NOT_ATTACHED = 0x11a,
  1381. NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
  1382. NVME_SC_CTRL_LIST_INVALID = 0x11c,
  1383. NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
  1384. NVME_SC_PMR_SAN_PROHIBITED = 0x123,
  1385. /*
  1386. * I/O Command Set Specific - NVM commands:
  1387. */
  1388. NVME_SC_BAD_ATTRIBUTES = 0x180,
  1389. NVME_SC_INVALID_PI = 0x181,
  1390. NVME_SC_READ_ONLY = 0x182,
  1391. NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
  1392. /*
  1393. * I/O Command Set Specific - Fabrics commands:
  1394. */
  1395. NVME_SC_CONNECT_FORMAT = 0x180,
  1396. NVME_SC_CONNECT_CTRL_BUSY = 0x181,
  1397. NVME_SC_CONNECT_INVALID_PARAM = 0x182,
  1398. NVME_SC_CONNECT_RESTART_DISC = 0x183,
  1399. NVME_SC_CONNECT_INVALID_HOST = 0x184,
  1400. NVME_SC_DISCOVERY_RESTART = 0x190,
  1401. NVME_SC_AUTH_REQUIRED = 0x191,
  1402. /*
  1403. * I/O Command Set Specific - Zoned commands:
  1404. */
  1405. NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8,
  1406. NVME_SC_ZONE_FULL = 0x1b9,
  1407. NVME_SC_ZONE_READ_ONLY = 0x1ba,
  1408. NVME_SC_ZONE_OFFLINE = 0x1bb,
  1409. NVME_SC_ZONE_INVALID_WRITE = 0x1bc,
  1410. NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd,
  1411. NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be,
  1412. NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
  1413. /*
  1414. * Media and Data Integrity Errors:
  1415. */
  1416. NVME_SC_WRITE_FAULT = 0x280,
  1417. NVME_SC_READ_ERROR = 0x281,
  1418. NVME_SC_GUARD_CHECK = 0x282,
  1419. NVME_SC_APPTAG_CHECK = 0x283,
  1420. NVME_SC_REFTAG_CHECK = 0x284,
  1421. NVME_SC_COMPARE_FAILED = 0x285,
  1422. NVME_SC_ACCESS_DENIED = 0x286,
  1423. NVME_SC_UNWRITTEN_BLOCK = 0x287,
  1424. /*
  1425. * Path-related Errors:
  1426. */
  1427. NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
  1428. NVME_SC_ANA_INACCESSIBLE = 0x302,
  1429. NVME_SC_ANA_TRANSITION = 0x303,
  1430. NVME_SC_HOST_PATH_ERROR = 0x370,
  1431. NVME_SC_HOST_ABORTED_CMD = 0x371,
  1432. NVME_SC_CRD = 0x1800,
  1433. NVME_SC_DNR = 0x4000,
  1434. };
  1435. struct nvme_completion {
  1436. /*
  1437. * Used by Admin and Fabrics commands to return data:
  1438. */
  1439. union nvme_result {
  1440. __le16 u16;
  1441. __le32 u32;
  1442. __le64 u64;
  1443. } result;
  1444. __le16 sq_head; /* how much of this queue may be reclaimed */
  1445. __le16 sq_id; /* submission queue that generated this entry */
  1446. __u16 command_id; /* of the command which completed */
  1447. __le16 status; /* did the command fail, and if so, why? */
  1448. };
  1449. #define NVME_VS(major, minor, tertiary) \
  1450. (((major) << 16) | ((minor) << 8) | (tertiary))
  1451. #define NVME_MAJOR(ver) ((ver) >> 16)
  1452. #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
  1453. #define NVME_TERTIARY(ver) ((ver) & 0xff)
  1454. #endif /* _LINUX_NVME_H */