mv643xx.h 51 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * mv643xx.h - MV-643XX Internal registers definition file.
  4. *
  5. * Copyright 2002 Momentum Computer, Inc.
  6. * Author: Matthew Dharm <mdharm@momenco.com>
  7. * Copyright 2002 GALILEO TECHNOLOGY, LTD.
  8. */
  9. #ifndef __ASM_MV643XX_H
  10. #define __ASM_MV643XX_H
  11. #include <asm/types.h>
  12. #include <linux/mv643xx_eth.h>
  13. #include <linux/mv643xx_i2c.h>
  14. /****************************************/
  15. /* Processor Address Space */
  16. /****************************************/
  17. /* DDR SDRAM BAR and size registers */
  18. #define MV64340_CS_0_BASE_ADDR 0x008
  19. #define MV64340_CS_0_SIZE 0x010
  20. #define MV64340_CS_1_BASE_ADDR 0x208
  21. #define MV64340_CS_1_SIZE 0x210
  22. #define MV64340_CS_2_BASE_ADDR 0x018
  23. #define MV64340_CS_2_SIZE 0x020
  24. #define MV64340_CS_3_BASE_ADDR 0x218
  25. #define MV64340_CS_3_SIZE 0x220
  26. /* Devices BAR and size registers */
  27. #define MV64340_DEV_CS0_BASE_ADDR 0x028
  28. #define MV64340_DEV_CS0_SIZE 0x030
  29. #define MV64340_DEV_CS1_BASE_ADDR 0x228
  30. #define MV64340_DEV_CS1_SIZE 0x230
  31. #define MV64340_DEV_CS2_BASE_ADDR 0x248
  32. #define MV64340_DEV_CS2_SIZE 0x250
  33. #define MV64340_DEV_CS3_BASE_ADDR 0x038
  34. #define MV64340_DEV_CS3_SIZE 0x040
  35. #define MV64340_BOOTCS_BASE_ADDR 0x238
  36. #define MV64340_BOOTCS_SIZE 0x240
  37. /* PCI 0 BAR and size registers */
  38. #define MV64340_PCI_0_IO_BASE_ADDR 0x048
  39. #define MV64340_PCI_0_IO_SIZE 0x050
  40. #define MV64340_PCI_0_MEMORY0_BASE_ADDR 0x058
  41. #define MV64340_PCI_0_MEMORY0_SIZE 0x060
  42. #define MV64340_PCI_0_MEMORY1_BASE_ADDR 0x080
  43. #define MV64340_PCI_0_MEMORY1_SIZE 0x088
  44. #define MV64340_PCI_0_MEMORY2_BASE_ADDR 0x258
  45. #define MV64340_PCI_0_MEMORY2_SIZE 0x260
  46. #define MV64340_PCI_0_MEMORY3_BASE_ADDR 0x280
  47. #define MV64340_PCI_0_MEMORY3_SIZE 0x288
  48. /* PCI 1 BAR and size registers */
  49. #define MV64340_PCI_1_IO_BASE_ADDR 0x090
  50. #define MV64340_PCI_1_IO_SIZE 0x098
  51. #define MV64340_PCI_1_MEMORY0_BASE_ADDR 0x0a0
  52. #define MV64340_PCI_1_MEMORY0_SIZE 0x0a8
  53. #define MV64340_PCI_1_MEMORY1_BASE_ADDR 0x0b0
  54. #define MV64340_PCI_1_MEMORY1_SIZE 0x0b8
  55. #define MV64340_PCI_1_MEMORY2_BASE_ADDR 0x2a0
  56. #define MV64340_PCI_1_MEMORY2_SIZE 0x2a8
  57. #define MV64340_PCI_1_MEMORY3_BASE_ADDR 0x2b0
  58. #define MV64340_PCI_1_MEMORY3_SIZE 0x2b8
  59. /* SRAM base address */
  60. #define MV64340_INTEGRATED_SRAM_BASE_ADDR 0x268
  61. /* internal registers space base address */
  62. #define MV64340_INTERNAL_SPACE_BASE_ADDR 0x068
  63. /* Enables the CS , DEV_CS , PCI 0 and PCI 1
  64. windows above */
  65. #define MV64340_BASE_ADDR_ENABLE 0x278
  66. /****************************************/
  67. /* PCI remap registers */
  68. /****************************************/
  69. /* PCI 0 */
  70. #define MV64340_PCI_0_IO_ADDR_REMAP 0x0f0
  71. #define MV64340_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8
  72. #define MV64340_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320
  73. #define MV64340_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100
  74. #define MV64340_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328
  75. #define MV64340_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8
  76. #define MV64340_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330
  77. #define MV64340_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300
  78. #define MV64340_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338
  79. /* PCI 1 */
  80. #define MV64340_PCI_1_IO_ADDR_REMAP 0x108
  81. #define MV64340_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110
  82. #define MV64340_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340
  83. #define MV64340_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118
  84. #define MV64340_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348
  85. #define MV64340_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310
  86. #define MV64340_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350
  87. #define MV64340_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318
  88. #define MV64340_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358
  89. #define MV64340_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0
  90. #define MV64340_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8
  91. #define MV64340_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0
  92. #define MV64340_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8
  93. #define MV64340_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0
  94. #define MV64340_CPU_GE_HEADERS_RETARGET_BASE 0x3d8
  95. #define MV64340_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0
  96. #define MV64340_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8
  97. /****************************************/
  98. /* CPU Control Registers */
  99. /****************************************/
  100. #define MV64340_CPU_CONFIG 0x000
  101. #define MV64340_CPU_MODE 0x120
  102. #define MV64340_CPU_MASTER_CONTROL 0x160
  103. #define MV64340_CPU_CROSS_BAR_CONTROL_LOW 0x150
  104. #define MV64340_CPU_CROSS_BAR_CONTROL_HIGH 0x158
  105. #define MV64340_CPU_CROSS_BAR_TIMEOUT 0x168
  106. /****************************************/
  107. /* SMP RegisterS */
  108. /****************************************/
  109. #define MV64340_SMP_WHO_AM_I 0x200
  110. #define MV64340_SMP_CPU0_DOORBELL 0x214
  111. #define MV64340_SMP_CPU0_DOORBELL_CLEAR 0x21C
  112. #define MV64340_SMP_CPU1_DOORBELL 0x224
  113. #define MV64340_SMP_CPU1_DOORBELL_CLEAR 0x22C
  114. #define MV64340_SMP_CPU0_DOORBELL_MASK 0x234
  115. #define MV64340_SMP_CPU1_DOORBELL_MASK 0x23C
  116. #define MV64340_SMP_SEMAPHOR0 0x244
  117. #define MV64340_SMP_SEMAPHOR1 0x24c
  118. #define MV64340_SMP_SEMAPHOR2 0x254
  119. #define MV64340_SMP_SEMAPHOR3 0x25c
  120. #define MV64340_SMP_SEMAPHOR4 0x264
  121. #define MV64340_SMP_SEMAPHOR5 0x26c
  122. #define MV64340_SMP_SEMAPHOR6 0x274
  123. #define MV64340_SMP_SEMAPHOR7 0x27c
  124. /****************************************/
  125. /* CPU Sync Barrier Register */
  126. /****************************************/
  127. #define MV64340_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0
  128. #define MV64340_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8
  129. #define MV64340_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0
  130. #define MV64340_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8
  131. /****************************************/
  132. /* CPU Access Protect */
  133. /****************************************/
  134. #define MV64340_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180
  135. #define MV64340_CPU_PROTECT_WINDOW_0_SIZE 0x188
  136. #define MV64340_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190
  137. #define MV64340_CPU_PROTECT_WINDOW_1_SIZE 0x198
  138. #define MV64340_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0
  139. #define MV64340_CPU_PROTECT_WINDOW_2_SIZE 0x1a8
  140. #define MV64340_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0
  141. #define MV64340_CPU_PROTECT_WINDOW_3_SIZE 0x1b8
  142. /****************************************/
  143. /* CPU Error Report */
  144. /****************************************/
  145. #define MV64340_CPU_ERROR_ADDR_LOW 0x070
  146. #define MV64340_CPU_ERROR_ADDR_HIGH 0x078
  147. #define MV64340_CPU_ERROR_DATA_LOW 0x128
  148. #define MV64340_CPU_ERROR_DATA_HIGH 0x130
  149. #define MV64340_CPU_ERROR_PARITY 0x138
  150. #define MV64340_CPU_ERROR_CAUSE 0x140
  151. #define MV64340_CPU_ERROR_MASK 0x148
  152. /****************************************/
  153. /* CPU Interface Debug Registers */
  154. /****************************************/
  155. #define MV64340_PUNIT_SLAVE_DEBUG_LOW 0x360
  156. #define MV64340_PUNIT_SLAVE_DEBUG_HIGH 0x368
  157. #define MV64340_PUNIT_MASTER_DEBUG_LOW 0x370
  158. #define MV64340_PUNIT_MASTER_DEBUG_HIGH 0x378
  159. #define MV64340_PUNIT_MMASK 0x3e4
  160. /****************************************/
  161. /* Integrated SRAM Registers */
  162. /****************************************/
  163. #define MV64340_SRAM_CONFIG 0x380
  164. #define MV64340_SRAM_TEST_MODE 0X3F4
  165. #define MV64340_SRAM_ERROR_CAUSE 0x388
  166. #define MV64340_SRAM_ERROR_ADDR 0x390
  167. #define MV64340_SRAM_ERROR_ADDR_HIGH 0X3F8
  168. #define MV64340_SRAM_ERROR_DATA_LOW 0x398
  169. #define MV64340_SRAM_ERROR_DATA_HIGH 0x3a0
  170. #define MV64340_SRAM_ERROR_DATA_PARITY 0x3a8
  171. /****************************************/
  172. /* SDRAM Configuration */
  173. /****************************************/
  174. #define MV64340_SDRAM_CONFIG 0x1400
  175. #define MV64340_D_UNIT_CONTROL_LOW 0x1404
  176. #define MV64340_D_UNIT_CONTROL_HIGH 0x1424
  177. #define MV64340_SDRAM_TIMING_CONTROL_LOW 0x1408
  178. #define MV64340_SDRAM_TIMING_CONTROL_HIGH 0x140c
  179. #define MV64340_SDRAM_ADDR_CONTROL 0x1410
  180. #define MV64340_SDRAM_OPEN_PAGES_CONTROL 0x1414
  181. #define MV64340_SDRAM_OPERATION 0x1418
  182. #define MV64340_SDRAM_MODE 0x141c
  183. #define MV64340_EXTENDED_DRAM_MODE 0x1420
  184. #define MV64340_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430
  185. #define MV64340_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434
  186. #define MV64340_SDRAM_CROSS_BAR_TIMEOUT 0x1438
  187. #define MV64340_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0
  188. #define MV64340_SDRAM_DATA_PADS_CALIBRATION 0x14c4
  189. /****************************************/
  190. /* SDRAM Error Report */
  191. /****************************************/
  192. #define MV64340_SDRAM_ERROR_DATA_LOW 0x1444
  193. #define MV64340_SDRAM_ERROR_DATA_HIGH 0x1440
  194. #define MV64340_SDRAM_ERROR_ADDR 0x1450
  195. #define MV64340_SDRAM_RECEIVED_ECC 0x1448
  196. #define MV64340_SDRAM_CALCULATED_ECC 0x144c
  197. #define MV64340_SDRAM_ECC_CONTROL 0x1454
  198. #define MV64340_SDRAM_ECC_ERROR_COUNTER 0x1458
  199. /******************************************/
  200. /* Controlled Delay Line (CDL) Registers */
  201. /******************************************/
  202. #define MV64340_DFCDL_CONFIG0 0x1480
  203. #define MV64340_DFCDL_CONFIG1 0x1484
  204. #define MV64340_DLL_WRITE 0x1488
  205. #define MV64340_DLL_READ 0x148c
  206. #define MV64340_SRAM_ADDR 0x1490
  207. #define MV64340_SRAM_DATA0 0x1494
  208. #define MV64340_SRAM_DATA1 0x1498
  209. #define MV64340_SRAM_DATA2 0x149c
  210. #define MV64340_DFCL_PROBE 0x14a0
  211. /******************************************/
  212. /* Debug Registers */
  213. /******************************************/
  214. #define MV64340_DUNIT_DEBUG_LOW 0x1460
  215. #define MV64340_DUNIT_DEBUG_HIGH 0x1464
  216. #define MV64340_DUNIT_MMASK 0X1b40
  217. /****************************************/
  218. /* Device Parameters */
  219. /****************************************/
  220. #define MV64340_DEVICE_BANK0_PARAMETERS 0x45c
  221. #define MV64340_DEVICE_BANK1_PARAMETERS 0x460
  222. #define MV64340_DEVICE_BANK2_PARAMETERS 0x464
  223. #define MV64340_DEVICE_BANK3_PARAMETERS 0x468
  224. #define MV64340_DEVICE_BOOT_BANK_PARAMETERS 0x46c
  225. #define MV64340_DEVICE_INTERFACE_CONTROL 0x4c0
  226. #define MV64340_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8
  227. #define MV64340_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc
  228. #define MV64340_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4
  229. /****************************************/
  230. /* Device interrupt registers */
  231. /****************************************/
  232. #define MV64340_DEVICE_INTERRUPT_CAUSE 0x4d0
  233. #define MV64340_DEVICE_INTERRUPT_MASK 0x4d4
  234. #define MV64340_DEVICE_ERROR_ADDR 0x4d8
  235. #define MV64340_DEVICE_ERROR_DATA 0x4dc
  236. #define MV64340_DEVICE_ERROR_PARITY 0x4e0
  237. /****************************************/
  238. /* Device debug registers */
  239. /****************************************/
  240. #define MV64340_DEVICE_DEBUG_LOW 0x4e4
  241. #define MV64340_DEVICE_DEBUG_HIGH 0x4e8
  242. #define MV64340_RUNIT_MMASK 0x4f0
  243. /****************************************/
  244. /* PCI Slave Address Decoding registers */
  245. /****************************************/
  246. #define MV64340_PCI_0_CS_0_BANK_SIZE 0xc08
  247. #define MV64340_PCI_1_CS_0_BANK_SIZE 0xc88
  248. #define MV64340_PCI_0_CS_1_BANK_SIZE 0xd08
  249. #define MV64340_PCI_1_CS_1_BANK_SIZE 0xd88
  250. #define MV64340_PCI_0_CS_2_BANK_SIZE 0xc0c
  251. #define MV64340_PCI_1_CS_2_BANK_SIZE 0xc8c
  252. #define MV64340_PCI_0_CS_3_BANK_SIZE 0xd0c
  253. #define MV64340_PCI_1_CS_3_BANK_SIZE 0xd8c
  254. #define MV64340_PCI_0_DEVCS_0_BANK_SIZE 0xc10
  255. #define MV64340_PCI_1_DEVCS_0_BANK_SIZE 0xc90
  256. #define MV64340_PCI_0_DEVCS_1_BANK_SIZE 0xd10
  257. #define MV64340_PCI_1_DEVCS_1_BANK_SIZE 0xd90
  258. #define MV64340_PCI_0_DEVCS_2_BANK_SIZE 0xd18
  259. #define MV64340_PCI_1_DEVCS_2_BANK_SIZE 0xd98
  260. #define MV64340_PCI_0_DEVCS_3_BANK_SIZE 0xc14
  261. #define MV64340_PCI_1_DEVCS_3_BANK_SIZE 0xc94
  262. #define MV64340_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14
  263. #define MV64340_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94
  264. #define MV64340_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c
  265. #define MV64340_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c
  266. #define MV64340_PCI_0_P2P_MEM1_BAR_SIZE 0xd20
  267. #define MV64340_PCI_1_P2P_MEM1_BAR_SIZE 0xda0
  268. #define MV64340_PCI_0_P2P_I_O_BAR_SIZE 0xd24
  269. #define MV64340_PCI_1_P2P_I_O_BAR_SIZE 0xda4
  270. #define MV64340_PCI_0_CPU_BAR_SIZE 0xd28
  271. #define MV64340_PCI_1_CPU_BAR_SIZE 0xda8
  272. #define MV64340_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00
  273. #define MV64340_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80
  274. #define MV64340_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c
  275. #define MV64340_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c
  276. #define MV64340_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c
  277. #define MV64340_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc
  278. #define MV64340_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48
  279. #define MV64340_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8
  280. #define MV64340_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48
  281. #define MV64340_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8
  282. #define MV64340_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c
  283. #define MV64340_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc
  284. #define MV64340_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c
  285. #define MV64340_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc
  286. #define MV64340_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04
  287. #define MV64340_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84
  288. #define MV64340_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08
  289. #define MV64340_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88
  290. #define MV64340_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C
  291. #define MV64340_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C
  292. #define MV64340_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10
  293. #define MV64340_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90
  294. #define MV64340_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50
  295. #define MV64340_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0
  296. #define MV64340_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50
  297. #define MV64340_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0
  298. #define MV64340_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58
  299. #define MV64340_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8
  300. #define MV64340_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54
  301. #define MV64340_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4
  302. #define MV64340_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54
  303. #define MV64340_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4
  304. #define MV64340_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c
  305. #define MV64340_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc
  306. #define MV64340_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60
  307. #define MV64340_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0
  308. #define MV64340_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64
  309. #define MV64340_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4
  310. #define MV64340_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68
  311. #define MV64340_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8
  312. #define MV64340_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c
  313. #define MV64340_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec
  314. #define MV64340_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70
  315. #define MV64340_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0
  316. #define MV64340_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74
  317. #define MV64340_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4
  318. #define MV64340_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00
  319. #define MV64340_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80
  320. #define MV64340_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38
  321. #define MV64340_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8
  322. #define MV64340_PCI_0_ADDR_DECODE_CONTROL 0xd3c
  323. #define MV64340_PCI_1_ADDR_DECODE_CONTROL 0xdbc
  324. #define MV64340_PCI_0_HEADERS_RETARGET_CONTROL 0xF40
  325. #define MV64340_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0
  326. #define MV64340_PCI_0_HEADERS_RETARGET_BASE 0xF44
  327. #define MV64340_PCI_1_HEADERS_RETARGET_BASE 0xFc4
  328. #define MV64340_PCI_0_HEADERS_RETARGET_HIGH 0xF48
  329. #define MV64340_PCI_1_HEADERS_RETARGET_HIGH 0xFc8
  330. /***********************************/
  331. /* PCI Control Register Map */
  332. /***********************************/
  333. #define MV64340_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20
  334. #define MV64340_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0
  335. #define MV64340_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C
  336. #define MV64340_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C
  337. #define MV64340_PCI_0_COMMAND 0xc00
  338. #define MV64340_PCI_1_COMMAND 0xc80
  339. #define MV64340_PCI_0_MODE 0xd00
  340. #define MV64340_PCI_1_MODE 0xd80
  341. #define MV64340_PCI_0_RETRY 0xc04
  342. #define MV64340_PCI_1_RETRY 0xc84
  343. #define MV64340_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04
  344. #define MV64340_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84
  345. #define MV64340_PCI_0_MSI_TRIGGER_TIMER 0xc38
  346. #define MV64340_PCI_1_MSI_TRIGGER_TIMER 0xcb8
  347. #define MV64340_PCI_0_ARBITER_CONTROL 0x1d00
  348. #define MV64340_PCI_1_ARBITER_CONTROL 0x1d80
  349. #define MV64340_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08
  350. #define MV64340_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88
  351. #define MV64340_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c
  352. #define MV64340_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c
  353. #define MV64340_PCI_0_CROSS_BAR_TIMEOUT 0x1d04
  354. #define MV64340_PCI_1_CROSS_BAR_TIMEOUT 0x1d84
  355. #define MV64340_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18
  356. #define MV64340_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98
  357. #define MV64340_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10
  358. #define MV64340_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90
  359. #define MV64340_PCI_0_P2P_CONFIG 0x1d14
  360. #define MV64340_PCI_1_P2P_CONFIG 0x1d94
  361. #define MV64340_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00
  362. #define MV64340_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04
  363. #define MV64340_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08
  364. #define MV64340_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10
  365. #define MV64340_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14
  366. #define MV64340_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18
  367. #define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20
  368. #define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24
  369. #define MV64340_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28
  370. #define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30
  371. #define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34
  372. #define MV64340_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38
  373. #define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40
  374. #define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44
  375. #define MV64340_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48
  376. #define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50
  377. #define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54
  378. #define MV64340_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58
  379. #define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80
  380. #define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84
  381. #define MV64340_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88
  382. #define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90
  383. #define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94
  384. #define MV64340_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98
  385. #define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0
  386. #define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
  387. #define MV64340_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8
  388. #define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0
  389. #define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
  390. #define MV64340_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8
  391. #define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0
  392. #define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
  393. #define MV64340_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8
  394. #define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0
  395. #define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
  396. #define MV64340_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8
  397. /****************************************/
  398. /* PCI Configuration Access Registers */
  399. /****************************************/
  400. #define MV64340_PCI_0_CONFIG_ADDR 0xcf8
  401. #define MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc
  402. #define MV64340_PCI_1_CONFIG_ADDR 0xc78
  403. #define MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c
  404. #define MV64340_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34
  405. #define MV64340_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4
  406. /****************************************/
  407. /* PCI Error Report Registers */
  408. /****************************************/
  409. #define MV64340_PCI_0_SERR_MASK 0xc28
  410. #define MV64340_PCI_1_SERR_MASK 0xca8
  411. #define MV64340_PCI_0_ERROR_ADDR_LOW 0x1d40
  412. #define MV64340_PCI_1_ERROR_ADDR_LOW 0x1dc0
  413. #define MV64340_PCI_0_ERROR_ADDR_HIGH 0x1d44
  414. #define MV64340_PCI_1_ERROR_ADDR_HIGH 0x1dc4
  415. #define MV64340_PCI_0_ERROR_ATTRIBUTE 0x1d48
  416. #define MV64340_PCI_1_ERROR_ATTRIBUTE 0x1dc8
  417. #define MV64340_PCI_0_ERROR_COMMAND 0x1d50
  418. #define MV64340_PCI_1_ERROR_COMMAND 0x1dd0
  419. #define MV64340_PCI_0_ERROR_CAUSE 0x1d58
  420. #define MV64340_PCI_1_ERROR_CAUSE 0x1dd8
  421. #define MV64340_PCI_0_ERROR_MASK 0x1d5c
  422. #define MV64340_PCI_1_ERROR_MASK 0x1ddc
  423. /****************************************/
  424. /* PCI Debug Registers */
  425. /****************************************/
  426. #define MV64340_PCI_0_MMASK 0X1D24
  427. #define MV64340_PCI_1_MMASK 0X1DA4
  428. /*********************************************/
  429. /* PCI Configuration, Function 0, Registers */
  430. /*********************************************/
  431. #define MV64340_PCI_DEVICE_AND_VENDOR_ID 0x000
  432. #define MV64340_PCI_STATUS_AND_COMMAND 0x004
  433. #define MV64340_PCI_CLASS_CODE_AND_REVISION_ID 0x008
  434. #define MV64340_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
  435. #define MV64340_PCI_SCS_0_BASE_ADDR_LOW 0x010
  436. #define MV64340_PCI_SCS_0_BASE_ADDR_HIGH 0x014
  437. #define MV64340_PCI_SCS_1_BASE_ADDR_LOW 0x018
  438. #define MV64340_PCI_SCS_1_BASE_ADDR_HIGH 0x01C
  439. #define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020
  440. #define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024
  441. #define MV64340_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c
  442. #define MV64340_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030
  443. #define MV64340_PCI_CAPABILTY_LIST_POINTER 0x034
  444. #define MV64340_PCI_INTERRUPT_PIN_AND_LINE 0x03C
  445. /* capability list */
  446. #define MV64340_PCI_POWER_MANAGEMENT_CAPABILITY 0x040
  447. #define MV64340_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
  448. #define MV64340_PCI_VPD_ADDR 0x048
  449. #define MV64340_PCI_VPD_DATA 0x04c
  450. #define MV64340_PCI_MSI_MESSAGE_CONTROL 0x050
  451. #define MV64340_PCI_MSI_MESSAGE_ADDR 0x054
  452. #define MV64340_PCI_MSI_MESSAGE_UPPER_ADDR 0x058
  453. #define MV64340_PCI_MSI_MESSAGE_DATA 0x05c
  454. #define MV64340_PCI_X_COMMAND 0x060
  455. #define MV64340_PCI_X_STATUS 0x064
  456. #define MV64340_PCI_COMPACT_PCI_HOT_SWAP 0x068
  457. /***********************************************/
  458. /* PCI Configuration, Function 1, Registers */
  459. /***********************************************/
  460. #define MV64340_PCI_SCS_2_BASE_ADDR_LOW 0x110
  461. #define MV64340_PCI_SCS_2_BASE_ADDR_HIGH 0x114
  462. #define MV64340_PCI_SCS_3_BASE_ADDR_LOW 0x118
  463. #define MV64340_PCI_SCS_3_BASE_ADDR_HIGH 0x11c
  464. #define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120
  465. #define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124
  466. /***********************************************/
  467. /* PCI Configuration, Function 2, Registers */
  468. /***********************************************/
  469. #define MV64340_PCI_DEVCS_0_BASE_ADDR_LOW 0x210
  470. #define MV64340_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214
  471. #define MV64340_PCI_DEVCS_1_BASE_ADDR_LOW 0x218
  472. #define MV64340_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c
  473. #define MV64340_PCI_DEVCS_2_BASE_ADDR_LOW 0x220
  474. #define MV64340_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224
  475. /***********************************************/
  476. /* PCI Configuration, Function 3, Registers */
  477. /***********************************************/
  478. #define MV64340_PCI_DEVCS_3_BASE_ADDR_LOW 0x310
  479. #define MV64340_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314
  480. #define MV64340_PCI_BOOT_CS_BASE_ADDR_LOW 0x318
  481. #define MV64340_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c
  482. #define MV64340_PCI_CPU_BASE_ADDR_LOW 0x220
  483. #define MV64340_PCI_CPU_BASE_ADDR_HIGH 0x224
  484. /***********************************************/
  485. /* PCI Configuration, Function 4, Registers */
  486. /***********************************************/
  487. #define MV64340_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410
  488. #define MV64340_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414
  489. #define MV64340_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418
  490. #define MV64340_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c
  491. #define MV64340_PCI_P2P_I_O_BASE_ADDR 0x420
  492. #define MV64340_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424
  493. /****************************************/
  494. /* Messaging Unit Registers (I20) */
  495. /****************************************/
  496. #define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010
  497. #define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014
  498. #define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018
  499. #define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C
  500. #define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020
  501. #define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024
  502. #define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028
  503. #define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C
  504. #define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030
  505. #define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034
  506. #define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040
  507. #define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044
  508. #define MV64340_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050
  509. #define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054
  510. #define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060
  511. #define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064
  512. #define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068
  513. #define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C
  514. #define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070
  515. #define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074
  516. #define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8
  517. #define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC
  518. #define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090
  519. #define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094
  520. #define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098
  521. #define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C
  522. #define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0
  523. #define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4
  524. #define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8
  525. #define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC
  526. #define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0
  527. #define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4
  528. #define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0
  529. #define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4
  530. #define MV64340_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0
  531. #define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4
  532. #define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0
  533. #define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4
  534. #define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8
  535. #define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC
  536. #define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0
  537. #define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4
  538. #define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078
  539. #define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C
  540. #define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10
  541. #define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14
  542. #define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18
  543. #define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C
  544. #define MV64340_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20
  545. #define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24
  546. #define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28
  547. #define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C
  548. #define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30
  549. #define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34
  550. #define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40
  551. #define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44
  552. #define MV64340_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50
  553. #define MV64340_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54
  554. #define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60
  555. #define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64
  556. #define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68
  557. #define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C
  558. #define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70
  559. #define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74
  560. #define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8
  561. #define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC
  562. #define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90
  563. #define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94
  564. #define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98
  565. #define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C
  566. #define MV64340_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0
  567. #define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4
  568. #define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8
  569. #define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC
  570. #define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0
  571. #define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4
  572. #define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0
  573. #define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4
  574. #define MV64340_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0
  575. #define MV64340_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4
  576. #define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0
  577. #define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4
  578. #define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8
  579. #define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC
  580. #define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0
  581. #define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4
  582. #define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78
  583. #define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C
  584. /****************************************/
  585. /* Ethernet Unit Registers */
  586. /****************************************/
  587. /*******************************************/
  588. /* CUNIT Registers */
  589. /*******************************************/
  590. /* Address Decoding Register Map */
  591. #define MV64340_CUNIT_BASE_ADDR_REG0 0xf200
  592. #define MV64340_CUNIT_BASE_ADDR_REG1 0xf208
  593. #define MV64340_CUNIT_BASE_ADDR_REG2 0xf210
  594. #define MV64340_CUNIT_BASE_ADDR_REG3 0xf218
  595. #define MV64340_CUNIT_SIZE0 0xf204
  596. #define MV64340_CUNIT_SIZE1 0xf20c
  597. #define MV64340_CUNIT_SIZE2 0xf214
  598. #define MV64340_CUNIT_SIZE3 0xf21c
  599. #define MV64340_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240
  600. #define MV64340_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244
  601. #define MV64340_CUNIT_BASE_ADDR_ENABLE_REG 0xf250
  602. #define MV64340_MPSC0_ACCESS_PROTECTION_REG 0xf254
  603. #define MV64340_MPSC1_ACCESS_PROTECTION_REG 0xf258
  604. #define MV64340_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C
  605. /* Error Report Registers */
  606. #define MV64340_CUNIT_INTERRUPT_CAUSE_REG 0xf310
  607. #define MV64340_CUNIT_INTERRUPT_MASK_REG 0xf314
  608. #define MV64340_CUNIT_ERROR_ADDR 0xf318
  609. /* Cunit Control Registers */
  610. #define MV64340_CUNIT_ARBITER_CONTROL_REG 0xf300
  611. #define MV64340_CUNIT_CONFIG_REG 0xb40c
  612. #define MV64340_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304
  613. /* Cunit Debug Registers */
  614. #define MV64340_CUNIT_DEBUG_LOW 0xf340
  615. #define MV64340_CUNIT_DEBUG_HIGH 0xf344
  616. #define MV64340_CUNIT_MMASK 0xf380
  617. /* MPSCs Clocks Routing Registers */
  618. #define MV64340_MPSC_ROUTING_REG 0xb400
  619. #define MV64340_MPSC_RX_CLOCK_ROUTING_REG 0xb404
  620. #define MV64340_MPSC_TX_CLOCK_ROUTING_REG 0xb408
  621. /* MPSCs Interrupts Registers */
  622. #define MV64340_MPSC_CAUSE_REG(port) (0xb804 + (port<<3))
  623. #define MV64340_MPSC_MASK_REG(port) (0xb884 + (port<<3))
  624. #define MV64340_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12))
  625. #define MV64340_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12))
  626. #define MV64340_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12))
  627. #define MV64340_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12))
  628. #define MV64340_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12))
  629. #define MV64340_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12))
  630. #define MV64340_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12))
  631. #define MV64340_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12))
  632. #define MV64340_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12))
  633. #define MV64340_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12))
  634. #define MV64340_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12))
  635. #define MV64340_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12))
  636. #define MV64340_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12))
  637. /* MPSC0 Registers */
  638. /***************************************/
  639. /* SDMA Registers */
  640. /***************************************/
  641. #define MV64340_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13))
  642. #define MV64340_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13))
  643. #define MV64340_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13))
  644. #define MV64340_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13))
  645. #define MV64340_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13))
  646. #define MV64340_SDMA_CAUSE_REG 0xb800
  647. #define MV64340_SDMA_MASK_REG 0xb880
  648. /* BRG Interrupts */
  649. #define MV64340_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3))
  650. #define MV64340_BRG_BAUDE_TUNING_REG(brg) (0xb208 + (brg<<3))
  651. #define MV64340_BRG_CAUSE_REG 0xb834
  652. #define MV64340_BRG_MASK_REG 0xb8b4
  653. /****************************************/
  654. /* DMA Channel Control */
  655. /****************************************/
  656. #define MV64340_DMA_CHANNEL0_CONTROL 0x840
  657. #define MV64340_DMA_CHANNEL0_CONTROL_HIGH 0x880
  658. #define MV64340_DMA_CHANNEL1_CONTROL 0x844
  659. #define MV64340_DMA_CHANNEL1_CONTROL_HIGH 0x884
  660. #define MV64340_DMA_CHANNEL2_CONTROL 0x848
  661. #define MV64340_DMA_CHANNEL2_CONTROL_HIGH 0x888
  662. #define MV64340_DMA_CHANNEL3_CONTROL 0x84C
  663. #define MV64340_DMA_CHANNEL3_CONTROL_HIGH 0x88C
  664. /****************************************/
  665. /* IDMA Registers */
  666. /****************************************/
  667. #define MV64340_DMA_CHANNEL0_BYTE_COUNT 0x800
  668. #define MV64340_DMA_CHANNEL1_BYTE_COUNT 0x804
  669. #define MV64340_DMA_CHANNEL2_BYTE_COUNT 0x808
  670. #define MV64340_DMA_CHANNEL3_BYTE_COUNT 0x80C
  671. #define MV64340_DMA_CHANNEL0_SOURCE_ADDR 0x810
  672. #define MV64340_DMA_CHANNEL1_SOURCE_ADDR 0x814
  673. #define MV64340_DMA_CHANNEL2_SOURCE_ADDR 0x818
  674. #define MV64340_DMA_CHANNEL3_SOURCE_ADDR 0x81c
  675. #define MV64340_DMA_CHANNEL0_DESTINATION_ADDR 0x820
  676. #define MV64340_DMA_CHANNEL1_DESTINATION_ADDR 0x824
  677. #define MV64340_DMA_CHANNEL2_DESTINATION_ADDR 0x828
  678. #define MV64340_DMA_CHANNEL3_DESTINATION_ADDR 0x82C
  679. #define MV64340_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830
  680. #define MV64340_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834
  681. #define MV64340_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838
  682. #define MV64340_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C
  683. #define MV64340_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870
  684. #define MV64340_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874
  685. #define MV64340_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878
  686. #define MV64340_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C
  687. /* IDMA Address Decoding Base Address Registers */
  688. #define MV64340_DMA_BASE_ADDR_REG0 0xa00
  689. #define MV64340_DMA_BASE_ADDR_REG1 0xa08
  690. #define MV64340_DMA_BASE_ADDR_REG2 0xa10
  691. #define MV64340_DMA_BASE_ADDR_REG3 0xa18
  692. #define MV64340_DMA_BASE_ADDR_REG4 0xa20
  693. #define MV64340_DMA_BASE_ADDR_REG5 0xa28
  694. #define MV64340_DMA_BASE_ADDR_REG6 0xa30
  695. #define MV64340_DMA_BASE_ADDR_REG7 0xa38
  696. /* IDMA Address Decoding Size Address Register */
  697. #define MV64340_DMA_SIZE_REG0 0xa04
  698. #define MV64340_DMA_SIZE_REG1 0xa0c
  699. #define MV64340_DMA_SIZE_REG2 0xa14
  700. #define MV64340_DMA_SIZE_REG3 0xa1c
  701. #define MV64340_DMA_SIZE_REG4 0xa24
  702. #define MV64340_DMA_SIZE_REG5 0xa2c
  703. #define MV64340_DMA_SIZE_REG6 0xa34
  704. #define MV64340_DMA_SIZE_REG7 0xa3C
  705. /* IDMA Address Decoding High Address Remap and Access
  706. Protection Registers */
  707. #define MV64340_DMA_HIGH_ADDR_REMAP_REG0 0xa60
  708. #define MV64340_DMA_HIGH_ADDR_REMAP_REG1 0xa64
  709. #define MV64340_DMA_HIGH_ADDR_REMAP_REG2 0xa68
  710. #define MV64340_DMA_HIGH_ADDR_REMAP_REG3 0xa6C
  711. #define MV64340_DMA_BASE_ADDR_ENABLE_REG 0xa80
  712. #define MV64340_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70
  713. #define MV64340_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74
  714. #define MV64340_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78
  715. #define MV64340_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c
  716. #define MV64340_DMA_ARBITER_CONTROL 0x860
  717. #define MV64340_DMA_CROSS_BAR_TIMEOUT 0x8d0
  718. /* IDMA Headers Retarget Registers */
  719. #define MV64340_DMA_HEADERS_RETARGET_CONTROL 0xa84
  720. #define MV64340_DMA_HEADERS_RETARGET_BASE 0xa88
  721. /* IDMA Interrupt Register */
  722. #define MV64340_DMA_INTERRUPT_CAUSE_REG 0x8c0
  723. #define MV64340_DMA_INTERRUPT_CAUSE_MASK 0x8c4
  724. #define MV64340_DMA_ERROR_ADDR 0x8c8
  725. #define MV64340_DMA_ERROR_SELECT 0x8cc
  726. /* IDMA Debug Register ( for internal use ) */
  727. #define MV64340_DMA_DEBUG_LOW 0x8e0
  728. #define MV64340_DMA_DEBUG_HIGH 0x8e4
  729. #define MV64340_DMA_SPARE 0xA8C
  730. /****************************************/
  731. /* Timer_Counter */
  732. /****************************************/
  733. #define MV64340_TIMER_COUNTER0 0x850
  734. #define MV64340_TIMER_COUNTER1 0x854
  735. #define MV64340_TIMER_COUNTER2 0x858
  736. #define MV64340_TIMER_COUNTER3 0x85C
  737. #define MV64340_TIMER_COUNTER_0_3_CONTROL 0x864
  738. #define MV64340_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868
  739. #define MV64340_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c
  740. /****************************************/
  741. /* Watchdog registers */
  742. /****************************************/
  743. #define MV64340_WATCHDOG_CONFIG_REG 0xb410
  744. #define MV64340_WATCHDOG_VALUE_REG 0xb414
  745. /****************************************/
  746. /* I2C Registers */
  747. /****************************************/
  748. #define MV64XXX_I2C_OFFSET 0xc000
  749. #define MV64XXX_I2C_REG_BLOCK_SIZE 0x0020
  750. /****************************************/
  751. /* GPP Interface Registers */
  752. /****************************************/
  753. #define MV64340_GPP_IO_CONTROL 0xf100
  754. #define MV64340_GPP_LEVEL_CONTROL 0xf110
  755. #define MV64340_GPP_VALUE 0xf104
  756. #define MV64340_GPP_INTERRUPT_CAUSE 0xf108
  757. #define MV64340_GPP_INTERRUPT_MASK0 0xf10c
  758. #define MV64340_GPP_INTERRUPT_MASK1 0xf114
  759. #define MV64340_GPP_VALUE_SET 0xf118
  760. #define MV64340_GPP_VALUE_CLEAR 0xf11c
  761. /****************************************/
  762. /* Interrupt Controller Registers */
  763. /****************************************/
  764. /****************************************/
  765. /* Interrupts */
  766. /****************************************/
  767. #define MV64340_MAIN_INTERRUPT_CAUSE_LOW 0x004
  768. #define MV64340_MAIN_INTERRUPT_CAUSE_HIGH 0x00c
  769. #define MV64340_CPU_INTERRUPT0_MASK_LOW 0x014
  770. #define MV64340_CPU_INTERRUPT0_MASK_HIGH 0x01c
  771. #define MV64340_CPU_INTERRUPT0_SELECT_CAUSE 0x024
  772. #define MV64340_CPU_INTERRUPT1_MASK_LOW 0x034
  773. #define MV64340_CPU_INTERRUPT1_MASK_HIGH 0x03c
  774. #define MV64340_CPU_INTERRUPT1_SELECT_CAUSE 0x044
  775. #define MV64340_INTERRUPT0_MASK_0_LOW 0x054
  776. #define MV64340_INTERRUPT0_MASK_0_HIGH 0x05c
  777. #define MV64340_INTERRUPT0_SELECT_CAUSE 0x064
  778. #define MV64340_INTERRUPT1_MASK_0_LOW 0x074
  779. #define MV64340_INTERRUPT1_MASK_0_HIGH 0x07c
  780. #define MV64340_INTERRUPT1_SELECT_CAUSE 0x084
  781. /****************************************/
  782. /* MPP Interface Registers */
  783. /****************************************/
  784. #define MV64340_MPP_CONTROL0 0xf000
  785. #define MV64340_MPP_CONTROL1 0xf004
  786. #define MV64340_MPP_CONTROL2 0xf008
  787. #define MV64340_MPP_CONTROL3 0xf00c
  788. /****************************************/
  789. /* Serial Initialization registers */
  790. /****************************************/
  791. #define MV64340_SERIAL_INIT_LAST_DATA 0xf324
  792. #define MV64340_SERIAL_INIT_CONTROL 0xf328
  793. #define MV64340_SERIAL_INIT_STATUS 0xf32c
  794. extern void mv64340_irq_init(unsigned int base);
  795. /* Watchdog Platform Device, Driver Data */
  796. #define MV64x60_WDT_NAME "mv64x60_wdt"
  797. struct mv64x60_wdt_pdata {
  798. int timeout; /* watchdog expiry in seconds, default 10 */
  799. int bus_clk; /* bus clock in MHz, default 133 */
  800. };
  801. #endif /* __ASM_MV643XX_H */