sh_mmcif.h 5.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * include/linux/mmc/sh_mmcif.h
  4. *
  5. * platform data for eMMC driver
  6. *
  7. * Copyright (C) 2010 Renesas Solutions Corp.
  8. */
  9. #ifndef LINUX_MMC_SH_MMCIF_H
  10. #define LINUX_MMC_SH_MMCIF_H
  11. #include <linux/io.h>
  12. #include <linux/platform_device.h>
  13. /*
  14. * MMCIF : CE_CLK_CTRL [19:16]
  15. * 1000 : Peripheral clock / 512
  16. * 0111 : Peripheral clock / 256
  17. * 0110 : Peripheral clock / 128
  18. * 0101 : Peripheral clock / 64
  19. * 0100 : Peripheral clock / 32
  20. * 0011 : Peripheral clock / 16
  21. * 0010 : Peripheral clock / 8
  22. * 0001 : Peripheral clock / 4
  23. * 0000 : Peripheral clock / 2
  24. * 1111 : Peripheral clock (sup_pclk set '1')
  25. */
  26. struct sh_mmcif_plat_data {
  27. unsigned int slave_id_tx; /* embedded slave_id_[tr]x */
  28. unsigned int slave_id_rx;
  29. u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */
  30. unsigned long caps;
  31. u32 ocr;
  32. };
  33. #define MMCIF_CE_CMD_SET 0x00000000
  34. #define MMCIF_CE_ARG 0x00000008
  35. #define MMCIF_CE_ARG_CMD12 0x0000000C
  36. #define MMCIF_CE_CMD_CTRL 0x00000010
  37. #define MMCIF_CE_BLOCK_SET 0x00000014
  38. #define MMCIF_CE_CLK_CTRL 0x00000018
  39. #define MMCIF_CE_BUF_ACC 0x0000001C
  40. #define MMCIF_CE_RESP3 0x00000020
  41. #define MMCIF_CE_RESP2 0x00000024
  42. #define MMCIF_CE_RESP1 0x00000028
  43. #define MMCIF_CE_RESP0 0x0000002C
  44. #define MMCIF_CE_RESP_CMD12 0x00000030
  45. #define MMCIF_CE_DATA 0x00000034
  46. #define MMCIF_CE_INT 0x00000040
  47. #define MMCIF_CE_INT_MASK 0x00000044
  48. #define MMCIF_CE_HOST_STS1 0x00000048
  49. #define MMCIF_CE_HOST_STS2 0x0000004C
  50. #define MMCIF_CE_CLK_CTRL2 0x00000070
  51. #define MMCIF_CE_VERSION 0x0000007C
  52. /* CE_BUF_ACC */
  53. #define BUF_ACC_DMAWEN (1 << 25)
  54. #define BUF_ACC_DMAREN (1 << 24)
  55. #define BUF_ACC_BUSW_32 (0 << 17)
  56. #define BUF_ACC_BUSW_16 (1 << 17)
  57. #define BUF_ACC_ATYP (1 << 16)
  58. /* CE_CLK_CTRL */
  59. #define CLK_ENABLE (1 << 24) /* 1: output mmc clock */
  60. #define CLK_CLEAR (0xf << 16)
  61. #define CLK_SUP_PCLK (0xf << 16)
  62. #define CLKDIV_4 (1 << 16) /* mmc clock frequency.
  63. * n: bus clock/(2^(n+1)) */
  64. #define CLKDIV_256 (7 << 16) /* mmc clock frequency. (see above) */
  65. #define SRSPTO_256 (2 << 12) /* resp timeout */
  66. #define SRBSYTO_29 (0xf << 8) /* resp busy timeout */
  67. #define SRWDTO_29 (0xf << 4) /* read/write timeout */
  68. #define SCCSTO_29 (0xf << 0) /* ccs timeout */
  69. /* CE_VERSION */
  70. #define SOFT_RST_ON (1 << 31)
  71. #define SOFT_RST_OFF 0
  72. static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
  73. {
  74. return __raw_readl(addr + reg);
  75. }
  76. static inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
  77. {
  78. __raw_writel(val, addr + reg);
  79. }
  80. #define SH_MMCIF_BBS 512 /* boot block size */
  81. static inline void sh_mmcif_boot_cmd_send(void __iomem *base,
  82. unsigned long cmd, unsigned long arg)
  83. {
  84. sh_mmcif_writel(base, MMCIF_CE_INT, 0);
  85. sh_mmcif_writel(base, MMCIF_CE_ARG, arg);
  86. sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd);
  87. }
  88. static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
  89. {
  90. unsigned long tmp;
  91. int cnt;
  92. for (cnt = 0; cnt < 1000000; cnt++) {
  93. tmp = sh_mmcif_readl(base, MMCIF_CE_INT);
  94. if (tmp & mask) {
  95. sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask);
  96. return 0;
  97. }
  98. }
  99. return -1;
  100. }
  101. static inline int sh_mmcif_boot_cmd(void __iomem *base,
  102. unsigned long cmd, unsigned long arg)
  103. {
  104. sh_mmcif_boot_cmd_send(base, cmd, arg);
  105. return sh_mmcif_boot_cmd_poll(base, 0x00010000);
  106. }
  107. static inline int sh_mmcif_boot_do_read_single(void __iomem *base,
  108. unsigned int block_nr,
  109. unsigned long *buf)
  110. {
  111. int k;
  112. /* CMD13 - Status */
  113. sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000);
  114. if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900)
  115. return -1;
  116. /* CMD17 - Read */
  117. sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS);
  118. if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0)
  119. return -1;
  120. for (k = 0; k < (SH_MMCIF_BBS / 4); k++)
  121. buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA);
  122. return 0;
  123. }
  124. static inline int sh_mmcif_boot_do_read(void __iomem *base,
  125. unsigned long first_block,
  126. unsigned long nr_blocks,
  127. void *buf)
  128. {
  129. unsigned long k;
  130. int ret = 0;
  131. /* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
  132. sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
  133. CLK_ENABLE | CLKDIV_4 | SRSPTO_256 |
  134. SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
  135. /* CMD9 - Get CSD */
  136. sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);
  137. /* CMD7 - Select the card */
  138. sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);
  139. /* CMD16 - Set the block size */
  140. sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS);
  141. for (k = 0; !ret && k < nr_blocks; k++)
  142. ret = sh_mmcif_boot_do_read_single(base, first_block + k,
  143. buf + (k * SH_MMCIF_BBS));
  144. return ret;
  145. }
  146. static inline void sh_mmcif_boot_init(void __iomem *base)
  147. {
  148. /* reset */
  149. sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON);
  150. sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF);
  151. /* byte swap */
  152. sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
  153. /* Set block size in MMCIF hardware */
  154. sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
  155. /* Enable the clock, set it to Bus clock/256 (about 325Khz). */
  156. sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
  157. CLK_ENABLE | CLKDIV_256 | SRSPTO_256 |
  158. SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
  159. /* CMD0 */
  160. sh_mmcif_boot_cmd(base, 0x00000040, 0);
  161. /* CMD1 - Get OCR */
  162. do {
  163. sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */
  164. } while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000)
  165. != 0x80000000);
  166. /* CMD2 - Get CID */
  167. sh_mmcif_boot_cmd(base, 0x02806040, 0);
  168. /* CMD3 - Set card relative address */
  169. sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);
  170. }
  171. #endif /* LINUX_MMC_SH_MMCIF_H */