sdio.h 6.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * include/linux/mmc/sdio.h
  4. *
  5. * Copyright 2006-2007 Pierre Ossman
  6. */
  7. #ifndef LINUX_MMC_SDIO_H
  8. #define LINUX_MMC_SDIO_H
  9. /* SDIO commands type argument response */
  10. #define SD_IO_SEND_OP_COND 5 /* bcr [23:0] OCR R4 */
  11. #define SD_IO_RW_DIRECT 52 /* ac [31:0] See below R5 */
  12. #define SD_IO_RW_EXTENDED 53 /* adtc [31:0] See below R5 */
  13. /*
  14. * SD_IO_RW_DIRECT argument format:
  15. *
  16. * [31] R/W flag
  17. * [30:28] Function number
  18. * [27] RAW flag
  19. * [25:9] Register address
  20. * [7:0] Data
  21. */
  22. /*
  23. * SD_IO_RW_EXTENDED argument format:
  24. *
  25. * [31] R/W flag
  26. * [30:28] Function number
  27. * [27] Block mode
  28. * [26] Increment address
  29. * [25:9] Register address
  30. * [8:0] Byte/block count
  31. */
  32. #define R4_18V_PRESENT (1<<24)
  33. #define R4_MEMORY_PRESENT (1 << 27)
  34. /*
  35. SDIO status in R5
  36. Type
  37. e : error bit
  38. s : status bit
  39. r : detected and set for the actual command response
  40. x : detected and set during command execution. the host must poll
  41. the card by sending status command in order to read these bits.
  42. Clear condition
  43. a : according to the card state
  44. b : always related to the previous command. Reception of
  45. a valid command will clear it (with a delay of one command)
  46. c : clear by read
  47. */
  48. #define R5_COM_CRC_ERROR (1 << 15) /* er, b */
  49. #define R5_ILLEGAL_COMMAND (1 << 14) /* er, b */
  50. #define R5_ERROR (1 << 11) /* erx, c */
  51. #define R5_FUNCTION_NUMBER (1 << 9) /* er, c */
  52. #define R5_OUT_OF_RANGE (1 << 8) /* er, c */
  53. #define R5_STATUS(x) (x & 0xCB00)
  54. #define R5_IO_CURRENT_STATE(x) ((x & 0x3000) >> 12) /* s, b */
  55. /*
  56. * Card Common Control Registers (CCCR)
  57. */
  58. #define SDIO_CCCR_CCCR 0x00
  59. #define SDIO_CCCR_REV_1_00 0 /* CCCR/FBR Version 1.00 */
  60. #define SDIO_CCCR_REV_1_10 1 /* CCCR/FBR Version 1.10 */
  61. #define SDIO_CCCR_REV_1_20 2 /* CCCR/FBR Version 1.20 */
  62. #define SDIO_CCCR_REV_3_00 3 /* CCCR/FBR Version 3.00 */
  63. #define SDIO_SDIO_REV_1_00 0 /* SDIO Spec Version 1.00 */
  64. #define SDIO_SDIO_REV_1_10 1 /* SDIO Spec Version 1.10 */
  65. #define SDIO_SDIO_REV_1_20 2 /* SDIO Spec Version 1.20 */
  66. #define SDIO_SDIO_REV_2_00 3 /* SDIO Spec Version 2.00 */
  67. #define SDIO_SDIO_REV_3_00 4 /* SDIO Spec Version 3.00 */
  68. #define SDIO_CCCR_SD 0x01
  69. #define SDIO_SD_REV_1_01 0 /* SD Physical Spec Version 1.01 */
  70. #define SDIO_SD_REV_1_10 1 /* SD Physical Spec Version 1.10 */
  71. #define SDIO_SD_REV_2_00 2 /* SD Physical Spec Version 2.00 */
  72. #define SDIO_SD_REV_3_00 3 /* SD Physical Spev Version 3.00 */
  73. #define SDIO_CCCR_IOEx 0x02
  74. #define SDIO_CCCR_IORx 0x03
  75. #define SDIO_CCCR_IENx 0x04 /* Function/Master Interrupt Enable */
  76. #define SDIO_CCCR_INTx 0x05 /* Function Interrupt Pending */
  77. #define SDIO_CCCR_ABORT 0x06 /* function abort/card reset */
  78. #define SDIO_CCCR_IF 0x07 /* bus interface controls */
  79. #define SDIO_BUS_WIDTH_MASK 0x03 /* data bus width setting */
  80. #define SDIO_BUS_WIDTH_1BIT 0x00
  81. #define SDIO_BUS_WIDTH_RESERVED 0x01
  82. #define SDIO_BUS_WIDTH_4BIT 0x02
  83. #define SDIO_BUS_ECSI 0x20 /* Enable continuous SPI interrupt */
  84. #define SDIO_BUS_SCSI 0x40 /* Support continuous SPI interrupt */
  85. #define SDIO_BUS_ASYNC_INT 0x20
  86. #define SDIO_BUS_CD_DISABLE 0x80 /* disable pull-up on DAT3 (pin 1) */
  87. #define SDIO_CCCR_CAPS 0x08
  88. #define SDIO_CCCR_CAP_SDC 0x01 /* can do CMD52 while data transfer */
  89. #define SDIO_CCCR_CAP_SMB 0x02 /* can do multi-block xfers (CMD53) */
  90. #define SDIO_CCCR_CAP_SRW 0x04 /* supports read-wait protocol */
  91. #define SDIO_CCCR_CAP_SBS 0x08 /* supports suspend/resume */
  92. #define SDIO_CCCR_CAP_S4MI 0x10 /* interrupt during 4-bit CMD53 */
  93. #define SDIO_CCCR_CAP_E4MI 0x20 /* enable ints during 4-bit CMD53 */
  94. #define SDIO_CCCR_CAP_LSC 0x40 /* low speed card */
  95. #define SDIO_CCCR_CAP_4BLS 0x80 /* 4 bit low speed card */
  96. #define SDIO_CCCR_CIS 0x09 /* common CIS pointer (3 bytes) */
  97. /* Following 4 regs are valid only if SBS is set */
  98. #define SDIO_CCCR_SUSPEND 0x0c
  99. #define SDIO_CCCR_SELx 0x0d
  100. #define SDIO_CCCR_EXECx 0x0e
  101. #define SDIO_CCCR_READYx 0x0f
  102. #define SDIO_CCCR_BLKSIZE 0x10
  103. #define SDIO_CCCR_POWER 0x12
  104. #define SDIO_POWER_SMPC 0x01 /* Supports Master Power Control */
  105. #define SDIO_POWER_EMPC 0x02 /* Enable Master Power Control */
  106. #define SDIO_CCCR_SPEED 0x13
  107. #define SDIO_SPEED_SHS 0x01 /* Supports High-Speed mode */
  108. #define SDIO_SPEED_BSS_SHIFT 1
  109. #define SDIO_SPEED_BSS_MASK (7<<SDIO_SPEED_BSS_SHIFT)
  110. #define SDIO_SPEED_SDR12 (0<<SDIO_SPEED_BSS_SHIFT)
  111. #define SDIO_SPEED_SDR25 (1<<SDIO_SPEED_BSS_SHIFT)
  112. #define SDIO_SPEED_SDR50 (2<<SDIO_SPEED_BSS_SHIFT)
  113. #define SDIO_SPEED_SDR104 (3<<SDIO_SPEED_BSS_SHIFT)
  114. #define SDIO_SPEED_DDR50 (4<<SDIO_SPEED_BSS_SHIFT)
  115. #define SDIO_SPEED_EHS SDIO_SPEED_SDR25 /* Enable High-Speed */
  116. #define SDIO_CCCR_UHS 0x14
  117. #define SDIO_UHS_SDR50 0x01
  118. #define SDIO_UHS_SDR104 0x02
  119. #define SDIO_UHS_DDR50 0x04
  120. #define SDIO_CCCR_DRIVE_STRENGTH 0x15
  121. #define SDIO_SDTx_MASK 0x07
  122. #define SDIO_DRIVE_SDTA (1<<0)
  123. #define SDIO_DRIVE_SDTC (1<<1)
  124. #define SDIO_DRIVE_SDTD (1<<2)
  125. #define SDIO_DRIVE_DTSx_MASK 0x03
  126. #define SDIO_DRIVE_DTSx_SHIFT 4
  127. #define SDIO_DTSx_SET_TYPE_B (0 << SDIO_DRIVE_DTSx_SHIFT)
  128. #define SDIO_DTSx_SET_TYPE_A (1 << SDIO_DRIVE_DTSx_SHIFT)
  129. #define SDIO_DTSx_SET_TYPE_C (2 << SDIO_DRIVE_DTSx_SHIFT)
  130. #define SDIO_DTSx_SET_TYPE_D (3 << SDIO_DRIVE_DTSx_SHIFT)
  131. /*
  132. * Function Basic Registers (FBR)
  133. */
  134. #define SDIO_FBR_BASE(f) ((f) * 0x100) /* base of function f's FBRs */
  135. #define SDIO_FBR_STD_IF 0x00
  136. #define SDIO_FBR_SUPPORTS_CSA 0x40 /* supports Code Storage Area */
  137. #define SDIO_FBR_ENABLE_CSA 0x80 /* enable Code Storage Area */
  138. #define SDIO_FBR_STD_IF_EXT 0x01
  139. #define SDIO_FBR_POWER 0x02
  140. #define SDIO_FBR_POWER_SPS 0x01 /* Supports Power Selection */
  141. #define SDIO_FBR_POWER_EPS 0x02 /* Enable (low) Power Selection */
  142. #define SDIO_FBR_CIS 0x09 /* CIS pointer (3 bytes) */
  143. #define SDIO_FBR_CSA 0x0C /* CSA pointer (3 bytes) */
  144. #define SDIO_FBR_CSA_DATA 0x0F
  145. #define SDIO_FBR_BLKSIZE 0x10 /* block size (2 bytes) */
  146. #endif /* LINUX_MMC_SDIO_H */