mmc.h 17 KB

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  1. /*
  2. * Header for MultiMediaCard (MMC)
  3. *
  4. * Copyright 2002 Hewlett-Packard Company
  5. *
  6. * Use consistent with the GNU GPL is permitted,
  7. * provided that this copyright notice is
  8. * preserved in its entirety in all copies and derived works.
  9. *
  10. * HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
  11. * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
  12. * FITNESS FOR ANY PARTICULAR PURPOSE.
  13. *
  14. * Many thanks to Alessandro Rubini and Jonathan Corbet!
  15. *
  16. * Based strongly on code by:
  17. *
  18. * Author: Yong-iL Joh <tolkien@mizi.com>
  19. *
  20. * Author: Andrew Christian
  21. * 15 May 2002
  22. */
  23. #ifndef LINUX_MMC_MMC_H
  24. #define LINUX_MMC_MMC_H
  25. #include <linux/types.h>
  26. /* Standard MMC commands (4.1) type argument response */
  27. /* class 1 */
  28. #define MMC_GO_IDLE_STATE 0 /* bc */
  29. #define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
  30. #define MMC_ALL_SEND_CID 2 /* bcr R2 */
  31. #define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
  32. #define MMC_SET_DSR 4 /* bc [31:16] RCA */
  33. #define MMC_SLEEP_AWAKE 5 /* ac [31:16] RCA 15:flg R1b */
  34. #define MMC_SWITCH 6 /* ac [31:0] See below R1b */
  35. #define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */
  36. #define MMC_SEND_EXT_CSD 8 /* adtc R1 */
  37. #define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */
  38. #define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */
  39. #define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
  40. #define MMC_STOP_TRANSMISSION 12 /* ac R1b */
  41. #define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
  42. #define MMC_BUS_TEST_R 14 /* adtc R1 */
  43. #define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
  44. #define MMC_BUS_TEST_W 19 /* adtc R1 */
  45. #define MMC_SPI_READ_OCR 58 /* spi spi_R3 */
  46. #define MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */
  47. /* class 2 */
  48. #define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
  49. #define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
  50. #define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
  51. #define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */
  52. #define MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */
  53. /* class 3 */
  54. #define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
  55. /* class 4 */
  56. #define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
  57. #define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
  58. #define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
  59. #define MMC_PROGRAM_CID 26 /* adtc R1 */
  60. #define MMC_PROGRAM_CSD 27 /* adtc R1 */
  61. /* class 6 */
  62. #define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
  63. #define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
  64. #define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
  65. /* class 5 */
  66. #define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
  67. #define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
  68. #define MMC_ERASE 38 /* ac R1b */
  69. /* class 9 */
  70. #define MMC_FAST_IO 39 /* ac <Complex> R4 */
  71. #define MMC_GO_IRQ_STATE 40 /* bcr R5 */
  72. /* class 7 */
  73. #define MMC_LOCK_UNLOCK 42 /* adtc R1b */
  74. /* class 8 */
  75. #define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
  76. #define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */
  77. /* class 11 */
  78. #define MMC_QUE_TASK_PARAMS 44 /* ac [20:16] task id R1 */
  79. #define MMC_QUE_TASK_ADDR 45 /* ac [31:0] data addr R1 */
  80. #define MMC_EXECUTE_READ_TASK 46 /* adtc [20:16] task id R1 */
  81. #define MMC_EXECUTE_WRITE_TASK 47 /* adtc [20:16] task id R1 */
  82. #define MMC_CMDQ_TASK_MGMT 48 /* ac [20:16] task id R1b */
  83. static inline bool mmc_op_multi(u32 opcode)
  84. {
  85. return opcode == MMC_WRITE_MULTIPLE_BLOCK ||
  86. opcode == MMC_READ_MULTIPLE_BLOCK;
  87. }
  88. /*
  89. * MMC_SWITCH argument format:
  90. *
  91. * [31:26] Always 0
  92. * [25:24] Access Mode
  93. * [23:16] Location of target Byte in EXT_CSD
  94. * [15:08] Value Byte
  95. * [07:03] Always 0
  96. * [02:00] Command Set
  97. */
  98. /*
  99. MMC status in R1, for native mode (SPI bits are different)
  100. Type
  101. e : error bit
  102. s : status bit
  103. r : detected and set for the actual command response
  104. x : detected and set during command execution. the host must poll
  105. the card by sending status command in order to read these bits.
  106. Clear condition
  107. a : according to the card state
  108. b : always related to the previous command. Reception of
  109. a valid command will clear it (with a delay of one command)
  110. c : clear by read
  111. */
  112. #define R1_OUT_OF_RANGE (1 << 31) /* er, c */
  113. #define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
  114. #define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
  115. #define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
  116. #define R1_ERASE_PARAM (1 << 27) /* ex, c */
  117. #define R1_WP_VIOLATION (1 << 26) /* erx, c */
  118. #define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
  119. #define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
  120. #define R1_COM_CRC_ERROR (1 << 23) /* er, b */
  121. #define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
  122. #define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
  123. #define R1_CC_ERROR (1 << 20) /* erx, c */
  124. #define R1_ERROR (1 << 19) /* erx, c */
  125. #define R1_UNDERRUN (1 << 18) /* ex, c */
  126. #define R1_OVERRUN (1 << 17) /* ex, c */
  127. #define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
  128. #define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
  129. #define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
  130. #define R1_ERASE_RESET (1 << 13) /* sr, c */
  131. #define R1_STATUS(x) (x & 0xFFF9A000)
  132. #define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
  133. #define R1_READY_FOR_DATA (1 << 8) /* sx, a */
  134. #define R1_SWITCH_ERROR (1 << 7) /* sx, c */
  135. #define R1_EXCEPTION_EVENT (1 << 6) /* sr, a */
  136. #define R1_APP_CMD (1 << 5) /* sr, c */
  137. #define R1_STATE_IDLE 0
  138. #define R1_STATE_READY 1
  139. #define R1_STATE_IDENT 2
  140. #define R1_STATE_STBY 3
  141. #define R1_STATE_TRAN 4
  142. #define R1_STATE_DATA 5
  143. #define R1_STATE_RCV 6
  144. #define R1_STATE_PRG 7
  145. #define R1_STATE_DIS 8
  146. static inline bool mmc_ready_for_data(u32 status)
  147. {
  148. /*
  149. * Some cards mishandle the status bits, so make sure to check both the
  150. * busy indication and the card state.
  151. */
  152. return status & R1_READY_FOR_DATA &&
  153. R1_CURRENT_STATE(status) == R1_STATE_TRAN;
  154. }
  155. /*
  156. * MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS
  157. * R1 is the low order byte; R2 is the next highest byte, when present.
  158. */
  159. #define R1_SPI_IDLE (1 << 0)
  160. #define R1_SPI_ERASE_RESET (1 << 1)
  161. #define R1_SPI_ILLEGAL_COMMAND (1 << 2)
  162. #define R1_SPI_COM_CRC (1 << 3)
  163. #define R1_SPI_ERASE_SEQ (1 << 4)
  164. #define R1_SPI_ADDRESS (1 << 5)
  165. #define R1_SPI_PARAMETER (1 << 6)
  166. /* R1 bit 7 is always zero */
  167. #define R2_SPI_CARD_LOCKED (1 << 8)
  168. #define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */
  169. #define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
  170. #define R2_SPI_ERROR (1 << 10)
  171. #define R2_SPI_CC_ERROR (1 << 11)
  172. #define R2_SPI_CARD_ECC_ERROR (1 << 12)
  173. #define R2_SPI_WP_VIOLATION (1 << 13)
  174. #define R2_SPI_ERASE_PARAM (1 << 14)
  175. #define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */
  176. #define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
  177. /*
  178. * OCR bits are mostly in host.h
  179. */
  180. #define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */
  181. /*
  182. * Card Command Classes (CCC)
  183. */
  184. #define CCC_BASIC (1<<0) /* (0) Basic protocol functions */
  185. /* (CMD0,1,2,3,4,7,9,10,12,13,15) */
  186. /* (and for SPI, CMD58,59) */
  187. #define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */
  188. /* (CMD11) */
  189. #define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */
  190. /* (CMD16,17,18) */
  191. #define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */
  192. /* (CMD20) */
  193. #define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */
  194. /* (CMD16,24,25,26,27) */
  195. #define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */
  196. /* (CMD32,33,34,35,36,37,38,39) */
  197. #define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */
  198. /* (CMD28,29,30) */
  199. #define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */
  200. /* (CMD16,CMD42) */
  201. #define CCC_APP_SPEC (1<<8) /* (8) Application specific */
  202. /* (CMD55,56,57,ACMD*) */
  203. #define CCC_IO_MODE (1<<9) /* (9) I/O mode */
  204. /* (CMD5,39,40,52,53) */
  205. #define CCC_SWITCH (1<<10) /* (10) High speed switch */
  206. /* (CMD6,34,35,36,37,50) */
  207. /* (11) Reserved */
  208. /* (CMD?) */
  209. /*
  210. * CSD field definitions
  211. */
  212. #define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */
  213. #define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */
  214. #define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1 */
  215. #define CSD_STRUCT_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */
  216. #define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */
  217. #define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */
  218. #define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */
  219. #define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 - 3.2 - 3.31 */
  220. #define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 - 4.1 */
  221. /*
  222. * EXT_CSD fields
  223. */
  224. #define EXT_CSD_CMDQ_MODE_EN 15 /* R/W */
  225. #define EXT_CSD_FLUSH_CACHE 32 /* W */
  226. #define EXT_CSD_CACHE_CTRL 33 /* R/W */
  227. #define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */
  228. #define EXT_CSD_PACKED_FAILURE_INDEX 35 /* RO */
  229. #define EXT_CSD_PACKED_CMD_STATUS 36 /* RO */
  230. #define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO, 2 bytes */
  231. #define EXT_CSD_EXP_EVENTS_CTRL 56 /* R/W, 2 bytes */
  232. #define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */
  233. #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
  234. #define EXT_CSD_PARTITION_SETTING_COMPLETED 155 /* R/W */
  235. #define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */
  236. #define EXT_CSD_PARTITION_SUPPORT 160 /* RO */
  237. #define EXT_CSD_HPI_MGMT 161 /* R/W */
  238. #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
  239. #define EXT_CSD_BKOPS_EN 163 /* R/W */
  240. #define EXT_CSD_BKOPS_START 164 /* W */
  241. #define EXT_CSD_SANITIZE_START 165 /* W */
  242. #define EXT_CSD_WR_REL_PARAM 166 /* RO */
  243. #define EXT_CSD_RPMB_MULT 168 /* RO */
  244. #define EXT_CSD_FW_CONFIG 169 /* R/W */
  245. #define EXT_CSD_BOOT_WP 173 /* R/W */
  246. #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
  247. #define EXT_CSD_PART_CONFIG 179 /* R/W */
  248. #define EXT_CSD_ERASED_MEM_CONT 181 /* RO */
  249. #define EXT_CSD_BUS_WIDTH 183 /* R/W */
  250. #define EXT_CSD_STROBE_SUPPORT 184 /* RO */
  251. #define EXT_CSD_HS_TIMING 185 /* R/W */
  252. #define EXT_CSD_POWER_CLASS 187 /* R/W */
  253. #define EXT_CSD_REV 192 /* RO */
  254. #define EXT_CSD_STRUCTURE 194 /* RO */
  255. #define EXT_CSD_CARD_TYPE 196 /* RO */
  256. #define EXT_CSD_DRIVER_STRENGTH 197 /* RO */
  257. #define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* RO */
  258. #define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
  259. #define EXT_CSD_PWR_CL_52_195 200 /* RO */
  260. #define EXT_CSD_PWR_CL_26_195 201 /* RO */
  261. #define EXT_CSD_PWR_CL_52_360 202 /* RO */
  262. #define EXT_CSD_PWR_CL_26_360 203 /* RO */
  263. #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
  264. #define EXT_CSD_S_A_TIMEOUT 217 /* RO */
  265. #define EXT_CSD_REL_WR_SEC_C 222 /* RO */
  266. #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
  267. #define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */
  268. #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
  269. #define EXT_CSD_BOOT_MULT 226 /* RO */
  270. #define EXT_CSD_SEC_TRIM_MULT 229 /* RO */
  271. #define EXT_CSD_SEC_ERASE_MULT 230 /* RO */
  272. #define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
  273. #define EXT_CSD_TRIM_MULT 232 /* RO */
  274. #define EXT_CSD_PWR_CL_200_195 236 /* RO */
  275. #define EXT_CSD_PWR_CL_200_360 237 /* RO */
  276. #define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */
  277. #define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */
  278. #define EXT_CSD_BKOPS_STATUS 246 /* RO */
  279. #define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */
  280. #define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
  281. #define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */
  282. #define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */
  283. #define EXT_CSD_FIRMWARE_VERSION 254 /* RO, 8 bytes */
  284. #define EXT_CSD_PRE_EOL_INFO 267 /* RO */
  285. #define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A 268 /* RO */
  286. #define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B 269 /* RO */
  287. #define EXT_CSD_CMDQ_DEPTH 307 /* RO */
  288. #define EXT_CSD_CMDQ_SUPPORT 308 /* RO */
  289. #define EXT_CSD_SUPPORTED_MODE 493 /* RO */
  290. #define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */
  291. #define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */
  292. #define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */
  293. #define EXT_CSD_MAX_PACKED_READS 501 /* RO */
  294. #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
  295. #define EXT_CSD_HPI_FEATURES 503 /* RO */
  296. /*
  297. * EXT_CSD field definitions
  298. */
  299. #define EXT_CSD_WR_REL_PARAM_EN (1<<2)
  300. #define EXT_CSD_WR_REL_PARAM_EN_RPMB_REL_WR (1<<4)
  301. #define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40)
  302. #define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10)
  303. #define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04)
  304. #define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01)
  305. #define EXT_CSD_PART_CONFIG_ACC_MASK (0x7)
  306. #define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1)
  307. #define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3)
  308. #define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4)
  309. #define EXT_CSD_PART_SETTING_COMPLETED (0x1)
  310. #define EXT_CSD_PART_SUPPORT_PART_EN (0x1)
  311. #define EXT_CSD_CMD_SET_NORMAL (1<<0)
  312. #define EXT_CSD_CMD_SET_SECURE (1<<1)
  313. #define EXT_CSD_CMD_SET_CPSECURE (1<<2)
  314. #define EXT_CSD_CARD_TYPE_HS_26 (1<<0) /* Card can run at 26MHz */
  315. #define EXT_CSD_CARD_TYPE_HS_52 (1<<1) /* Card can run at 52MHz */
  316. #define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_HS_26 | \
  317. EXT_CSD_CARD_TYPE_HS_52)
  318. #define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */
  319. /* DDR mode @1.8V or 3V I/O */
  320. #define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */
  321. /* DDR mode @1.2V I/O */
  322. #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
  323. | EXT_CSD_CARD_TYPE_DDR_1_2V)
  324. #define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */
  325. #define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz */
  326. /* SDR mode @1.2V I/O */
  327. #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
  328. EXT_CSD_CARD_TYPE_HS200_1_2V)
  329. #define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz DDR, 1.8V */
  330. #define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */
  331. #define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
  332. EXT_CSD_CARD_TYPE_HS400_1_2V)
  333. #define EXT_CSD_CARD_TYPE_HS400ES (1<<8) /* Card can run at HS400ES */
  334. #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
  335. #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
  336. #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
  337. #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
  338. #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
  339. #define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */
  340. #define EXT_CSD_TIMING_BC 0 /* Backwards compatility */
  341. #define EXT_CSD_TIMING_HS 1 /* High speed */
  342. #define EXT_CSD_TIMING_HS200 2 /* HS200 */
  343. #define EXT_CSD_TIMING_HS400 3 /* HS400 */
  344. #define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */
  345. #define EXT_CSD_SEC_ER_EN BIT(0)
  346. #define EXT_CSD_SEC_BD_BLK_EN BIT(2)
  347. #define EXT_CSD_SEC_GB_CL_EN BIT(4)
  348. #define EXT_CSD_SEC_SANITIZE BIT(6) /* v4.5 only */
  349. #define EXT_CSD_RST_N_EN_MASK 0x3
  350. #define EXT_CSD_RST_N_ENABLED 1 /* RST_n is enabled on card */
  351. #define EXT_CSD_NO_POWER_NOTIFICATION 0
  352. #define EXT_CSD_POWER_ON 1
  353. #define EXT_CSD_POWER_OFF_SHORT 2
  354. #define EXT_CSD_POWER_OFF_LONG 3
  355. #define EXT_CSD_PWR_CL_8BIT_MASK 0xF0 /* 8 bit PWR CLS */
  356. #define EXT_CSD_PWR_CL_4BIT_MASK 0x0F /* 8 bit PWR CLS */
  357. #define EXT_CSD_PWR_CL_8BIT_SHIFT 4
  358. #define EXT_CSD_PWR_CL_4BIT_SHIFT 0
  359. #define EXT_CSD_PACKED_EVENT_EN BIT(3)
  360. /*
  361. * EXCEPTION_EVENT_STATUS field
  362. */
  363. #define EXT_CSD_URGENT_BKOPS BIT(0)
  364. #define EXT_CSD_DYNCAP_NEEDED BIT(1)
  365. #define EXT_CSD_SYSPOOL_EXHAUSTED BIT(2)
  366. #define EXT_CSD_PACKED_FAILURE BIT(3)
  367. #define EXT_CSD_PACKED_GENERIC_ERROR BIT(0)
  368. #define EXT_CSD_PACKED_INDEXED_ERROR BIT(1)
  369. /*
  370. * BKOPS status level
  371. */
  372. #define EXT_CSD_BKOPS_LEVEL_2 0x2
  373. /*
  374. * BKOPS modes
  375. */
  376. #define EXT_CSD_MANUAL_BKOPS_MASK 0x01
  377. #define EXT_CSD_AUTO_BKOPS_MASK 0x02
  378. /*
  379. * Command Queue
  380. */
  381. #define EXT_CSD_CMDQ_MODE_ENABLED BIT(0)
  382. #define EXT_CSD_CMDQ_DEPTH_MASK GENMASK(4, 0)
  383. #define EXT_CSD_CMDQ_SUPPORTED BIT(0)
  384. /*
  385. * MMC_SWITCH access modes
  386. */
  387. #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
  388. #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */
  389. #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */
  390. #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
  391. /*
  392. * Erase/trim/discard
  393. */
  394. #define MMC_ERASE_ARG 0x00000000
  395. #define MMC_SECURE_ERASE_ARG 0x80000000
  396. #define MMC_TRIM_ARG 0x00000001
  397. #define MMC_DISCARD_ARG 0x00000003
  398. #define MMC_SECURE_TRIM1_ARG 0x80000001
  399. #define MMC_SECURE_TRIM2_ARG 0x80008000
  400. #define MMC_SECURE_ARGS 0x80000000
  401. #define MMC_TRIM_ARGS 0x00008001
  402. #define mmc_driver_type_mask(n) (1 << (n))
  403. struct mmc_card;
  404. extern int mmc_select_bus_width(struct mmc_card *card);
  405. extern int mmc_select_hs(struct mmc_card *card);
  406. extern int mmc_select_hs_ddr(struct mmc_card *card);
  407. extern int mmc_select_hs400(struct mmc_card *card);
  408. extern int mmc_hs200_tuning(struct mmc_card *card);
  409. extern int mmc_select_timing(struct mmc_card *card);
  410. #endif /* LINUX_MMC_MMC_H */