device.h 42 KB

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  1. /*
  2. * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #ifndef MLX4_DEVICE_H
  33. #define MLX4_DEVICE_H
  34. #include <linux/if_ether.h>
  35. #include <linux/pci.h>
  36. #include <linux/completion.h>
  37. #include <linux/radix-tree.h>
  38. #include <linux/cpu_rmap.h>
  39. #include <linux/crash_dump.h>
  40. #include <linux/refcount.h>
  41. #include <linux/timecounter.h>
  42. #define DEFAULT_UAR_PAGE_SHIFT 12
  43. #define MAX_MSIX_P_PORT 17
  44. #define MAX_MSIX 128
  45. #define MIN_MSIX_P_PORT 5
  46. #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \
  47. (dev_cap).num_ports * MIN_MSIX_P_PORT)
  48. #define MLX4_MAX_100M_UNITS_VAL 255 /*
  49. * work around: can't set values
  50. * greater then this value when
  51. * using 100 Mbps units.
  52. */
  53. #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
  54. #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
  55. #define MLX4_RATELIMIT_DEFAULT 0x00ff
  56. #define MLX4_ROCE_MAX_GIDS 128
  57. #define MLX4_ROCE_PF_GIDS 16
  58. enum {
  59. MLX4_FLAG_MSI_X = 1 << 0,
  60. MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
  61. MLX4_FLAG_MASTER = 1 << 2,
  62. MLX4_FLAG_SLAVE = 1 << 3,
  63. MLX4_FLAG_SRIOV = 1 << 4,
  64. MLX4_FLAG_OLD_REG_MAC = 1 << 6,
  65. MLX4_FLAG_BONDED = 1 << 7,
  66. MLX4_FLAG_SECURE_HOST = 1 << 8,
  67. };
  68. enum {
  69. MLX4_PORT_CAP_IS_SM = 1 << 1,
  70. MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
  71. };
  72. enum {
  73. MLX4_MAX_PORTS = 2,
  74. MLX4_MAX_PORT_PKEYS = 128,
  75. MLX4_MAX_PORT_GIDS = 128
  76. };
  77. /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
  78. * These qkeys must not be allowed for general use. This is a 64k range,
  79. * and to test for violation, we use the mask (protect against future chg).
  80. */
  81. #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
  82. #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
  83. enum {
  84. MLX4_BOARD_ID_LEN = 64
  85. };
  86. enum {
  87. MLX4_MAX_NUM_PF = 16,
  88. MLX4_MAX_NUM_VF = 126,
  89. MLX4_MAX_NUM_VF_P_PORT = 64,
  90. MLX4_MFUNC_MAX = 128,
  91. MLX4_MAX_EQ_NUM = 1024,
  92. MLX4_MFUNC_EQ_NUM = 4,
  93. MLX4_MFUNC_MAX_EQES = 8,
  94. MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
  95. };
  96. /* Driver supports 3 different device methods to manage traffic steering:
  97. * -device managed - High level API for ib and eth flow steering. FW is
  98. * managing flow steering tables.
  99. * - B0 steering mode - Common low level API for ib and (if supported) eth.
  100. * - A0 steering mode - Limited low level API for eth. In case of IB,
  101. * B0 mode is in use.
  102. */
  103. enum {
  104. MLX4_STEERING_MODE_A0,
  105. MLX4_STEERING_MODE_B0,
  106. MLX4_STEERING_MODE_DEVICE_MANAGED
  107. };
  108. enum {
  109. MLX4_STEERING_DMFS_A0_DEFAULT,
  110. MLX4_STEERING_DMFS_A0_DYNAMIC,
  111. MLX4_STEERING_DMFS_A0_STATIC,
  112. MLX4_STEERING_DMFS_A0_DISABLE,
  113. MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
  114. };
  115. static inline const char *mlx4_steering_mode_str(int steering_mode)
  116. {
  117. switch (steering_mode) {
  118. case MLX4_STEERING_MODE_A0:
  119. return "A0 steering";
  120. case MLX4_STEERING_MODE_B0:
  121. return "B0 steering";
  122. case MLX4_STEERING_MODE_DEVICE_MANAGED:
  123. return "Device managed flow steering";
  124. default:
  125. return "Unrecognize steering mode";
  126. }
  127. }
  128. enum {
  129. MLX4_TUNNEL_OFFLOAD_MODE_NONE,
  130. MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
  131. };
  132. enum {
  133. MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
  134. MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
  135. MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
  136. MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
  137. MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
  138. MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
  139. MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
  140. MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
  141. MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
  142. MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
  143. MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
  144. MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
  145. MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
  146. MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
  147. MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
  148. MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
  149. MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
  150. MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
  151. MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
  152. MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
  153. MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
  154. MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
  155. MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
  156. MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
  157. MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
  158. MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52,
  159. MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
  160. MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
  161. MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
  162. MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
  163. MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
  164. };
  165. enum {
  166. MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
  167. MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
  168. MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
  169. MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
  170. MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
  171. MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
  172. MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
  173. MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
  174. MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
  175. MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
  176. MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
  177. MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11,
  178. MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12,
  179. MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13,
  180. MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14,
  181. MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15,
  182. MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16,
  183. MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17,
  184. MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
  185. MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19,
  186. MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20,
  187. MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21,
  188. MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22,
  189. MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23,
  190. MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24,
  191. MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25,
  192. MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26,
  193. MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27,
  194. MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28,
  195. MLX4_DEV_CAP_FLAG2_PHV_EN = 1LL << 29,
  196. MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30,
  197. MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31,
  198. MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1ULL << 32,
  199. MLX4_DEV_CAP_FLAG2_ROCE_V1_V2 = 1ULL << 33,
  200. MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER = 1ULL << 34,
  201. MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT = 1ULL << 35,
  202. MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP = 1ULL << 36,
  203. MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT = 1ULL << 37,
  204. MLX4_DEV_CAP_FLAG2_USER_MAC_EN = 1ULL << 38,
  205. MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW = 1ULL << 39,
  206. MLX4_DEV_CAP_FLAG2_SW_CQ_INIT = 1ULL << 40,
  207. };
  208. enum {
  209. MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0,
  210. MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1
  211. };
  212. enum {
  213. MLX4_VF_CAP_FLAG_RESET = 1 << 0
  214. };
  215. /* bit enums for an 8-bit flags field indicating special use
  216. * QPs which require special handling in qp_reserve_range.
  217. * Currently, this only includes QPs used by the ETH interface,
  218. * where we expect to use blueflame. These QPs must not have
  219. * bits 6 and 7 set in their qp number.
  220. *
  221. * This enum may use only bits 0..7.
  222. */
  223. enum {
  224. MLX4_RESERVE_A0_QP = 1 << 6,
  225. MLX4_RESERVE_ETH_BF_QP = 1 << 7,
  226. };
  227. enum {
  228. MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
  229. MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1,
  230. MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2,
  231. MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3
  232. };
  233. enum {
  234. MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0,
  235. MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1,
  236. MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2
  237. };
  238. #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
  239. enum {
  240. MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
  241. MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
  242. MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
  243. MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
  244. MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
  245. MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
  246. MLX4_BMME_FLAG_ROCE_V1_V2 = 1 << 19,
  247. MLX4_BMME_FLAG_PORT_REMAP = 1 << 24,
  248. MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28,
  249. };
  250. enum {
  251. MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP,
  252. MLX4_FLAG_ROCE_V1_V2 = MLX4_BMME_FLAG_ROCE_V1_V2
  253. };
  254. enum mlx4_event {
  255. MLX4_EVENT_TYPE_COMP = 0x00,
  256. MLX4_EVENT_TYPE_PATH_MIG = 0x01,
  257. MLX4_EVENT_TYPE_COMM_EST = 0x02,
  258. MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
  259. MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
  260. MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
  261. MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
  262. MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
  263. MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
  264. MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
  265. MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
  266. MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
  267. MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
  268. MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
  269. MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
  270. MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
  271. MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
  272. MLX4_EVENT_TYPE_CMD = 0x0a,
  273. MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
  274. MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
  275. MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
  276. MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
  277. MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
  278. MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
  279. MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e,
  280. MLX4_EVENT_TYPE_NONE = 0xff,
  281. };
  282. enum {
  283. MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
  284. MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
  285. };
  286. enum {
  287. MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1,
  288. MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2,
  289. };
  290. enum {
  291. MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
  292. };
  293. enum slave_port_state {
  294. SLAVE_PORT_DOWN = 0,
  295. SLAVE_PENDING_UP,
  296. SLAVE_PORT_UP,
  297. };
  298. enum slave_port_gen_event {
  299. SLAVE_PORT_GEN_EVENT_DOWN = 0,
  300. SLAVE_PORT_GEN_EVENT_UP,
  301. SLAVE_PORT_GEN_EVENT_NONE,
  302. };
  303. enum slave_port_state_event {
  304. MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
  305. MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
  306. MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
  307. MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
  308. };
  309. enum {
  310. MLX4_PERM_LOCAL_READ = 1 << 10,
  311. MLX4_PERM_LOCAL_WRITE = 1 << 11,
  312. MLX4_PERM_REMOTE_READ = 1 << 12,
  313. MLX4_PERM_REMOTE_WRITE = 1 << 13,
  314. MLX4_PERM_ATOMIC = 1 << 14,
  315. MLX4_PERM_BIND_MW = 1 << 15,
  316. MLX4_PERM_MASK = 0xFC00
  317. };
  318. enum {
  319. MLX4_OPCODE_NOP = 0x00,
  320. MLX4_OPCODE_SEND_INVAL = 0x01,
  321. MLX4_OPCODE_RDMA_WRITE = 0x08,
  322. MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
  323. MLX4_OPCODE_SEND = 0x0a,
  324. MLX4_OPCODE_SEND_IMM = 0x0b,
  325. MLX4_OPCODE_LSO = 0x0e,
  326. MLX4_OPCODE_RDMA_READ = 0x10,
  327. MLX4_OPCODE_ATOMIC_CS = 0x11,
  328. MLX4_OPCODE_ATOMIC_FA = 0x12,
  329. MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
  330. MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
  331. MLX4_OPCODE_BIND_MW = 0x18,
  332. MLX4_OPCODE_FMR = 0x19,
  333. MLX4_OPCODE_LOCAL_INVAL = 0x1b,
  334. MLX4_OPCODE_CONFIG_CMD = 0x1f,
  335. MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
  336. MLX4_RECV_OPCODE_SEND = 0x01,
  337. MLX4_RECV_OPCODE_SEND_IMM = 0x02,
  338. MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
  339. MLX4_CQE_OPCODE_ERROR = 0x1e,
  340. MLX4_CQE_OPCODE_RESIZE = 0x16,
  341. };
  342. enum {
  343. MLX4_STAT_RATE_OFFSET = 5
  344. };
  345. enum mlx4_protocol {
  346. MLX4_PROT_IB_IPV6 = 0,
  347. MLX4_PROT_ETH,
  348. MLX4_PROT_IB_IPV4,
  349. MLX4_PROT_FCOE
  350. };
  351. enum {
  352. MLX4_MTT_FLAG_PRESENT = 1
  353. };
  354. enum mlx4_qp_region {
  355. MLX4_QP_REGION_FW = 0,
  356. MLX4_QP_REGION_RSS_RAW_ETH,
  357. MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH,
  358. MLX4_QP_REGION_ETH_ADDR,
  359. MLX4_QP_REGION_FC_ADDR,
  360. MLX4_QP_REGION_FC_EXCH,
  361. MLX4_NUM_QP_REGION
  362. };
  363. enum mlx4_port_type {
  364. MLX4_PORT_TYPE_NONE = 0,
  365. MLX4_PORT_TYPE_IB = 1,
  366. MLX4_PORT_TYPE_ETH = 2,
  367. MLX4_PORT_TYPE_AUTO = 3
  368. };
  369. enum mlx4_special_vlan_idx {
  370. MLX4_NO_VLAN_IDX = 0,
  371. MLX4_VLAN_MISS_IDX,
  372. MLX4_VLAN_REGULAR
  373. };
  374. enum mlx4_steer_type {
  375. MLX4_MC_STEER = 0,
  376. MLX4_UC_STEER,
  377. MLX4_NUM_STEERS
  378. };
  379. enum mlx4_resource_usage {
  380. MLX4_RES_USAGE_NONE,
  381. MLX4_RES_USAGE_DRIVER,
  382. MLX4_RES_USAGE_USER_VERBS,
  383. };
  384. enum {
  385. MLX4_NUM_FEXCH = 64 * 1024,
  386. };
  387. enum {
  388. MLX4_MAX_FAST_REG_PAGES = 511,
  389. };
  390. enum {
  391. /*
  392. * Max wqe size for rdma read is 512 bytes, so this
  393. * limits our max_sge_rd as the wqe needs to fit:
  394. * - ctrl segment (16 bytes)
  395. * - rdma segment (16 bytes)
  396. * - scatter elements (16 bytes each)
  397. */
  398. MLX4_MAX_SGE_RD = (512 - 16 - 16) / 16
  399. };
  400. enum {
  401. MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
  402. MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
  403. MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
  404. MLX4_DEV_PMC_SUBTYPE_SL_TO_VL_MAP = 0x17,
  405. };
  406. /* Port mgmt change event handling */
  407. enum {
  408. MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
  409. MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
  410. MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
  411. MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
  412. MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
  413. };
  414. union sl2vl_tbl_to_u64 {
  415. u8 sl8[8];
  416. u64 sl64;
  417. };
  418. enum {
  419. MLX4_DEVICE_STATE_UP = 1 << 0,
  420. MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1,
  421. };
  422. enum {
  423. MLX4_INTERFACE_STATE_UP = 1 << 0,
  424. MLX4_INTERFACE_STATE_DELETION = 1 << 1,
  425. MLX4_INTERFACE_STATE_NOWAIT = 1 << 2,
  426. };
  427. #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
  428. MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
  429. enum mlx4_module_id {
  430. MLX4_MODULE_ID_SFP = 0x3,
  431. MLX4_MODULE_ID_QSFP = 0xC,
  432. MLX4_MODULE_ID_QSFP_PLUS = 0xD,
  433. MLX4_MODULE_ID_QSFP28 = 0x11,
  434. };
  435. enum { /* rl */
  436. MLX4_QP_RATE_LIMIT_NONE = 0,
  437. MLX4_QP_RATE_LIMIT_KBS = 1,
  438. MLX4_QP_RATE_LIMIT_MBS = 2,
  439. MLX4_QP_RATE_LIMIT_GBS = 3
  440. };
  441. struct mlx4_rate_limit_caps {
  442. u16 num_rates; /* Number of different rates */
  443. u8 min_unit;
  444. u16 min_val;
  445. u8 max_unit;
  446. u16 max_val;
  447. };
  448. static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
  449. {
  450. return (major << 32) | (minor << 16) | subminor;
  451. }
  452. struct mlx4_phys_caps {
  453. u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
  454. u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
  455. u32 num_phys_eqs;
  456. u32 base_sqpn;
  457. u32 base_proxy_sqpn;
  458. u32 base_tunnel_sqpn;
  459. };
  460. struct mlx4_spec_qps {
  461. u32 qp0_qkey;
  462. u32 qp0_proxy;
  463. u32 qp0_tunnel;
  464. u32 qp1_proxy;
  465. u32 qp1_tunnel;
  466. };
  467. struct mlx4_caps {
  468. u64 fw_ver;
  469. u32 function;
  470. int num_ports;
  471. int vl_cap[MLX4_MAX_PORTS + 1];
  472. int ib_mtu_cap[MLX4_MAX_PORTS + 1];
  473. __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
  474. u64 def_mac[MLX4_MAX_PORTS + 1];
  475. int eth_mtu_cap[MLX4_MAX_PORTS + 1];
  476. int gid_table_len[MLX4_MAX_PORTS + 1];
  477. int pkey_table_len[MLX4_MAX_PORTS + 1];
  478. int trans_type[MLX4_MAX_PORTS + 1];
  479. int vendor_oui[MLX4_MAX_PORTS + 1];
  480. int wavelength[MLX4_MAX_PORTS + 1];
  481. u64 trans_code[MLX4_MAX_PORTS + 1];
  482. int local_ca_ack_delay;
  483. int num_uars;
  484. u32 uar_page_size;
  485. int bf_reg_size;
  486. int bf_regs_per_page;
  487. int max_sq_sg;
  488. int max_rq_sg;
  489. int num_qps;
  490. int max_wqes;
  491. int max_sq_desc_sz;
  492. int max_rq_desc_sz;
  493. int max_qp_init_rdma;
  494. int max_qp_dest_rdma;
  495. int max_tc_eth;
  496. struct mlx4_spec_qps *spec_qps;
  497. int num_srqs;
  498. int max_srq_wqes;
  499. int max_srq_sge;
  500. int reserved_srqs;
  501. int num_cqs;
  502. int max_cqes;
  503. int reserved_cqs;
  504. int num_sys_eqs;
  505. int num_eqs;
  506. int reserved_eqs;
  507. int num_comp_vectors;
  508. int num_mpts;
  509. int num_mtts;
  510. int fmr_reserved_mtts;
  511. int reserved_mtts;
  512. int reserved_mrws;
  513. int reserved_uars;
  514. int num_mgms;
  515. int num_amgms;
  516. int reserved_mcgs;
  517. int num_qp_per_mgm;
  518. int steering_mode;
  519. int dmfs_high_steer_mode;
  520. int fs_log_max_ucast_qp_range_size;
  521. int num_pds;
  522. int reserved_pds;
  523. int max_xrcds;
  524. int reserved_xrcds;
  525. int mtt_entry_sz;
  526. u32 max_msg_sz;
  527. u32 page_size_cap;
  528. u64 flags;
  529. u64 flags2;
  530. u32 bmme_flags;
  531. u32 reserved_lkey;
  532. u16 stat_rate_support;
  533. u8 port_width_cap[MLX4_MAX_PORTS + 1];
  534. int max_gso_sz;
  535. int max_rss_tbl_sz;
  536. int reserved_qps_cnt[MLX4_NUM_QP_REGION];
  537. int reserved_qps;
  538. int reserved_qps_base[MLX4_NUM_QP_REGION];
  539. int log_num_macs;
  540. int log_num_vlans;
  541. enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
  542. u8 supported_type[MLX4_MAX_PORTS + 1];
  543. u8 suggested_type[MLX4_MAX_PORTS + 1];
  544. u8 default_sense[MLX4_MAX_PORTS + 1];
  545. u32 port_mask[MLX4_MAX_PORTS + 1];
  546. enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
  547. u32 max_counters;
  548. u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
  549. u16 sqp_demux;
  550. u32 eqe_size;
  551. u32 cqe_size;
  552. u8 eqe_factor;
  553. u32 userspace_caps; /* userspace must be aware of these */
  554. u32 function_caps; /* VFs must be aware of these */
  555. u16 hca_core_clock;
  556. u64 phys_port_id[MLX4_MAX_PORTS + 1];
  557. int tunnel_offload_mode;
  558. u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
  559. u8 phv_bit[MLX4_MAX_PORTS + 1];
  560. u8 alloc_res_qp_mask;
  561. u32 dmfs_high_rate_qpn_base;
  562. u32 dmfs_high_rate_qpn_range;
  563. u32 vf_caps;
  564. bool wol_port[MLX4_MAX_PORTS + 1];
  565. struct mlx4_rate_limit_caps rl_caps;
  566. u32 health_buffer_addrs;
  567. bool map_clock_to_user;
  568. };
  569. struct mlx4_buf_list {
  570. void *buf;
  571. dma_addr_t map;
  572. };
  573. struct mlx4_buf {
  574. struct mlx4_buf_list direct;
  575. struct mlx4_buf_list *page_list;
  576. int nbufs;
  577. int npages;
  578. int page_shift;
  579. };
  580. struct mlx4_mtt {
  581. u32 offset;
  582. int order;
  583. int page_shift;
  584. };
  585. enum {
  586. MLX4_DB_PER_PAGE = PAGE_SIZE / 4
  587. };
  588. struct mlx4_db_pgdir {
  589. struct list_head list;
  590. DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
  591. DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
  592. unsigned long *bits[2];
  593. __be32 *db_page;
  594. dma_addr_t db_dma;
  595. };
  596. struct mlx4_ib_user_db_page;
  597. struct mlx4_db {
  598. __be32 *db;
  599. union {
  600. struct mlx4_db_pgdir *pgdir;
  601. struct mlx4_ib_user_db_page *user_page;
  602. } u;
  603. dma_addr_t dma;
  604. int index;
  605. int order;
  606. };
  607. struct mlx4_hwq_resources {
  608. struct mlx4_db db;
  609. struct mlx4_mtt mtt;
  610. struct mlx4_buf buf;
  611. };
  612. struct mlx4_mr {
  613. struct mlx4_mtt mtt;
  614. u64 iova;
  615. u64 size;
  616. u32 key;
  617. u32 pd;
  618. u32 access;
  619. int enabled;
  620. };
  621. enum mlx4_mw_type {
  622. MLX4_MW_TYPE_1 = 1,
  623. MLX4_MW_TYPE_2 = 2,
  624. };
  625. struct mlx4_mw {
  626. u32 key;
  627. u32 pd;
  628. enum mlx4_mw_type type;
  629. int enabled;
  630. };
  631. struct mlx4_uar {
  632. unsigned long pfn;
  633. int index;
  634. struct list_head bf_list;
  635. unsigned free_bf_bmap;
  636. void __iomem *map;
  637. void __iomem *bf_map;
  638. };
  639. struct mlx4_bf {
  640. unsigned int offset;
  641. int buf_size;
  642. struct mlx4_uar *uar;
  643. void __iomem *reg;
  644. };
  645. struct mlx4_cq {
  646. void (*comp) (struct mlx4_cq *);
  647. void (*event) (struct mlx4_cq *, enum mlx4_event);
  648. struct mlx4_uar *uar;
  649. u32 cons_index;
  650. u16 irq;
  651. __be32 *set_ci_db;
  652. __be32 *arm_db;
  653. int arm_sn;
  654. int cqn;
  655. unsigned vector;
  656. refcount_t refcount;
  657. struct completion free;
  658. struct {
  659. struct list_head list;
  660. void (*comp)(struct mlx4_cq *);
  661. void *priv;
  662. } tasklet_ctx;
  663. int reset_notify_added;
  664. struct list_head reset_notify;
  665. u8 usage;
  666. };
  667. struct mlx4_qp {
  668. void (*event) (struct mlx4_qp *, enum mlx4_event);
  669. int qpn;
  670. refcount_t refcount;
  671. struct completion free;
  672. u8 usage;
  673. };
  674. struct mlx4_srq {
  675. void (*event) (struct mlx4_srq *, enum mlx4_event);
  676. int srqn;
  677. int max;
  678. int max_gs;
  679. int wqe_shift;
  680. refcount_t refcount;
  681. struct completion free;
  682. };
  683. struct mlx4_av {
  684. __be32 port_pd;
  685. u8 reserved1;
  686. u8 g_slid;
  687. __be16 dlid;
  688. u8 reserved2;
  689. u8 gid_index;
  690. u8 stat_rate;
  691. u8 hop_limit;
  692. __be32 sl_tclass_flowlabel;
  693. u8 dgid[16];
  694. };
  695. struct mlx4_eth_av {
  696. __be32 port_pd;
  697. u8 reserved1;
  698. u8 smac_idx;
  699. u16 reserved2;
  700. u8 reserved3;
  701. u8 gid_index;
  702. u8 stat_rate;
  703. u8 hop_limit;
  704. __be32 sl_tclass_flowlabel;
  705. u8 dgid[16];
  706. u8 s_mac[6];
  707. u8 reserved4[2];
  708. __be16 vlan;
  709. u8 mac[ETH_ALEN];
  710. };
  711. union mlx4_ext_av {
  712. struct mlx4_av ib;
  713. struct mlx4_eth_av eth;
  714. };
  715. /* Counters should be saturate once they reach their maximum value */
  716. #define ASSIGN_32BIT_COUNTER(counter, value) do { \
  717. if ((value) > U32_MAX) \
  718. counter = cpu_to_be32(U32_MAX); \
  719. else \
  720. counter = cpu_to_be32(value); \
  721. } while (0)
  722. struct mlx4_counter {
  723. u8 reserved1[3];
  724. u8 counter_mode;
  725. __be32 num_ifc;
  726. u32 reserved2[2];
  727. __be64 rx_frames;
  728. __be64 rx_bytes;
  729. __be64 tx_frames;
  730. __be64 tx_bytes;
  731. };
  732. struct mlx4_quotas {
  733. int qp;
  734. int cq;
  735. int srq;
  736. int mpt;
  737. int mtt;
  738. int counter;
  739. int xrcd;
  740. };
  741. struct mlx4_vf_dev {
  742. u8 min_port;
  743. u8 n_ports;
  744. };
  745. struct mlx4_fw_crdump {
  746. bool snapshot_enable;
  747. struct devlink_region *region_crspace;
  748. struct devlink_region *region_fw_health;
  749. };
  750. enum mlx4_pci_status {
  751. MLX4_PCI_STATUS_DISABLED,
  752. MLX4_PCI_STATUS_ENABLED,
  753. };
  754. struct mlx4_dev_persistent {
  755. struct pci_dev *pdev;
  756. struct mlx4_dev *dev;
  757. int nvfs[MLX4_MAX_PORTS + 1];
  758. int num_vfs;
  759. enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1];
  760. enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1];
  761. struct work_struct catas_work;
  762. struct workqueue_struct *catas_wq;
  763. struct mutex device_state_mutex; /* protect HW state */
  764. u8 state;
  765. struct mutex interface_state_mutex; /* protect SW state */
  766. u8 interface_state;
  767. struct mutex pci_status_mutex; /* sync pci state */
  768. enum mlx4_pci_status pci_status;
  769. struct mlx4_fw_crdump crdump;
  770. };
  771. struct mlx4_dev {
  772. struct mlx4_dev_persistent *persist;
  773. unsigned long flags;
  774. unsigned long num_slaves;
  775. struct mlx4_caps caps;
  776. struct mlx4_phys_caps phys_caps;
  777. struct mlx4_quotas quotas;
  778. struct radix_tree_root qp_table_tree;
  779. u8 rev_id;
  780. u8 port_random_macs;
  781. char board_id[MLX4_BOARD_ID_LEN];
  782. int numa_node;
  783. int oper_log_mgm_entry_size;
  784. u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
  785. u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
  786. struct mlx4_vf_dev *dev_vfs;
  787. u8 uar_page_shift;
  788. };
  789. struct mlx4_clock_params {
  790. u64 offset;
  791. u8 bar;
  792. u8 size;
  793. };
  794. struct mlx4_eqe {
  795. u8 reserved1;
  796. u8 type;
  797. u8 reserved2;
  798. u8 subtype;
  799. union {
  800. u32 raw[6];
  801. struct {
  802. __be32 cqn;
  803. } __packed comp;
  804. struct {
  805. u16 reserved1;
  806. __be16 token;
  807. u32 reserved2;
  808. u8 reserved3[3];
  809. u8 status;
  810. __be64 out_param;
  811. } __packed cmd;
  812. struct {
  813. __be32 qpn;
  814. } __packed qp;
  815. struct {
  816. __be32 srqn;
  817. } __packed srq;
  818. struct {
  819. __be32 cqn;
  820. u32 reserved1;
  821. u8 reserved2[3];
  822. u8 syndrome;
  823. } __packed cq_err;
  824. struct {
  825. u32 reserved1[2];
  826. __be32 port;
  827. } __packed port_change;
  828. struct {
  829. #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
  830. u32 reserved;
  831. u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
  832. } __packed comm_channel_arm;
  833. struct {
  834. u8 port;
  835. u8 reserved[3];
  836. __be64 mac;
  837. } __packed mac_update;
  838. struct {
  839. __be32 slave_id;
  840. } __packed flr_event;
  841. struct {
  842. __be16 current_temperature;
  843. __be16 warning_threshold;
  844. } __packed warming;
  845. struct {
  846. u8 reserved[3];
  847. u8 port;
  848. union {
  849. struct {
  850. __be16 mstr_sm_lid;
  851. __be16 port_lid;
  852. __be32 changed_attr;
  853. u8 reserved[3];
  854. u8 mstr_sm_sl;
  855. __be64 gid_prefix;
  856. } __packed port_info;
  857. struct {
  858. __be32 block_ptr;
  859. __be32 tbl_entries_mask;
  860. } __packed tbl_change_info;
  861. struct {
  862. u8 sl2vl_table[8];
  863. } __packed sl2vl_tbl_change_info;
  864. } params;
  865. } __packed port_mgmt_change;
  866. struct {
  867. u8 reserved[3];
  868. u8 port;
  869. u32 reserved1[5];
  870. } __packed bad_cable;
  871. } event;
  872. u8 slave_id;
  873. u8 reserved3[2];
  874. u8 owner;
  875. } __packed;
  876. struct mlx4_init_port_param {
  877. int set_guid0;
  878. int set_node_guid;
  879. int set_si_guid;
  880. u16 mtu;
  881. int port_width_cap;
  882. u16 vl_cap;
  883. u16 max_gid;
  884. u16 max_pkey;
  885. u64 guid0;
  886. u64 node_guid;
  887. u64 si_guid;
  888. };
  889. #define MAD_IFC_DATA_SZ 192
  890. /* MAD IFC Mailbox */
  891. struct mlx4_mad_ifc {
  892. u8 base_version;
  893. u8 mgmt_class;
  894. u8 class_version;
  895. u8 method;
  896. __be16 status;
  897. __be16 class_specific;
  898. __be64 tid;
  899. __be16 attr_id;
  900. __be16 resv;
  901. __be32 attr_mod;
  902. __be64 mkey;
  903. __be16 dr_slid;
  904. __be16 dr_dlid;
  905. u8 reserved[28];
  906. u8 data[MAD_IFC_DATA_SZ];
  907. } __packed;
  908. #define mlx4_foreach_port(port, dev, type) \
  909. for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
  910. if ((type) == (dev)->caps.port_mask[(port)])
  911. #define mlx4_foreach_ib_transport_port(port, dev) \
  912. for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
  913. if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
  914. ((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_ETH))
  915. #define MLX4_INVALID_SLAVE_ID 0xFF
  916. #define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1)
  917. void handle_port_mgmt_change_event(struct work_struct *work);
  918. static inline int mlx4_master_func_num(struct mlx4_dev *dev)
  919. {
  920. return dev->caps.function;
  921. }
  922. static inline int mlx4_is_master(struct mlx4_dev *dev)
  923. {
  924. return dev->flags & MLX4_FLAG_MASTER;
  925. }
  926. static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
  927. {
  928. return dev->phys_caps.base_sqpn + 8 +
  929. 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
  930. }
  931. static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
  932. {
  933. return (qpn < dev->phys_caps.base_sqpn + 8 +
  934. 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) &&
  935. qpn >= dev->phys_caps.base_sqpn) ||
  936. (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]);
  937. }
  938. static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
  939. {
  940. int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
  941. if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
  942. return 1;
  943. return 0;
  944. }
  945. static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
  946. {
  947. return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
  948. }
  949. static inline int mlx4_is_slave(struct mlx4_dev *dev)
  950. {
  951. return dev->flags & MLX4_FLAG_SLAVE;
  952. }
  953. static inline int mlx4_is_eth(struct mlx4_dev *dev, int port)
  954. {
  955. return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1;
  956. }
  957. int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
  958. struct mlx4_buf *buf);
  959. void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
  960. static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
  961. {
  962. if (buf->nbufs == 1)
  963. return buf->direct.buf + offset;
  964. else
  965. return buf->page_list[offset >> PAGE_SHIFT].buf +
  966. (offset & (PAGE_SIZE - 1));
  967. }
  968. int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
  969. void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
  970. int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
  971. void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
  972. int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
  973. void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
  974. int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
  975. void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
  976. int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
  977. struct mlx4_mtt *mtt);
  978. void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
  979. u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
  980. int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
  981. int npages, int page_shift, struct mlx4_mr *mr);
  982. int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
  983. int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
  984. int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
  985. struct mlx4_mw *mw);
  986. void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
  987. int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
  988. int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
  989. int start_index, int npages, u64 *page_list);
  990. int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
  991. struct mlx4_buf *buf);
  992. int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
  993. void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
  994. int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
  995. int size);
  996. void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
  997. int size);
  998. int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
  999. struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
  1000. unsigned int vector, int collapsed, int timestamp_en,
  1001. void *buf_addr, bool user_cq);
  1002. void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
  1003. int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
  1004. int *base, u8 flags, u8 usage);
  1005. void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
  1006. int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
  1007. void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
  1008. int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
  1009. struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
  1010. void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
  1011. int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
  1012. int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
  1013. int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
  1014. int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
  1015. int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
  1016. int block_mcast_loopback, enum mlx4_protocol prot);
  1017. int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
  1018. enum mlx4_protocol prot);
  1019. int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
  1020. u8 port, int block_mcast_loopback,
  1021. enum mlx4_protocol protocol, u64 *reg_id);
  1022. int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
  1023. enum mlx4_protocol protocol, u64 reg_id);
  1024. enum {
  1025. MLX4_DOMAIN_UVERBS = 0x1000,
  1026. MLX4_DOMAIN_ETHTOOL = 0x2000,
  1027. MLX4_DOMAIN_RFS = 0x3000,
  1028. MLX4_DOMAIN_NIC = 0x5000,
  1029. };
  1030. enum mlx4_net_trans_rule_id {
  1031. MLX4_NET_TRANS_RULE_ID_ETH = 0,
  1032. MLX4_NET_TRANS_RULE_ID_IB,
  1033. MLX4_NET_TRANS_RULE_ID_IPV6,
  1034. MLX4_NET_TRANS_RULE_ID_IPV4,
  1035. MLX4_NET_TRANS_RULE_ID_TCP,
  1036. MLX4_NET_TRANS_RULE_ID_UDP,
  1037. MLX4_NET_TRANS_RULE_ID_VXLAN,
  1038. MLX4_NET_TRANS_RULE_NUM, /* should be last */
  1039. };
  1040. extern const u16 __sw_id_hw[];
  1041. static inline int map_hw_to_sw_id(u16 header_id)
  1042. {
  1043. int i;
  1044. for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
  1045. if (header_id == __sw_id_hw[i])
  1046. return i;
  1047. }
  1048. return -EINVAL;
  1049. }
  1050. enum mlx4_net_trans_promisc_mode {
  1051. MLX4_FS_REGULAR = 1,
  1052. MLX4_FS_ALL_DEFAULT,
  1053. MLX4_FS_MC_DEFAULT,
  1054. MLX4_FS_MIRROR_RX_PORT,
  1055. MLX4_FS_MIRROR_SX_PORT,
  1056. MLX4_FS_UC_SNIFFER,
  1057. MLX4_FS_MC_SNIFFER,
  1058. MLX4_FS_MODE_NUM, /* should be last */
  1059. };
  1060. struct mlx4_spec_eth {
  1061. u8 dst_mac[ETH_ALEN];
  1062. u8 dst_mac_msk[ETH_ALEN];
  1063. u8 src_mac[ETH_ALEN];
  1064. u8 src_mac_msk[ETH_ALEN];
  1065. u8 ether_type_enable;
  1066. __be16 ether_type;
  1067. __be16 vlan_id_msk;
  1068. __be16 vlan_id;
  1069. };
  1070. struct mlx4_spec_tcp_udp {
  1071. __be16 dst_port;
  1072. __be16 dst_port_msk;
  1073. __be16 src_port;
  1074. __be16 src_port_msk;
  1075. };
  1076. struct mlx4_spec_ipv4 {
  1077. __be32 dst_ip;
  1078. __be32 dst_ip_msk;
  1079. __be32 src_ip;
  1080. __be32 src_ip_msk;
  1081. };
  1082. struct mlx4_spec_ib {
  1083. __be32 l3_qpn;
  1084. __be32 qpn_msk;
  1085. u8 dst_gid[16];
  1086. u8 dst_gid_msk[16];
  1087. };
  1088. struct mlx4_spec_vxlan {
  1089. __be32 vni;
  1090. __be32 vni_mask;
  1091. };
  1092. struct mlx4_spec_list {
  1093. struct list_head list;
  1094. enum mlx4_net_trans_rule_id id;
  1095. union {
  1096. struct mlx4_spec_eth eth;
  1097. struct mlx4_spec_ib ib;
  1098. struct mlx4_spec_ipv4 ipv4;
  1099. struct mlx4_spec_tcp_udp tcp_udp;
  1100. struct mlx4_spec_vxlan vxlan;
  1101. };
  1102. };
  1103. enum mlx4_net_trans_hw_rule_queue {
  1104. MLX4_NET_TRANS_Q_FIFO,
  1105. MLX4_NET_TRANS_Q_LIFO,
  1106. };
  1107. struct mlx4_net_trans_rule {
  1108. struct list_head list;
  1109. enum mlx4_net_trans_hw_rule_queue queue_mode;
  1110. bool exclusive;
  1111. bool allow_loopback;
  1112. enum mlx4_net_trans_promisc_mode promisc_mode;
  1113. u8 port;
  1114. u16 priority;
  1115. u32 qpn;
  1116. };
  1117. struct mlx4_net_trans_rule_hw_ctrl {
  1118. __be16 prio;
  1119. u8 type;
  1120. u8 flags;
  1121. u8 rsvd1;
  1122. u8 funcid;
  1123. u8 vep;
  1124. u8 port;
  1125. __be32 qpn;
  1126. __be32 rsvd2;
  1127. };
  1128. struct mlx4_net_trans_rule_hw_ib {
  1129. u8 size;
  1130. u8 rsvd1;
  1131. __be16 id;
  1132. u32 rsvd2;
  1133. __be32 l3_qpn;
  1134. __be32 qpn_mask;
  1135. u8 dst_gid[16];
  1136. u8 dst_gid_msk[16];
  1137. } __packed;
  1138. struct mlx4_net_trans_rule_hw_eth {
  1139. u8 size;
  1140. u8 rsvd;
  1141. __be16 id;
  1142. u8 rsvd1[6];
  1143. u8 dst_mac[6];
  1144. u16 rsvd2;
  1145. u8 dst_mac_msk[6];
  1146. u16 rsvd3;
  1147. u8 src_mac[6];
  1148. u16 rsvd4;
  1149. u8 src_mac_msk[6];
  1150. u8 rsvd5;
  1151. u8 ether_type_enable;
  1152. __be16 ether_type;
  1153. __be16 vlan_tag_msk;
  1154. __be16 vlan_tag;
  1155. } __packed;
  1156. struct mlx4_net_trans_rule_hw_tcp_udp {
  1157. u8 size;
  1158. u8 rsvd;
  1159. __be16 id;
  1160. __be16 rsvd1[3];
  1161. __be16 dst_port;
  1162. __be16 rsvd2;
  1163. __be16 dst_port_msk;
  1164. __be16 rsvd3;
  1165. __be16 src_port;
  1166. __be16 rsvd4;
  1167. __be16 src_port_msk;
  1168. } __packed;
  1169. struct mlx4_net_trans_rule_hw_ipv4 {
  1170. u8 size;
  1171. u8 rsvd;
  1172. __be16 id;
  1173. __be32 rsvd1;
  1174. __be32 dst_ip;
  1175. __be32 dst_ip_msk;
  1176. __be32 src_ip;
  1177. __be32 src_ip_msk;
  1178. } __packed;
  1179. struct mlx4_net_trans_rule_hw_vxlan {
  1180. u8 size;
  1181. u8 rsvd;
  1182. __be16 id;
  1183. __be32 rsvd1;
  1184. __be32 vni;
  1185. __be32 vni_mask;
  1186. } __packed;
  1187. struct _rule_hw {
  1188. union {
  1189. struct {
  1190. u8 size;
  1191. u8 rsvd;
  1192. __be16 id;
  1193. };
  1194. struct mlx4_net_trans_rule_hw_eth eth;
  1195. struct mlx4_net_trans_rule_hw_ib ib;
  1196. struct mlx4_net_trans_rule_hw_ipv4 ipv4;
  1197. struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
  1198. struct mlx4_net_trans_rule_hw_vxlan vxlan;
  1199. };
  1200. };
  1201. enum {
  1202. VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
  1203. VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
  1204. VXLAN_STEER_BY_VSID_VNI = 1 << 2,
  1205. VXLAN_STEER_BY_INNER_MAC = 1 << 3,
  1206. VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
  1207. };
  1208. enum {
  1209. MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS = 0x2,
  1210. };
  1211. int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
  1212. enum mlx4_net_trans_promisc_mode mode);
  1213. int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
  1214. enum mlx4_net_trans_promisc_mode mode);
  1215. int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
  1216. int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
  1217. int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
  1218. int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
  1219. int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
  1220. int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
  1221. void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
  1222. int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
  1223. int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
  1224. int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
  1225. u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
  1226. int mlx4_SET_PORT_user_mac(struct mlx4_dev *dev, u8 port, u8 *user_mac);
  1227. int mlx4_SET_PORT_user_mtu(struct mlx4_dev *dev, u8 port, u16 user_mtu);
  1228. int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
  1229. u8 promisc);
  1230. int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time);
  1231. int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port,
  1232. u8 ignore_fcs_value);
  1233. int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
  1234. int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val);
  1235. int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv);
  1236. int mlx4_get_is_vlan_offload_disabled(struct mlx4_dev *dev, u8 port,
  1237. bool *vlan_offload_disabled);
  1238. void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl,
  1239. struct _rule_hw *eth_header);
  1240. int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
  1241. int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
  1242. int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
  1243. void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
  1244. int mlx4_SYNC_TPT(struct mlx4_dev *dev);
  1245. int mlx4_test_interrupt(struct mlx4_dev *dev, int vector);
  1246. int mlx4_test_async(struct mlx4_dev *dev);
  1247. int mlx4_query_diag_counters(struct mlx4_dev *dev, u8 op_modifier,
  1248. const u32 offset[], u32 value[],
  1249. size_t array_len, u8 port);
  1250. u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port);
  1251. bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector);
  1252. struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port);
  1253. int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector);
  1254. void mlx4_release_eq(struct mlx4_dev *dev, int vec);
  1255. int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector);
  1256. int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
  1257. int mlx4_get_phys_port_id(struct mlx4_dev *dev);
  1258. int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
  1259. int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
  1260. int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx, u8 usage);
  1261. void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
  1262. int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port);
  1263. void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry,
  1264. int port);
  1265. __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port);
  1266. void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port);
  1267. int mlx4_flow_attach(struct mlx4_dev *dev,
  1268. struct mlx4_net_trans_rule *rule, u64 *reg_id);
  1269. int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
  1270. int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
  1271. enum mlx4_net_trans_promisc_mode flow_type);
  1272. int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
  1273. enum mlx4_net_trans_rule_id id);
  1274. int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
  1275. int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr,
  1276. int port, int qpn, u16 prio, u64 *reg_id);
  1277. void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
  1278. int i, int val);
  1279. int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
  1280. int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
  1281. int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
  1282. int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
  1283. int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
  1284. int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
  1285. enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
  1286. int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
  1287. void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
  1288. __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
  1289. int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
  1290. int *slave_id);
  1291. int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
  1292. u8 *gid);
  1293. int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
  1294. u32 max_range_qpn);
  1295. u64 mlx4_read_clock(struct mlx4_dev *dev);
  1296. struct mlx4_active_ports {
  1297. DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
  1298. };
  1299. /* Returns a bitmap of the physical ports which are assigned to slave */
  1300. struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
  1301. /* Returns the physical port that represents the virtual port of the slave, */
  1302. /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
  1303. /* mapping is returned. */
  1304. int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
  1305. struct mlx4_slaves_pport {
  1306. DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
  1307. };
  1308. /* Returns a bitmap of all slaves that are assigned to port. */
  1309. struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
  1310. int port);
  1311. /* Returns a bitmap of all slaves that are assigned exactly to all the */
  1312. /* the ports that are set in crit_ports. */
  1313. struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
  1314. struct mlx4_dev *dev,
  1315. const struct mlx4_active_ports *crit_ports);
  1316. /* Returns the slave's virtual port that represents the physical port. */
  1317. int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
  1318. int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
  1319. int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
  1320. int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis);
  1321. int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port);
  1322. int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2);
  1323. int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
  1324. int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
  1325. int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
  1326. int enable);
  1327. struct mlx4_mpt_entry;
  1328. int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
  1329. struct mlx4_mpt_entry ***mpt_entry);
  1330. int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
  1331. struct mlx4_mpt_entry **mpt_entry);
  1332. int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
  1333. u32 pdn);
  1334. int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
  1335. struct mlx4_mpt_entry *mpt_entry,
  1336. u32 access);
  1337. void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
  1338. struct mlx4_mpt_entry **mpt_entry);
  1339. void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr);
  1340. int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
  1341. u64 iova, u64 size, int npages,
  1342. int page_shift, struct mlx4_mpt_entry *mpt_entry);
  1343. int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
  1344. u16 offset, u16 size, u8 *data);
  1345. int mlx4_max_tc(struct mlx4_dev *dev);
  1346. /* Returns true if running in low memory profile (kdump kernel) */
  1347. static inline bool mlx4_low_memory_profile(void)
  1348. {
  1349. return is_kdump_kernel();
  1350. }
  1351. /* ACCESS REG commands */
  1352. enum mlx4_access_reg_method {
  1353. MLX4_ACCESS_REG_QUERY = 0x1,
  1354. MLX4_ACCESS_REG_WRITE = 0x2,
  1355. };
  1356. /* ACCESS PTYS Reg command */
  1357. enum mlx4_ptys_proto {
  1358. MLX4_PTYS_IB = 1<<0,
  1359. MLX4_PTYS_EN = 1<<2,
  1360. };
  1361. enum mlx4_ptys_flags {
  1362. MLX4_PTYS_AN_DISABLE_CAP = 1 << 5,
  1363. MLX4_PTYS_AN_DISABLE_ADMIN = 1 << 6,
  1364. };
  1365. struct mlx4_ptys_reg {
  1366. u8 flags;
  1367. u8 local_port;
  1368. u8 resrvd2;
  1369. u8 proto_mask;
  1370. __be32 resrvd3[2];
  1371. __be32 eth_proto_cap;
  1372. __be16 ib_width_cap;
  1373. __be16 ib_speed_cap;
  1374. __be32 resrvd4;
  1375. __be32 eth_proto_admin;
  1376. __be16 ib_width_admin;
  1377. __be16 ib_speed_admin;
  1378. __be32 resrvd5;
  1379. __be32 eth_proto_oper;
  1380. __be16 ib_width_oper;
  1381. __be16 ib_speed_oper;
  1382. __be32 resrvd6;
  1383. __be32 eth_proto_lp_adv;
  1384. } __packed;
  1385. int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
  1386. enum mlx4_access_reg_method method,
  1387. struct mlx4_ptys_reg *ptys_reg);
  1388. int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
  1389. struct mlx4_clock_params *params);
  1390. static inline int mlx4_to_hw_uar_index(struct mlx4_dev *dev, int index)
  1391. {
  1392. return (index << (PAGE_SHIFT - dev->uar_page_shift));
  1393. }
  1394. static inline int mlx4_get_num_reserved_uar(struct mlx4_dev *dev)
  1395. {
  1396. /* The first 128 UARs are used for EQ doorbells */
  1397. return (128 >> (PAGE_SHIFT - dev->uar_page_shift));
  1398. }
  1399. #endif /* MLX4_DEVICE_H */