arm-gic.h 5.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * include/linux/irqchip/arm-gic.h
  4. *
  5. * Copyright (C) 2002 ARM Limited, All Rights Reserved.
  6. */
  7. #ifndef __LINUX_IRQCHIP_ARM_GIC_H
  8. #define __LINUX_IRQCHIP_ARM_GIC_H
  9. #define GIC_CPU_CTRL 0x00
  10. #define GIC_CPU_PRIMASK 0x04
  11. #define GIC_CPU_BINPOINT 0x08
  12. #define GIC_CPU_INTACK 0x0c
  13. #define GIC_CPU_EOI 0x10
  14. #define GIC_CPU_RUNNINGPRI 0x14
  15. #define GIC_CPU_HIGHPRI 0x18
  16. #define GIC_CPU_ALIAS_BINPOINT 0x1c
  17. #define GIC_CPU_ACTIVEPRIO 0xd0
  18. #define GIC_CPU_IDENT 0xfc
  19. #define GIC_CPU_DEACTIVATE 0x1000
  20. #define GICC_ENABLE 0x1
  21. #define GICC_INT_PRI_THRESHOLD 0xf0
  22. #define GIC_CPU_CTRL_EnableGrp0_SHIFT 0
  23. #define GIC_CPU_CTRL_EnableGrp0 (1 << GIC_CPU_CTRL_EnableGrp0_SHIFT)
  24. #define GIC_CPU_CTRL_EnableGrp1_SHIFT 1
  25. #define GIC_CPU_CTRL_EnableGrp1 (1 << GIC_CPU_CTRL_EnableGrp1_SHIFT)
  26. #define GIC_CPU_CTRL_AckCtl_SHIFT 2
  27. #define GIC_CPU_CTRL_AckCtl (1 << GIC_CPU_CTRL_AckCtl_SHIFT)
  28. #define GIC_CPU_CTRL_FIQEn_SHIFT 3
  29. #define GIC_CPU_CTRL_FIQEn (1 << GIC_CPU_CTRL_FIQEn_SHIFT)
  30. #define GIC_CPU_CTRL_CBPR_SHIFT 4
  31. #define GIC_CPU_CTRL_CBPR (1 << GIC_CPU_CTRL_CBPR_SHIFT)
  32. #define GIC_CPU_CTRL_EOImodeNS_SHIFT 9
  33. #define GIC_CPU_CTRL_EOImodeNS (1 << GIC_CPU_CTRL_EOImodeNS_SHIFT)
  34. #define GICC_IAR_INT_ID_MASK 0x3ff
  35. #define GICC_INT_SPURIOUS 1023
  36. #define GICC_DIS_BYPASS_MASK 0x1e0
  37. #define GIC_DIST_CTRL 0x000
  38. #define GIC_DIST_CTR 0x004
  39. #define GIC_DIST_IIDR 0x008
  40. #define GIC_DIST_IGROUP 0x080
  41. #define GIC_DIST_ENABLE_SET 0x100
  42. #define GIC_DIST_ENABLE_CLEAR 0x180
  43. #define GIC_DIST_PENDING_SET 0x200
  44. #define GIC_DIST_PENDING_CLEAR 0x280
  45. #define GIC_DIST_ACTIVE_SET 0x300
  46. #define GIC_DIST_ACTIVE_CLEAR 0x380
  47. #define GIC_DIST_PRI 0x400
  48. #define GIC_DIST_TARGET 0x800
  49. #define GIC_DIST_CONFIG 0xc00
  50. #define GIC_DIST_SOFTINT 0xf00
  51. #define GIC_DIST_SGI_PENDING_CLEAR 0xf10
  52. #define GIC_DIST_SGI_PENDING_SET 0xf20
  53. #define GICD_ENABLE 0x1
  54. #define GICD_DISABLE 0x0
  55. #define GICD_INT_ACTLOW_LVLTRIG 0x0
  56. #define GICD_INT_EN_CLR_X32 0xffffffff
  57. #define GICD_INT_EN_SET_SGI 0x0000ffff
  58. #define GICD_INT_EN_CLR_PPI 0xffff0000
  59. #define GICD_IIDR_IMPLEMENTER_SHIFT 0
  60. #define GICD_IIDR_IMPLEMENTER_MASK (0xfff << GICD_IIDR_IMPLEMENTER_SHIFT)
  61. #define GICD_IIDR_REVISION_SHIFT 12
  62. #define GICD_IIDR_REVISION_MASK (0xf << GICD_IIDR_REVISION_SHIFT)
  63. #define GICD_IIDR_VARIANT_SHIFT 16
  64. #define GICD_IIDR_VARIANT_MASK (0xf << GICD_IIDR_VARIANT_SHIFT)
  65. #define GICD_IIDR_PRODUCT_ID_SHIFT 24
  66. #define GICD_IIDR_PRODUCT_ID_MASK (0xff << GICD_IIDR_PRODUCT_ID_SHIFT)
  67. #define GICH_HCR 0x0
  68. #define GICH_VTR 0x4
  69. #define GICH_VMCR 0x8
  70. #define GICH_MISR 0x10
  71. #define GICH_EISR0 0x20
  72. #define GICH_EISR1 0x24
  73. #define GICH_ELRSR0 0x30
  74. #define GICH_ELRSR1 0x34
  75. #define GICH_APR 0xf0
  76. #define GICH_LR0 0x100
  77. #define GICH_HCR_EN (1 << 0)
  78. #define GICH_HCR_UIE (1 << 1)
  79. #define GICH_HCR_NPIE (1 << 3)
  80. #define GICH_LR_VIRTUALID (0x3ff << 0)
  81. #define GICH_LR_PHYSID_CPUID_SHIFT (10)
  82. #define GICH_LR_PHYSID_CPUID (0x3ff << GICH_LR_PHYSID_CPUID_SHIFT)
  83. #define GICH_LR_PRIORITY_SHIFT 23
  84. #define GICH_LR_STATE (3 << 28)
  85. #define GICH_LR_PENDING_BIT (1 << 28)
  86. #define GICH_LR_ACTIVE_BIT (1 << 29)
  87. #define GICH_LR_EOI (1 << 19)
  88. #define GICH_LR_GROUP1 (1 << 30)
  89. #define GICH_LR_HW (1 << 31)
  90. #define GICH_VMCR_ENABLE_GRP0_SHIFT 0
  91. #define GICH_VMCR_ENABLE_GRP0_MASK (1 << GICH_VMCR_ENABLE_GRP0_SHIFT)
  92. #define GICH_VMCR_ENABLE_GRP1_SHIFT 1
  93. #define GICH_VMCR_ENABLE_GRP1_MASK (1 << GICH_VMCR_ENABLE_GRP1_SHIFT)
  94. #define GICH_VMCR_ACK_CTL_SHIFT 2
  95. #define GICH_VMCR_ACK_CTL_MASK (1 << GICH_VMCR_ACK_CTL_SHIFT)
  96. #define GICH_VMCR_FIQ_EN_SHIFT 3
  97. #define GICH_VMCR_FIQ_EN_MASK (1 << GICH_VMCR_FIQ_EN_SHIFT)
  98. #define GICH_VMCR_CBPR_SHIFT 4
  99. #define GICH_VMCR_CBPR_MASK (1 << GICH_VMCR_CBPR_SHIFT)
  100. #define GICH_VMCR_EOI_MODE_SHIFT 9
  101. #define GICH_VMCR_EOI_MODE_MASK (1 << GICH_VMCR_EOI_MODE_SHIFT)
  102. #define GICH_VMCR_PRIMASK_SHIFT 27
  103. #define GICH_VMCR_PRIMASK_MASK (0x1f << GICH_VMCR_PRIMASK_SHIFT)
  104. #define GICH_VMCR_BINPOINT_SHIFT 21
  105. #define GICH_VMCR_BINPOINT_MASK (0x7 << GICH_VMCR_BINPOINT_SHIFT)
  106. #define GICH_VMCR_ALIAS_BINPOINT_SHIFT 18
  107. #define GICH_VMCR_ALIAS_BINPOINT_MASK (0x7 << GICH_VMCR_ALIAS_BINPOINT_SHIFT)
  108. #define GICH_MISR_EOI (1 << 0)
  109. #define GICH_MISR_U (1 << 1)
  110. #define GICV_PMR_PRIORITY_SHIFT 3
  111. #define GICV_PMR_PRIORITY_MASK (0x1f << GICV_PMR_PRIORITY_SHIFT)
  112. #ifndef __ASSEMBLY__
  113. #include <linux/irqdomain.h>
  114. struct device_node;
  115. struct gic_chip_data;
  116. void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
  117. int gic_cpu_if_down(unsigned int gic_nr);
  118. void gic_cpu_save(struct gic_chip_data *gic);
  119. void gic_cpu_restore(struct gic_chip_data *gic);
  120. void gic_dist_save(struct gic_chip_data *gic);
  121. void gic_dist_restore(struct gic_chip_data *gic);
  122. /*
  123. * Subdrivers that need some preparatory work can initialize their
  124. * chips and call this to register their GICs.
  125. */
  126. int gic_of_init(struct device_node *node, struct device_node *parent);
  127. /*
  128. * Initialises and registers a non-root or child GIC chip. Memory for
  129. * the gic_chip_data structure is dynamically allocated.
  130. */
  131. int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq);
  132. /*
  133. * Legacy platforms not converted to DT yet must use this to init
  134. * their GIC
  135. */
  136. void gic_init(void __iomem *dist , void __iomem *cpu);
  137. void gic_send_sgi(unsigned int cpu_id, unsigned int irq);
  138. int gic_get_cpu_id(unsigned int cpu);
  139. void gic_migrate_target(unsigned int new_cpu_id);
  140. unsigned long gic_get_sgir_physaddr(void);
  141. #endif /* __ASSEMBLY */
  142. #endif