irq.h 42 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef _LINUX_IRQ_H
  3. #define _LINUX_IRQ_H
  4. /*
  5. * Please do not include this file in generic code. There is currently
  6. * no requirement for any architecture to implement anything held
  7. * within this file.
  8. *
  9. * Thanks. --rmk
  10. */
  11. #include <linux/cache.h>
  12. #include <linux/spinlock.h>
  13. #include <linux/cpumask.h>
  14. #include <linux/irqhandler.h>
  15. #include <linux/irqreturn.h>
  16. #include <linux/irqnr.h>
  17. #include <linux/topology.h>
  18. #include <linux/io.h>
  19. #include <linux/slab.h>
  20. #include <asm/irq.h>
  21. #include <asm/ptrace.h>
  22. #include <asm/irq_regs.h>
  23. struct seq_file;
  24. struct module;
  25. struct msi_msg;
  26. struct irq_affinity_desc;
  27. enum irqchip_irq_state;
  28. /*
  29. * IRQ line status.
  30. *
  31. * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
  32. *
  33. * IRQ_TYPE_NONE - default, unspecified type
  34. * IRQ_TYPE_EDGE_RISING - rising edge triggered
  35. * IRQ_TYPE_EDGE_FALLING - falling edge triggered
  36. * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
  37. * IRQ_TYPE_LEVEL_HIGH - high level triggered
  38. * IRQ_TYPE_LEVEL_LOW - low level triggered
  39. * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
  40. * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
  41. * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
  42. * to setup the HW to a sane default (used
  43. * by irqdomain map() callbacks to synchronize
  44. * the HW state and SW flags for a newly
  45. * allocated descriptor).
  46. *
  47. * IRQ_TYPE_PROBE - Special flag for probing in progress
  48. *
  49. * Bits which can be modified via irq_set/clear/modify_status_flags()
  50. * IRQ_LEVEL - Interrupt is level type. Will be also
  51. * updated in the code when the above trigger
  52. * bits are modified via irq_set_irq_type()
  53. * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
  54. * it from affinity setting
  55. * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
  56. * IRQ_NOREQUEST - Interrupt cannot be requested via
  57. * request_irq()
  58. * IRQ_NOTHREAD - Interrupt cannot be threaded
  59. * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
  60. * request/setup_irq()
  61. * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
  62. * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
  63. * IRQ_NESTED_THREAD - Interrupt nests into another thread
  64. * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
  65. * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
  66. * it from the spurious interrupt detection
  67. * mechanism and from core side polling.
  68. * IRQ_DISABLE_UNLAZY - Disable lazy irq disable
  69. * IRQ_HIDDEN - Don't show up in /proc/interrupts
  70. * IRQ_RAW - Skip tick management and irqtime accounting
  71. */
  72. enum {
  73. IRQ_TYPE_NONE = 0x00000000,
  74. IRQ_TYPE_EDGE_RISING = 0x00000001,
  75. IRQ_TYPE_EDGE_FALLING = 0x00000002,
  76. IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
  77. IRQ_TYPE_LEVEL_HIGH = 0x00000004,
  78. IRQ_TYPE_LEVEL_LOW = 0x00000008,
  79. IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
  80. IRQ_TYPE_SENSE_MASK = 0x0000000f,
  81. IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
  82. IRQ_TYPE_PROBE = 0x00000010,
  83. IRQ_LEVEL = (1 << 8),
  84. IRQ_PER_CPU = (1 << 9),
  85. IRQ_NOPROBE = (1 << 10),
  86. IRQ_NOREQUEST = (1 << 11),
  87. IRQ_NOAUTOEN = (1 << 12),
  88. IRQ_NO_BALANCING = (1 << 13),
  89. IRQ_MOVE_PCNTXT = (1 << 14),
  90. IRQ_NESTED_THREAD = (1 << 15),
  91. IRQ_NOTHREAD = (1 << 16),
  92. IRQ_PER_CPU_DEVID = (1 << 17),
  93. IRQ_IS_POLLED = (1 << 18),
  94. IRQ_DISABLE_UNLAZY = (1 << 19),
  95. IRQ_HIDDEN = (1 << 20),
  96. IRQ_RAW = (1 << 21),
  97. };
  98. #define IRQF_MODIFY_MASK \
  99. (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
  100. IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
  101. IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
  102. IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY | IRQ_HIDDEN)
  103. #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
  104. /*
  105. * Return value for chip->irq_set_affinity()
  106. *
  107. * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity
  108. * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity
  109. * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
  110. * support stacked irqchips, which indicates skipping
  111. * all descendent irqchips.
  112. */
  113. enum {
  114. IRQ_SET_MASK_OK = 0,
  115. IRQ_SET_MASK_OK_NOCOPY,
  116. IRQ_SET_MASK_OK_DONE,
  117. };
  118. struct msi_desc;
  119. struct irq_domain;
  120. /**
  121. * struct irq_common_data - per irq data shared by all irqchips
  122. * @state_use_accessors: status information for irq chip functions.
  123. * Use accessor functions to deal with it
  124. * @node: node index useful for balancing
  125. * @handler_data: per-IRQ data for the irq_chip methods
  126. * @affinity: IRQ affinity on SMP. If this is an IPI
  127. * related irq, then this is the mask of the
  128. * CPUs to which an IPI can be sent.
  129. * @effective_affinity: The effective IRQ affinity on SMP as some irq
  130. * chips do not allow multi CPU destinations.
  131. * A subset of @affinity.
  132. * @msi_desc: MSI descriptor
  133. * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional.
  134. */
  135. struct irq_common_data {
  136. unsigned int __private state_use_accessors;
  137. #ifdef CONFIG_NUMA
  138. unsigned int node;
  139. #endif
  140. void *handler_data;
  141. struct msi_desc *msi_desc;
  142. cpumask_var_t affinity;
  143. #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
  144. cpumask_var_t effective_affinity;
  145. #endif
  146. #ifdef CONFIG_GENERIC_IRQ_IPI
  147. unsigned int ipi_offset;
  148. #endif
  149. };
  150. /**
  151. * struct irq_data - per irq chip data passed down to chip functions
  152. * @mask: precomputed bitmask for accessing the chip registers
  153. * @irq: interrupt number
  154. * @hwirq: hardware interrupt number, local to the interrupt domain
  155. * @common: point to data shared by all irqchips
  156. * @chip: low level interrupt hardware access
  157. * @domain: Interrupt translation domain; responsible for mapping
  158. * between hwirq number and linux irq number.
  159. * @parent_data: pointer to parent struct irq_data to support hierarchy
  160. * irq_domain
  161. * @chip_data: platform-specific per-chip private data for the chip
  162. * methods, to allow shared chip implementations
  163. */
  164. struct irq_data {
  165. u32 mask;
  166. unsigned int irq;
  167. unsigned long hwirq;
  168. struct irq_common_data *common;
  169. struct irq_chip *chip;
  170. struct irq_domain *domain;
  171. #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
  172. struct irq_data *parent_data;
  173. #endif
  174. void *chip_data;
  175. };
  176. /*
  177. * Bit masks for irq_common_data.state_use_accessors
  178. *
  179. * IRQD_TRIGGER_MASK - Mask for the trigger type bits
  180. * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
  181. * IRQD_ACTIVATED - Interrupt has already been activated
  182. * IRQD_NO_BALANCING - Balancing disabled for this IRQ
  183. * IRQD_PER_CPU - Interrupt is per cpu
  184. * IRQD_AFFINITY_SET - Interrupt affinity was set
  185. * IRQD_LEVEL - Interrupt is level triggered
  186. * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
  187. * from suspend
  188. * IRQD_MOVE_PCNTXT - Interrupt can be moved in process
  189. * context
  190. * IRQD_IRQ_DISABLED - Disabled state of the interrupt
  191. * IRQD_IRQ_MASKED - Masked state of the interrupt
  192. * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
  193. * IRQD_WAKEUP_ARMED - Wakeup mode armed
  194. * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU
  195. * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel
  196. * IRQD_IRQ_STARTED - Startup state of the interrupt
  197. * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity
  198. * mask. Applies only to affinity managed irqs.
  199. * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target
  200. * IRQD_DEFAULT_TRIGGER_SET - Expected trigger already been set
  201. * IRQD_CAN_RESERVE - Can use reservation mode
  202. * IRQD_MSI_NOMASK_QUIRK - Non-maskable MSI quirk for affinity change
  203. * required
  204. * IRQD_HANDLE_ENFORCE_IRQCTX - Enforce that handle_irq_*() is only invoked
  205. * from actual interrupt context.
  206. * IRQD_AFFINITY_ON_ACTIVATE - Affinity is set on activation. Don't call
  207. * irq_chip::irq_set_affinity() when deactivated.
  208. * IRQD_IRQ_ENABLED_ON_SUSPEND - Interrupt is enabled on suspend by irq pm if
  209. * irqchip have flag IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND set.
  210. */
  211. enum {
  212. IRQD_TRIGGER_MASK = 0xf,
  213. IRQD_SETAFFINITY_PENDING = (1 << 8),
  214. IRQD_ACTIVATED = (1 << 9),
  215. IRQD_NO_BALANCING = (1 << 10),
  216. IRQD_PER_CPU = (1 << 11),
  217. IRQD_AFFINITY_SET = (1 << 12),
  218. IRQD_LEVEL = (1 << 13),
  219. IRQD_WAKEUP_STATE = (1 << 14),
  220. IRQD_MOVE_PCNTXT = (1 << 15),
  221. IRQD_IRQ_DISABLED = (1 << 16),
  222. IRQD_IRQ_MASKED = (1 << 17),
  223. IRQD_IRQ_INPROGRESS = (1 << 18),
  224. IRQD_WAKEUP_ARMED = (1 << 19),
  225. IRQD_FORWARDED_TO_VCPU = (1 << 20),
  226. IRQD_AFFINITY_MANAGED = (1 << 21),
  227. IRQD_IRQ_STARTED = (1 << 22),
  228. IRQD_MANAGED_SHUTDOWN = (1 << 23),
  229. IRQD_SINGLE_TARGET = (1 << 24),
  230. IRQD_DEFAULT_TRIGGER_SET = (1 << 25),
  231. IRQD_CAN_RESERVE = (1 << 26),
  232. IRQD_MSI_NOMASK_QUIRK = (1 << 27),
  233. IRQD_HANDLE_ENFORCE_IRQCTX = (1 << 28),
  234. IRQD_AFFINITY_ON_ACTIVATE = (1 << 29),
  235. IRQD_IRQ_ENABLED_ON_SUSPEND = (1 << 30),
  236. };
  237. #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
  238. static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
  239. {
  240. return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING;
  241. }
  242. static inline bool irqd_is_per_cpu(struct irq_data *d)
  243. {
  244. return __irqd_to_state(d) & IRQD_PER_CPU;
  245. }
  246. static inline bool irqd_can_balance(struct irq_data *d)
  247. {
  248. return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING));
  249. }
  250. static inline bool irqd_affinity_was_set(struct irq_data *d)
  251. {
  252. return __irqd_to_state(d) & IRQD_AFFINITY_SET;
  253. }
  254. static inline void irqd_mark_affinity_was_set(struct irq_data *d)
  255. {
  256. __irqd_to_state(d) |= IRQD_AFFINITY_SET;
  257. }
  258. static inline bool irqd_trigger_type_was_set(struct irq_data *d)
  259. {
  260. return __irqd_to_state(d) & IRQD_DEFAULT_TRIGGER_SET;
  261. }
  262. static inline u32 irqd_get_trigger_type(struct irq_data *d)
  263. {
  264. return __irqd_to_state(d) & IRQD_TRIGGER_MASK;
  265. }
  266. /*
  267. * Must only be called inside irq_chip.irq_set_type() functions or
  268. * from the DT/ACPI setup code.
  269. */
  270. static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
  271. {
  272. __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK;
  273. __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK;
  274. __irqd_to_state(d) |= IRQD_DEFAULT_TRIGGER_SET;
  275. }
  276. static inline bool irqd_is_level_type(struct irq_data *d)
  277. {
  278. return __irqd_to_state(d) & IRQD_LEVEL;
  279. }
  280. /*
  281. * Must only be called of irqchip.irq_set_affinity() or low level
  282. * hieararchy domain allocation functions.
  283. */
  284. static inline void irqd_set_single_target(struct irq_data *d)
  285. {
  286. __irqd_to_state(d) |= IRQD_SINGLE_TARGET;
  287. }
  288. static inline bool irqd_is_single_target(struct irq_data *d)
  289. {
  290. return __irqd_to_state(d) & IRQD_SINGLE_TARGET;
  291. }
  292. static inline void irqd_set_handle_enforce_irqctx(struct irq_data *d)
  293. {
  294. __irqd_to_state(d) |= IRQD_HANDLE_ENFORCE_IRQCTX;
  295. }
  296. static inline bool irqd_is_handle_enforce_irqctx(struct irq_data *d)
  297. {
  298. return __irqd_to_state(d) & IRQD_HANDLE_ENFORCE_IRQCTX;
  299. }
  300. static inline bool irqd_is_enabled_on_suspend(struct irq_data *d)
  301. {
  302. return __irqd_to_state(d) & IRQD_IRQ_ENABLED_ON_SUSPEND;
  303. }
  304. static inline bool irqd_is_wakeup_set(struct irq_data *d)
  305. {
  306. return __irqd_to_state(d) & IRQD_WAKEUP_STATE;
  307. }
  308. static inline bool irqd_can_move_in_process_context(struct irq_data *d)
  309. {
  310. return __irqd_to_state(d) & IRQD_MOVE_PCNTXT;
  311. }
  312. static inline bool irqd_irq_disabled(struct irq_data *d)
  313. {
  314. return __irqd_to_state(d) & IRQD_IRQ_DISABLED;
  315. }
  316. static inline bool irqd_irq_masked(struct irq_data *d)
  317. {
  318. return __irqd_to_state(d) & IRQD_IRQ_MASKED;
  319. }
  320. static inline bool irqd_irq_inprogress(struct irq_data *d)
  321. {
  322. return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS;
  323. }
  324. static inline bool irqd_is_wakeup_armed(struct irq_data *d)
  325. {
  326. return __irqd_to_state(d) & IRQD_WAKEUP_ARMED;
  327. }
  328. static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d)
  329. {
  330. return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU;
  331. }
  332. static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d)
  333. {
  334. __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU;
  335. }
  336. static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d)
  337. {
  338. __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU;
  339. }
  340. static inline bool irqd_affinity_is_managed(struct irq_data *d)
  341. {
  342. return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED;
  343. }
  344. static inline bool irqd_is_activated(struct irq_data *d)
  345. {
  346. return __irqd_to_state(d) & IRQD_ACTIVATED;
  347. }
  348. static inline void irqd_set_activated(struct irq_data *d)
  349. {
  350. __irqd_to_state(d) |= IRQD_ACTIVATED;
  351. }
  352. static inline void irqd_clr_activated(struct irq_data *d)
  353. {
  354. __irqd_to_state(d) &= ~IRQD_ACTIVATED;
  355. }
  356. static inline bool irqd_is_started(struct irq_data *d)
  357. {
  358. return __irqd_to_state(d) & IRQD_IRQ_STARTED;
  359. }
  360. static inline bool irqd_is_managed_and_shutdown(struct irq_data *d)
  361. {
  362. return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN;
  363. }
  364. static inline void irqd_set_can_reserve(struct irq_data *d)
  365. {
  366. __irqd_to_state(d) |= IRQD_CAN_RESERVE;
  367. }
  368. static inline void irqd_clr_can_reserve(struct irq_data *d)
  369. {
  370. __irqd_to_state(d) &= ~IRQD_CAN_RESERVE;
  371. }
  372. static inline bool irqd_can_reserve(struct irq_data *d)
  373. {
  374. return __irqd_to_state(d) & IRQD_CAN_RESERVE;
  375. }
  376. static inline void irqd_set_msi_nomask_quirk(struct irq_data *d)
  377. {
  378. __irqd_to_state(d) |= IRQD_MSI_NOMASK_QUIRK;
  379. }
  380. static inline void irqd_clr_msi_nomask_quirk(struct irq_data *d)
  381. {
  382. __irqd_to_state(d) &= ~IRQD_MSI_NOMASK_QUIRK;
  383. }
  384. static inline bool irqd_msi_nomask_quirk(struct irq_data *d)
  385. {
  386. return __irqd_to_state(d) & IRQD_MSI_NOMASK_QUIRK;
  387. }
  388. static inline void irqd_set_affinity_on_activate(struct irq_data *d)
  389. {
  390. __irqd_to_state(d) |= IRQD_AFFINITY_ON_ACTIVATE;
  391. }
  392. static inline bool irqd_affinity_on_activate(struct irq_data *d)
  393. {
  394. return __irqd_to_state(d) & IRQD_AFFINITY_ON_ACTIVATE;
  395. }
  396. #undef __irqd_to_state
  397. static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
  398. {
  399. return d->hwirq;
  400. }
  401. /**
  402. * struct irq_chip - hardware interrupt chip descriptor
  403. *
  404. * @parent_device: pointer to parent device for irqchip
  405. * @name: name for /proc/interrupts
  406. * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
  407. * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
  408. * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
  409. * @irq_disable: disable the interrupt
  410. * @irq_ack: start of a new interrupt
  411. * @irq_mask: mask an interrupt source
  412. * @irq_mask_ack: ack and mask an interrupt source
  413. * @irq_unmask: unmask an interrupt source
  414. * @irq_eoi: end of interrupt
  415. * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force
  416. * argument is true, it tells the driver to
  417. * unconditionally apply the affinity setting. Sanity
  418. * checks against the supplied affinity mask are not
  419. * required. This is used for CPU hotplug where the
  420. * target CPU is not yet set in the cpu_online_mask.
  421. * @irq_retrigger: resend an IRQ to the CPU
  422. * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
  423. * @irq_set_wake: enable/disable power-management wake-on of an IRQ
  424. * @irq_bus_lock: function to lock access to slow bus (i2c) chips
  425. * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
  426. * @irq_cpu_online: configure an interrupt source for a secondary CPU
  427. * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
  428. * @irq_suspend: function called from core code on suspend once per
  429. * chip, when one or more interrupts are installed
  430. * @irq_resume: function called from core code on resume once per chip,
  431. * when one ore more interrupts are installed
  432. * @irq_pm_shutdown: function called from core code on shutdown once per chip
  433. * @irq_calc_mask: Optional function to set irq_data.mask for special cases
  434. * @irq_print_chip: optional to print special chip info in show_interrupts
  435. * @irq_request_resources: optional to request resources before calling
  436. * any other callback related to this irq
  437. * @irq_release_resources: optional to release resources acquired with
  438. * irq_request_resources
  439. * @irq_compose_msi_msg: optional to compose message content for MSI
  440. * @irq_write_msi_msg: optional to write message content for MSI
  441. * @irq_get_irqchip_state: return the internal state of an interrupt
  442. * @irq_set_irqchip_state: set the internal state of a interrupt
  443. * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine
  444. * @ipi_send_single: send a single IPI to destination cpus
  445. * @ipi_send_mask: send an IPI to destination cpus in cpumask
  446. * @irq_nmi_setup: function called from core code before enabling an NMI
  447. * @irq_nmi_teardown: function called from core code after disabling an NMI
  448. * @flags: chip specific flags
  449. */
  450. struct irq_chip {
  451. struct device *parent_device;
  452. const char *name;
  453. unsigned int (*irq_startup)(struct irq_data *data);
  454. void (*irq_shutdown)(struct irq_data *data);
  455. void (*irq_enable)(struct irq_data *data);
  456. void (*irq_disable)(struct irq_data *data);
  457. void (*irq_ack)(struct irq_data *data);
  458. void (*irq_mask)(struct irq_data *data);
  459. void (*irq_mask_ack)(struct irq_data *data);
  460. void (*irq_unmask)(struct irq_data *data);
  461. void (*irq_eoi)(struct irq_data *data);
  462. int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
  463. int (*irq_retrigger)(struct irq_data *data);
  464. int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
  465. int (*irq_set_wake)(struct irq_data *data, unsigned int on);
  466. void (*irq_bus_lock)(struct irq_data *data);
  467. void (*irq_bus_sync_unlock)(struct irq_data *data);
  468. void (*irq_cpu_online)(struct irq_data *data);
  469. void (*irq_cpu_offline)(struct irq_data *data);
  470. void (*irq_suspend)(struct irq_data *data);
  471. void (*irq_resume)(struct irq_data *data);
  472. void (*irq_pm_shutdown)(struct irq_data *data);
  473. void (*irq_calc_mask)(struct irq_data *data);
  474. void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
  475. int (*irq_request_resources)(struct irq_data *data);
  476. void (*irq_release_resources)(struct irq_data *data);
  477. void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
  478. void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
  479. int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state);
  480. int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state);
  481. int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info);
  482. void (*ipi_send_single)(struct irq_data *data, unsigned int cpu);
  483. void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest);
  484. int (*irq_nmi_setup)(struct irq_data *data);
  485. void (*irq_nmi_teardown)(struct irq_data *data);
  486. unsigned long flags;
  487. };
  488. /*
  489. * irq_chip specific flags
  490. *
  491. * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
  492. * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
  493. * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
  494. * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
  495. * when irq enabled
  496. * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
  497. * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
  498. * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
  499. * IRQCHIP_SUPPORTS_LEVEL_MSI: Chip can provide two doorbells for Level MSIs
  500. * IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips
  501. * IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND: Invokes __enable_irq()/__disable_irq() for wake irqs
  502. * in the suspend path if they are in disabled state
  503. * IRQCHIP_AFFINITY_PRE_STARTUP: Default affinity update before startup
  504. */
  505. enum {
  506. IRQCHIP_SET_TYPE_MASKED = (1 << 0),
  507. IRQCHIP_EOI_IF_HANDLED = (1 << 1),
  508. IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
  509. IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
  510. IRQCHIP_SKIP_SET_WAKE = (1 << 4),
  511. IRQCHIP_ONESHOT_SAFE = (1 << 5),
  512. IRQCHIP_EOI_THREADED = (1 << 6),
  513. IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7),
  514. IRQCHIP_SUPPORTS_NMI = (1 << 8),
  515. IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = (1 << 9),
  516. IRQCHIP_AFFINITY_PRE_STARTUP = (1 << 10),
  517. };
  518. #include <linux/irqdesc.h>
  519. /*
  520. * Pick up the arch-dependent methods:
  521. */
  522. #include <asm/hw_irq.h>
  523. #ifndef NR_IRQS_LEGACY
  524. # define NR_IRQS_LEGACY 0
  525. #endif
  526. #ifndef ARCH_IRQ_INIT_FLAGS
  527. # define ARCH_IRQ_INIT_FLAGS 0
  528. #endif
  529. #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
  530. struct irqaction;
  531. extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
  532. extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
  533. extern void irq_cpu_online(void);
  534. extern void irq_cpu_offline(void);
  535. extern int irq_set_affinity_locked(struct irq_data *data,
  536. const struct cpumask *cpumask, bool force);
  537. extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info);
  538. #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION)
  539. extern void irq_migrate_all_off_this_cpu(void);
  540. extern int irq_affinity_online_cpu(unsigned int cpu);
  541. #else
  542. # define irq_affinity_online_cpu NULL
  543. #endif
  544. #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
  545. void __irq_move_irq(struct irq_data *data);
  546. static inline void irq_move_irq(struct irq_data *data)
  547. {
  548. if (unlikely(irqd_is_setaffinity_pending(data)))
  549. __irq_move_irq(data);
  550. }
  551. void irq_move_masked_irq(struct irq_data *data);
  552. void irq_force_complete_move(struct irq_desc *desc);
  553. #else
  554. static inline void irq_move_irq(struct irq_data *data) { }
  555. static inline void irq_move_masked_irq(struct irq_data *data) { }
  556. static inline void irq_force_complete_move(struct irq_desc *desc) { }
  557. #endif
  558. extern int no_irq_affinity;
  559. #ifdef CONFIG_HARDIRQS_SW_RESEND
  560. int irq_set_parent(int irq, int parent_irq);
  561. #else
  562. static inline int irq_set_parent(int irq, int parent_irq)
  563. {
  564. return 0;
  565. }
  566. #endif
  567. /*
  568. * Built-in IRQ handlers for various IRQ types,
  569. * callable via desc->handle_irq()
  570. */
  571. extern void handle_level_irq(struct irq_desc *desc);
  572. extern void handle_fasteoi_irq(struct irq_desc *desc);
  573. extern void handle_percpu_devid_fasteoi_ipi(struct irq_desc *desc);
  574. extern void handle_edge_irq(struct irq_desc *desc);
  575. extern void handle_edge_eoi_irq(struct irq_desc *desc);
  576. extern void handle_simple_irq(struct irq_desc *desc);
  577. extern void handle_untracked_irq(struct irq_desc *desc);
  578. extern void handle_percpu_irq(struct irq_desc *desc);
  579. extern void handle_percpu_devid_irq(struct irq_desc *desc);
  580. extern void handle_bad_irq(struct irq_desc *desc);
  581. extern void handle_nested_irq(unsigned int irq);
  582. extern void handle_fasteoi_nmi(struct irq_desc *desc);
  583. extern void handle_percpu_devid_fasteoi_nmi(struct irq_desc *desc);
  584. extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
  585. extern int irq_chip_pm_get(struct irq_data *data);
  586. extern int irq_chip_pm_put(struct irq_data *data);
  587. #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
  588. extern void handle_fasteoi_ack_irq(struct irq_desc *desc);
  589. extern void handle_fasteoi_mask_irq(struct irq_desc *desc);
  590. extern int irq_chip_set_parent_state(struct irq_data *data,
  591. enum irqchip_irq_state which,
  592. bool val);
  593. extern int irq_chip_get_parent_state(struct irq_data *data,
  594. enum irqchip_irq_state which,
  595. bool *state);
  596. extern void irq_chip_enable_parent(struct irq_data *data);
  597. extern void irq_chip_disable_parent(struct irq_data *data);
  598. extern void irq_chip_ack_parent(struct irq_data *data);
  599. extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
  600. extern void irq_chip_mask_parent(struct irq_data *data);
  601. extern void irq_chip_mask_ack_parent(struct irq_data *data);
  602. extern void irq_chip_unmask_parent(struct irq_data *data);
  603. extern void irq_chip_eoi_parent(struct irq_data *data);
  604. extern int irq_chip_set_affinity_parent(struct irq_data *data,
  605. const struct cpumask *dest,
  606. bool force);
  607. extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
  608. extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data,
  609. void *vcpu_info);
  610. extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type);
  611. extern int irq_chip_request_resources_parent(struct irq_data *data);
  612. extern void irq_chip_release_resources_parent(struct irq_data *data);
  613. #endif
  614. /* Handling of unhandled and spurious interrupts: */
  615. extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret);
  616. /* Enable/disable irq debugging output: */
  617. extern int noirqdebug_setup(char *str);
  618. /* Checks whether the interrupt can be requested by request_irq(): */
  619. extern int can_request_irq(unsigned int irq, unsigned long irqflags);
  620. /* Dummy irq-chip implementations: */
  621. extern struct irq_chip no_irq_chip;
  622. extern struct irq_chip dummy_irq_chip;
  623. extern void
  624. irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
  625. irq_flow_handler_t handle, const char *name);
  626. static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
  627. irq_flow_handler_t handle)
  628. {
  629. irq_set_chip_and_handler_name(irq, chip, handle, NULL);
  630. }
  631. extern int irq_set_percpu_devid(unsigned int irq);
  632. extern int irq_set_percpu_devid_partition(unsigned int irq,
  633. const struct cpumask *affinity);
  634. extern int irq_get_percpu_devid_partition(unsigned int irq,
  635. struct cpumask *affinity);
  636. extern void
  637. __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
  638. const char *name);
  639. static inline void
  640. irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
  641. {
  642. __irq_set_handler(irq, handle, 0, NULL);
  643. }
  644. /*
  645. * Set a highlevel chained flow handler for a given IRQ.
  646. * (a chained handler is automatically enabled and set to
  647. * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
  648. */
  649. static inline void
  650. irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
  651. {
  652. __irq_set_handler(irq, handle, 1, NULL);
  653. }
  654. /*
  655. * Set a highlevel chained flow handler and its data for a given IRQ.
  656. * (a chained handler is automatically enabled and set to
  657. * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
  658. */
  659. void
  660. irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
  661. void *data);
  662. void __irq_modify_status(unsigned int irq, unsigned long clr,
  663. unsigned long set, unsigned long mask);
  664. void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
  665. static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
  666. {
  667. irq_modify_status(irq, 0, set);
  668. }
  669. static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
  670. {
  671. irq_modify_status(irq, clr, 0);
  672. }
  673. static inline void irq_set_noprobe(unsigned int irq)
  674. {
  675. irq_modify_status(irq, 0, IRQ_NOPROBE);
  676. }
  677. static inline void irq_set_probe(unsigned int irq)
  678. {
  679. irq_modify_status(irq, IRQ_NOPROBE, 0);
  680. }
  681. static inline void irq_set_nothread(unsigned int irq)
  682. {
  683. irq_modify_status(irq, 0, IRQ_NOTHREAD);
  684. }
  685. static inline void irq_set_thread(unsigned int irq)
  686. {
  687. irq_modify_status(irq, IRQ_NOTHREAD, 0);
  688. }
  689. static inline void irq_set_nested_thread(unsigned int irq, bool nest)
  690. {
  691. if (nest)
  692. irq_set_status_flags(irq, IRQ_NESTED_THREAD);
  693. else
  694. irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
  695. }
  696. static inline void irq_set_percpu_devid_flags(unsigned int irq)
  697. {
  698. irq_set_status_flags(irq,
  699. IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
  700. IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
  701. }
  702. /* Set/get chip/data for an IRQ: */
  703. extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
  704. extern int irq_set_handler_data(unsigned int irq, void *data);
  705. extern int irq_set_chip_data(unsigned int irq, void *data);
  706. extern int irq_set_irq_type(unsigned int irq, unsigned int type);
  707. extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
  708. extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
  709. struct msi_desc *entry);
  710. extern struct irq_data *irq_get_irq_data(unsigned int irq);
  711. static inline struct irq_chip *irq_get_chip(unsigned int irq)
  712. {
  713. struct irq_data *d = irq_get_irq_data(irq);
  714. return d ? d->chip : NULL;
  715. }
  716. static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
  717. {
  718. return d->chip;
  719. }
  720. static inline void *irq_get_chip_data(unsigned int irq)
  721. {
  722. struct irq_data *d = irq_get_irq_data(irq);
  723. return d ? d->chip_data : NULL;
  724. }
  725. static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
  726. {
  727. return d->chip_data;
  728. }
  729. static inline void *irq_get_handler_data(unsigned int irq)
  730. {
  731. struct irq_data *d = irq_get_irq_data(irq);
  732. return d ? d->common->handler_data : NULL;
  733. }
  734. static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
  735. {
  736. return d->common->handler_data;
  737. }
  738. static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
  739. {
  740. struct irq_data *d = irq_get_irq_data(irq);
  741. return d ? d->common->msi_desc : NULL;
  742. }
  743. static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d)
  744. {
  745. return d->common->msi_desc;
  746. }
  747. static inline u32 irq_get_trigger_type(unsigned int irq)
  748. {
  749. struct irq_data *d = irq_get_irq_data(irq);
  750. return d ? irqd_get_trigger_type(d) : 0;
  751. }
  752. static inline int irq_common_data_get_node(struct irq_common_data *d)
  753. {
  754. #ifdef CONFIG_NUMA
  755. return d->node;
  756. #else
  757. return 0;
  758. #endif
  759. }
  760. static inline int irq_data_get_node(struct irq_data *d)
  761. {
  762. return irq_common_data_get_node(d->common);
  763. }
  764. static inline struct cpumask *irq_get_affinity_mask(int irq)
  765. {
  766. struct irq_data *d = irq_get_irq_data(irq);
  767. return d ? d->common->affinity : NULL;
  768. }
  769. static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d)
  770. {
  771. return d->common->affinity;
  772. }
  773. #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
  774. static inline
  775. struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
  776. {
  777. return d->common->effective_affinity;
  778. }
  779. static inline void irq_data_update_effective_affinity(struct irq_data *d,
  780. const struct cpumask *m)
  781. {
  782. cpumask_copy(d->common->effective_affinity, m);
  783. }
  784. #else
  785. static inline void irq_data_update_effective_affinity(struct irq_data *d,
  786. const struct cpumask *m)
  787. {
  788. }
  789. static inline
  790. struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
  791. {
  792. return d->common->affinity;
  793. }
  794. #endif
  795. unsigned int arch_dynirq_lower_bound(unsigned int from);
  796. int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
  797. struct module *owner,
  798. const struct irq_affinity_desc *affinity);
  799. int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from,
  800. unsigned int cnt, int node, struct module *owner,
  801. const struct irq_affinity_desc *affinity);
  802. /* use macros to avoid needing export.h for THIS_MODULE */
  803. #define irq_alloc_descs(irq, from, cnt, node) \
  804. __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL)
  805. #define irq_alloc_desc(node) \
  806. irq_alloc_descs(-1, 1, 1, node)
  807. #define irq_alloc_desc_at(at, node) \
  808. irq_alloc_descs(at, at, 1, node)
  809. #define irq_alloc_desc_from(from, node) \
  810. irq_alloc_descs(-1, from, 1, node)
  811. #define irq_alloc_descs_from(from, cnt, node) \
  812. irq_alloc_descs(-1, from, cnt, node)
  813. #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \
  814. __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL)
  815. #define devm_irq_alloc_desc(dev, node) \
  816. devm_irq_alloc_descs(dev, -1, 1, 1, node)
  817. #define devm_irq_alloc_desc_at(dev, at, node) \
  818. devm_irq_alloc_descs(dev, at, at, 1, node)
  819. #define devm_irq_alloc_desc_from(dev, from, node) \
  820. devm_irq_alloc_descs(dev, -1, from, 1, node)
  821. #define devm_irq_alloc_descs_from(dev, from, cnt, node) \
  822. devm_irq_alloc_descs(dev, -1, from, cnt, node)
  823. void irq_free_descs(unsigned int irq, unsigned int cnt);
  824. static inline void irq_free_desc(unsigned int irq)
  825. {
  826. irq_free_descs(irq, 1);
  827. }
  828. #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
  829. unsigned int irq_alloc_hwirqs(int cnt, int node);
  830. static inline unsigned int irq_alloc_hwirq(int node)
  831. {
  832. return irq_alloc_hwirqs(1, node);
  833. }
  834. void irq_free_hwirqs(unsigned int from, int cnt);
  835. static inline void irq_free_hwirq(unsigned int irq)
  836. {
  837. return irq_free_hwirqs(irq, 1);
  838. }
  839. int arch_setup_hwirq(unsigned int irq, int node);
  840. void arch_teardown_hwirq(unsigned int irq);
  841. #endif
  842. #ifdef CONFIG_GENERIC_IRQ_LEGACY
  843. void irq_init_desc(unsigned int irq);
  844. #endif
  845. /**
  846. * struct irq_chip_regs - register offsets for struct irq_gci
  847. * @enable: Enable register offset to reg_base
  848. * @disable: Disable register offset to reg_base
  849. * @mask: Mask register offset to reg_base
  850. * @ack: Ack register offset to reg_base
  851. * @eoi: Eoi register offset to reg_base
  852. * @type: Type configuration register offset to reg_base
  853. * @polarity: Polarity configuration register offset to reg_base
  854. */
  855. struct irq_chip_regs {
  856. unsigned long enable;
  857. unsigned long disable;
  858. unsigned long mask;
  859. unsigned long ack;
  860. unsigned long eoi;
  861. unsigned long type;
  862. unsigned long polarity;
  863. };
  864. /**
  865. * struct irq_chip_type - Generic interrupt chip instance for a flow type
  866. * @chip: The real interrupt chip which provides the callbacks
  867. * @regs: Register offsets for this chip
  868. * @handler: Flow handler associated with this chip
  869. * @type: Chip can handle these flow types
  870. * @mask_cache_priv: Cached mask register private to the chip type
  871. * @mask_cache: Pointer to cached mask register
  872. *
  873. * A irq_generic_chip can have several instances of irq_chip_type when
  874. * it requires different functions and register offsets for different
  875. * flow types.
  876. */
  877. struct irq_chip_type {
  878. struct irq_chip chip;
  879. struct irq_chip_regs regs;
  880. irq_flow_handler_t handler;
  881. u32 type;
  882. u32 mask_cache_priv;
  883. u32 *mask_cache;
  884. };
  885. /**
  886. * struct irq_chip_generic - Generic irq chip data structure
  887. * @lock: Lock to protect register and cache data access
  888. * @reg_base: Register base address (virtual)
  889. * @reg_readl: Alternate I/O accessor (defaults to readl if NULL)
  890. * @reg_writel: Alternate I/O accessor (defaults to writel if NULL)
  891. * @suspend: Function called from core code on suspend once per
  892. * chip; can be useful instead of irq_chip::suspend to
  893. * handle chip details even when no interrupts are in use
  894. * @resume: Function called from core code on resume once per chip;
  895. * can be useful instead of irq_chip::suspend to handle
  896. * chip details even when no interrupts are in use
  897. * @irq_base: Interrupt base nr for this chip
  898. * @irq_cnt: Number of interrupts handled by this chip
  899. * @mask_cache: Cached mask register shared between all chip types
  900. * @type_cache: Cached type register
  901. * @polarity_cache: Cached polarity register
  902. * @wake_enabled: Interrupt can wakeup from suspend
  903. * @wake_active: Interrupt is marked as an wakeup from suspend source
  904. * @num_ct: Number of available irq_chip_type instances (usually 1)
  905. * @private: Private data for non generic chip callbacks
  906. * @installed: bitfield to denote installed interrupts
  907. * @unused: bitfield to denote unused interrupts
  908. * @domain: irq domain pointer
  909. * @list: List head for keeping track of instances
  910. * @chip_types: Array of interrupt irq_chip_types
  911. *
  912. * Note, that irq_chip_generic can have multiple irq_chip_type
  913. * implementations which can be associated to a particular irq line of
  914. * an irq_chip_generic instance. That allows to share and protect
  915. * state in an irq_chip_generic instance when we need to implement
  916. * different flow mechanisms (level/edge) for it.
  917. */
  918. struct irq_chip_generic {
  919. raw_spinlock_t lock;
  920. void __iomem *reg_base;
  921. u32 (*reg_readl)(void __iomem *addr);
  922. void (*reg_writel)(u32 val, void __iomem *addr);
  923. void (*suspend)(struct irq_chip_generic *gc);
  924. void (*resume)(struct irq_chip_generic *gc);
  925. unsigned int irq_base;
  926. unsigned int irq_cnt;
  927. u32 mask_cache;
  928. u32 type_cache;
  929. u32 polarity_cache;
  930. u32 wake_enabled;
  931. u32 wake_active;
  932. unsigned int num_ct;
  933. void *private;
  934. unsigned long installed;
  935. unsigned long unused;
  936. struct irq_domain *domain;
  937. struct list_head list;
  938. struct irq_chip_type chip_types[];
  939. };
  940. /**
  941. * enum irq_gc_flags - Initialization flags for generic irq chips
  942. * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
  943. * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
  944. * irq chips which need to call irq_set_wake() on
  945. * the parent irq. Usually GPIO implementations
  946. * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
  947. * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
  948. * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
  949. */
  950. enum irq_gc_flags {
  951. IRQ_GC_INIT_MASK_CACHE = 1 << 0,
  952. IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
  953. IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
  954. IRQ_GC_NO_MASK = 1 << 3,
  955. IRQ_GC_BE_IO = 1 << 4,
  956. };
  957. /*
  958. * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
  959. * @irqs_per_chip: Number of interrupts per chip
  960. * @num_chips: Number of chips
  961. * @irq_flags_to_set: IRQ* flags to set on irq setup
  962. * @irq_flags_to_clear: IRQ* flags to clear on irq setup
  963. * @gc_flags: Generic chip specific setup flags
  964. * @gc: Array of pointers to generic interrupt chips
  965. */
  966. struct irq_domain_chip_generic {
  967. unsigned int irqs_per_chip;
  968. unsigned int num_chips;
  969. unsigned int irq_flags_to_clear;
  970. unsigned int irq_flags_to_set;
  971. enum irq_gc_flags gc_flags;
  972. struct irq_chip_generic *gc[];
  973. };
  974. /* Generic chip callback functions */
  975. void irq_gc_noop(struct irq_data *d);
  976. void irq_gc_mask_disable_reg(struct irq_data *d);
  977. void irq_gc_mask_set_bit(struct irq_data *d);
  978. void irq_gc_mask_clr_bit(struct irq_data *d);
  979. void irq_gc_unmask_enable_reg(struct irq_data *d);
  980. void irq_gc_ack_set_bit(struct irq_data *d);
  981. void irq_gc_ack_clr_bit(struct irq_data *d);
  982. void irq_gc_mask_disable_and_ack_set(struct irq_data *d);
  983. void irq_gc_eoi(struct irq_data *d);
  984. int irq_gc_set_wake(struct irq_data *d, unsigned int on);
  985. /* Setup functions for irq_chip_generic */
  986. int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
  987. irq_hw_number_t hw_irq);
  988. struct irq_chip_generic *
  989. irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
  990. void __iomem *reg_base, irq_flow_handler_t handler);
  991. void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
  992. enum irq_gc_flags flags, unsigned int clr,
  993. unsigned int set);
  994. int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
  995. void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
  996. unsigned int clr, unsigned int set);
  997. struct irq_chip_generic *
  998. devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct,
  999. unsigned int irq_base, void __iomem *reg_base,
  1000. irq_flow_handler_t handler);
  1001. int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc,
  1002. u32 msk, enum irq_gc_flags flags,
  1003. unsigned int clr, unsigned int set);
  1004. struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
  1005. int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
  1006. int num_ct, const char *name,
  1007. irq_flow_handler_t handler,
  1008. unsigned int clr, unsigned int set,
  1009. enum irq_gc_flags flags);
  1010. #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \
  1011. handler, clr, set, flags) \
  1012. ({ \
  1013. MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \
  1014. __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\
  1015. handler, clr, set, flags); \
  1016. })
  1017. static inline void irq_free_generic_chip(struct irq_chip_generic *gc)
  1018. {
  1019. kfree(gc);
  1020. }
  1021. static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc,
  1022. u32 msk, unsigned int clr,
  1023. unsigned int set)
  1024. {
  1025. irq_remove_generic_chip(gc, msk, clr, set);
  1026. irq_free_generic_chip(gc);
  1027. }
  1028. static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
  1029. {
  1030. return container_of(d->chip, struct irq_chip_type, chip);
  1031. }
  1032. #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
  1033. #ifdef CONFIG_SMP
  1034. static inline void irq_gc_lock(struct irq_chip_generic *gc)
  1035. {
  1036. raw_spin_lock(&gc->lock);
  1037. }
  1038. static inline void irq_gc_unlock(struct irq_chip_generic *gc)
  1039. {
  1040. raw_spin_unlock(&gc->lock);
  1041. }
  1042. #else
  1043. static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
  1044. static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
  1045. #endif
  1046. /*
  1047. * The irqsave variants are for usage in non interrupt code. Do not use
  1048. * them in irq_chip callbacks. Use irq_gc_lock() instead.
  1049. */
  1050. #define irq_gc_lock_irqsave(gc, flags) \
  1051. raw_spin_lock_irqsave(&(gc)->lock, flags)
  1052. #define irq_gc_unlock_irqrestore(gc, flags) \
  1053. raw_spin_unlock_irqrestore(&(gc)->lock, flags)
  1054. static inline void irq_reg_writel(struct irq_chip_generic *gc,
  1055. u32 val, int reg_offset)
  1056. {
  1057. if (gc->reg_writel)
  1058. gc->reg_writel(val, gc->reg_base + reg_offset);
  1059. else
  1060. writel(val, gc->reg_base + reg_offset);
  1061. }
  1062. static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
  1063. int reg_offset)
  1064. {
  1065. if (gc->reg_readl)
  1066. return gc->reg_readl(gc->reg_base + reg_offset);
  1067. else
  1068. return readl(gc->reg_base + reg_offset);
  1069. }
  1070. struct irq_matrix;
  1071. struct irq_matrix *irq_alloc_matrix(unsigned int matrix_bits,
  1072. unsigned int alloc_start,
  1073. unsigned int alloc_end);
  1074. void irq_matrix_online(struct irq_matrix *m);
  1075. void irq_matrix_offline(struct irq_matrix *m);
  1076. void irq_matrix_assign_system(struct irq_matrix *m, unsigned int bit, bool replace);
  1077. int irq_matrix_reserve_managed(struct irq_matrix *m, const struct cpumask *msk);
  1078. void irq_matrix_remove_managed(struct irq_matrix *m, const struct cpumask *msk);
  1079. int irq_matrix_alloc_managed(struct irq_matrix *m, const struct cpumask *msk,
  1080. unsigned int *mapped_cpu);
  1081. void irq_matrix_reserve(struct irq_matrix *m);
  1082. void irq_matrix_remove_reserved(struct irq_matrix *m);
  1083. int irq_matrix_alloc(struct irq_matrix *m, const struct cpumask *msk,
  1084. bool reserved, unsigned int *mapped_cpu);
  1085. void irq_matrix_free(struct irq_matrix *m, unsigned int cpu,
  1086. unsigned int bit, bool managed);
  1087. void irq_matrix_assign(struct irq_matrix *m, unsigned int bit);
  1088. unsigned int irq_matrix_available(struct irq_matrix *m, bool cpudown);
  1089. unsigned int irq_matrix_allocated(struct irq_matrix *m);
  1090. unsigned int irq_matrix_reserved(struct irq_matrix *m);
  1091. void irq_matrix_debug_show(struct seq_file *sf, struct irq_matrix *m, int ind);
  1092. /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */
  1093. #define INVALID_HWIRQ (~0UL)
  1094. irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu);
  1095. int __ipi_send_single(struct irq_desc *desc, unsigned int cpu);
  1096. int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest);
  1097. int ipi_send_single(unsigned int virq, unsigned int cpu);
  1098. int ipi_send_mask(unsigned int virq, const struct cpumask *dest);
  1099. #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER
  1100. /*
  1101. * Registers a generic IRQ handling function as the top-level IRQ handler in
  1102. * the system, which is generally the first C code called from an assembly
  1103. * architecture-specific interrupt handler.
  1104. *
  1105. * Returns 0 on success, or -EBUSY if an IRQ handler has already been
  1106. * registered.
  1107. */
  1108. int __init set_handle_irq(void (*handle_irq)(struct pt_regs *));
  1109. /*
  1110. * Allows interrupt handlers to find the irqchip that's been registered as the
  1111. * top-level IRQ handler.
  1112. */
  1113. extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init;
  1114. #else
  1115. #define set_handle_irq(handle_irq) \
  1116. do { \
  1117. (void)handle_irq; \
  1118. WARN_ON(1); \
  1119. } while (0)
  1120. #endif
  1121. #endif /* _LINUX_IRQ_H */