fsl_devices.h 4.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * include/linux/fsl_devices.h
  4. *
  5. * Definitions for any platform device related flags or structures for
  6. * Freescale processor devices
  7. *
  8. * Maintainer: Kumar Gala <galak@kernel.crashing.org>
  9. *
  10. * Copyright 2004,2012 Freescale Semiconductor, Inc
  11. */
  12. #ifndef _FSL_DEVICE_H_
  13. #define _FSL_DEVICE_H_
  14. #define FSL_UTMI_PHY_DLY 10 /*As per P1010RM, delay for UTMI
  15. PHY CLK to become stable - 10ms*/
  16. #define FSL_USB_PHY_CLK_TIMEOUT 10000 /* uSec */
  17. #include <linux/types.h>
  18. /*
  19. * Some conventions on how we handle peripherals on Freescale chips
  20. *
  21. * unique device: a platform_device entry in fsl_plat_devs[] plus
  22. * associated device information in its platform_data structure.
  23. *
  24. * A chip is described by a set of unique devices.
  25. *
  26. * Each sub-arch has its own master list of unique devices and
  27. * enumerates them by enum fsl_devices in a sub-arch specific header
  28. *
  29. * The platform data structure is broken into two parts. The
  30. * first is device specific information that help identify any
  31. * unique features of a peripheral. The second is any
  32. * information that may be defined by the board or how the device
  33. * is connected externally of the chip.
  34. *
  35. * naming conventions:
  36. * - platform data structures: <driver>_platform_data
  37. * - platform data device flags: FSL_<driver>_DEV_<FLAG>
  38. * - platform data board flags: FSL_<driver>_BRD_<FLAG>
  39. *
  40. */
  41. enum fsl_usb2_controller_ver {
  42. FSL_USB_VER_NONE = -1,
  43. FSL_USB_VER_OLD = 0,
  44. FSL_USB_VER_1_6 = 1,
  45. FSL_USB_VER_2_2 = 2,
  46. FSL_USB_VER_2_4 = 3,
  47. FSL_USB_VER_2_5 = 4,
  48. };
  49. enum fsl_usb2_operating_modes {
  50. FSL_USB2_MPH_HOST,
  51. FSL_USB2_DR_HOST,
  52. FSL_USB2_DR_DEVICE,
  53. FSL_USB2_DR_OTG,
  54. };
  55. enum fsl_usb2_phy_modes {
  56. FSL_USB2_PHY_NONE,
  57. FSL_USB2_PHY_ULPI,
  58. FSL_USB2_PHY_UTMI,
  59. FSL_USB2_PHY_UTMI_WIDE,
  60. FSL_USB2_PHY_SERIAL,
  61. FSL_USB2_PHY_UTMI_DUAL,
  62. };
  63. struct clk;
  64. struct platform_device;
  65. struct fsl_usb2_platform_data {
  66. /* board specific information */
  67. enum fsl_usb2_controller_ver controller_ver;
  68. enum fsl_usb2_operating_modes operating_mode;
  69. enum fsl_usb2_phy_modes phy_mode;
  70. unsigned int port_enables;
  71. unsigned int workaround;
  72. int (*init)(struct platform_device *);
  73. void (*exit)(struct platform_device *);
  74. void __iomem *regs; /* ioremap'd register base */
  75. struct clk *clk;
  76. unsigned power_budget; /* hcd->power_budget */
  77. unsigned big_endian_mmio:1;
  78. unsigned big_endian_desc:1;
  79. unsigned es:1; /* need USBMODE:ES */
  80. unsigned le_setup_buf:1;
  81. unsigned have_sysif_regs:1;
  82. unsigned invert_drvvbus:1;
  83. unsigned invert_pwr_fault:1;
  84. unsigned suspended:1;
  85. unsigned already_suspended:1;
  86. unsigned has_fsl_erratum_a007792:1;
  87. unsigned has_fsl_erratum_14:1;
  88. unsigned has_fsl_erratum_a005275:1;
  89. unsigned has_fsl_erratum_a005697:1;
  90. unsigned has_fsl_erratum_a006918:1;
  91. unsigned check_phy_clk_valid:1;
  92. /* register save area for suspend/resume */
  93. u32 pm_command;
  94. u32 pm_status;
  95. u32 pm_intr_enable;
  96. u32 pm_frame_index;
  97. u32 pm_segment;
  98. u32 pm_frame_list;
  99. u32 pm_async_next;
  100. u32 pm_configured_flag;
  101. u32 pm_portsc;
  102. u32 pm_usbgenctrl;
  103. };
  104. /* Flags in fsl_usb2_mph_platform_data */
  105. #define FSL_USB2_PORT0_ENABLED 0x00000001
  106. #define FSL_USB2_PORT1_ENABLED 0x00000002
  107. #define FLS_USB2_WORKAROUND_ENGCM09152 (1 << 0)
  108. struct spi_device;
  109. struct fsl_spi_platform_data {
  110. u32 initial_spmode; /* initial SPMODE value */
  111. s16 bus_num;
  112. unsigned int flags;
  113. #define SPI_QE_CPU_MODE (1 << 0) /* QE CPU ("PIO") mode */
  114. #define SPI_CPM_MODE (1 << 1) /* CPM/QE ("DMA") mode */
  115. #define SPI_CPM1 (1 << 2) /* SPI unit is in CPM1 block */
  116. #define SPI_CPM2 (1 << 3) /* SPI unit is in CPM2 block */
  117. #define SPI_QE (1 << 4) /* SPI unit is in QE block */
  118. /* board specific information */
  119. u16 max_chipselect;
  120. void (*cs_control)(struct spi_device *spi, bool on);
  121. u32 sysclk;
  122. };
  123. struct mpc8xx_pcmcia_ops {
  124. void(*hw_ctrl)(int slot, int enable);
  125. int(*voltage_set)(int slot, int vcc, int vpp);
  126. };
  127. /* Returns non-zero if the current suspend operation would
  128. * lead to a deep sleep (i.e. power removed from the core,
  129. * instead of just the clock).
  130. */
  131. #if defined(CONFIG_PPC_83xx) && defined(CONFIG_SUSPEND)
  132. int fsl_deep_sleep(void);
  133. #else
  134. static inline int fsl_deep_sleep(void) { return 0; }
  135. #endif
  136. #endif /* _FSL_DEVICE_H_ */