ptp_qoriq.h 7.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2010 OMICRON electronics GmbH
  4. * Copyright 2018 NXP
  5. */
  6. #ifndef __PTP_QORIQ_H__
  7. #define __PTP_QORIQ_H__
  8. #include <linux/io.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/ptp_clock_kernel.h>
  11. /*
  12. * qoriq ptp registers
  13. */
  14. struct ctrl_regs {
  15. u32 tmr_ctrl; /* Timer control register */
  16. u32 tmr_tevent; /* Timestamp event register */
  17. u32 tmr_temask; /* Timer event mask register */
  18. u32 tmr_pevent; /* Timestamp event register */
  19. u32 tmr_pemask; /* Timer event mask register */
  20. u32 tmr_stat; /* Timestamp status register */
  21. u32 tmr_cnt_h; /* Timer counter high register */
  22. u32 tmr_cnt_l; /* Timer counter low register */
  23. u32 tmr_add; /* Timer drift compensation addend register */
  24. u32 tmr_acc; /* Timer accumulator register */
  25. u32 tmr_prsc; /* Timer prescale */
  26. u8 res1[4];
  27. u32 tmroff_h; /* Timer offset high */
  28. u32 tmroff_l; /* Timer offset low */
  29. };
  30. struct alarm_regs {
  31. u32 tmr_alarm1_h; /* Timer alarm 1 high register */
  32. u32 tmr_alarm1_l; /* Timer alarm 1 high register */
  33. u32 tmr_alarm2_h; /* Timer alarm 2 high register */
  34. u32 tmr_alarm2_l; /* Timer alarm 2 high register */
  35. };
  36. struct fiper_regs {
  37. u32 tmr_fiper1; /* Timer fixed period interval */
  38. u32 tmr_fiper2; /* Timer fixed period interval */
  39. u32 tmr_fiper3; /* Timer fixed period interval */
  40. };
  41. struct etts_regs {
  42. u32 tmr_etts1_h; /* Timestamp of general purpose external trigger */
  43. u32 tmr_etts1_l; /* Timestamp of general purpose external trigger */
  44. u32 tmr_etts2_h; /* Timestamp of general purpose external trigger */
  45. u32 tmr_etts2_l; /* Timestamp of general purpose external trigger */
  46. };
  47. struct ptp_qoriq_registers {
  48. struct ctrl_regs __iomem *ctrl_regs;
  49. struct alarm_regs __iomem *alarm_regs;
  50. struct fiper_regs __iomem *fiper_regs;
  51. struct etts_regs __iomem *etts_regs;
  52. };
  53. /* Offset definitions for the four register groups */
  54. #define ETSEC_CTRL_REGS_OFFSET 0x0
  55. #define ETSEC_ALARM_REGS_OFFSET 0x40
  56. #define ETSEC_FIPER_REGS_OFFSET 0x80
  57. #define ETSEC_ETTS_REGS_OFFSET 0xa0
  58. #define CTRL_REGS_OFFSET 0x80
  59. #define ALARM_REGS_OFFSET 0xb8
  60. #define FIPER_REGS_OFFSET 0xd0
  61. #define ETTS_REGS_OFFSET 0xe0
  62. /* Bit definitions for the TMR_CTRL register */
  63. #define ALM1P (1<<31) /* Alarm1 output polarity */
  64. #define ALM2P (1<<30) /* Alarm2 output polarity */
  65. #define FIPERST (1<<28) /* FIPER start indication */
  66. #define PP1L (1<<27) /* Fiper1 pulse loopback mode enabled. */
  67. #define PP2L (1<<26) /* Fiper2 pulse loopback mode enabled. */
  68. #define TCLK_PERIOD_SHIFT (16) /* 1588 timer reference clock period. */
  69. #define TCLK_PERIOD_MASK (0x3ff)
  70. #define RTPE (1<<15) /* Record Tx Timestamp to PAL Enable. */
  71. #define FRD (1<<14) /* FIPER Realignment Disable */
  72. #define ESFDP (1<<11) /* External Tx/Rx SFD Polarity. */
  73. #define ESFDE (1<<10) /* External Tx/Rx SFD Enable. */
  74. #define ETEP2 (1<<9) /* External trigger 2 edge polarity */
  75. #define ETEP1 (1<<8) /* External trigger 1 edge polarity */
  76. #define COPH (1<<7) /* Generated clock output phase. */
  77. #define CIPH (1<<6) /* External oscillator input clock phase */
  78. #define TMSR (1<<5) /* Timer soft reset. */
  79. #define BYP (1<<3) /* Bypass drift compensated clock */
  80. #define TE (1<<2) /* 1588 timer enable. */
  81. #define CKSEL_SHIFT (0) /* 1588 Timer reference clock source */
  82. #define CKSEL_MASK (0x3)
  83. /* Bit definitions for the TMR_TEVENT register */
  84. #define ETS2 (1<<25) /* External trigger 2 timestamp sampled */
  85. #define ETS1 (1<<24) /* External trigger 1 timestamp sampled */
  86. #define ALM2 (1<<17) /* Current time = alarm time register 2 */
  87. #define ALM1 (1<<16) /* Current time = alarm time register 1 */
  88. #define PP1 (1<<7) /* periodic pulse generated on FIPER1 */
  89. #define PP2 (1<<6) /* periodic pulse generated on FIPER2 */
  90. #define PP3 (1<<5) /* periodic pulse generated on FIPER3 */
  91. /* Bit definitions for the TMR_TEMASK register */
  92. #define ETS2EN (1<<25) /* External trigger 2 timestamp enable */
  93. #define ETS1EN (1<<24) /* External trigger 1 timestamp enable */
  94. #define ALM2EN (1<<17) /* Timer ALM2 event enable */
  95. #define ALM1EN (1<<16) /* Timer ALM1 event enable */
  96. #define PP1EN (1<<7) /* Periodic pulse event 1 enable */
  97. #define PP2EN (1<<6) /* Periodic pulse event 2 enable */
  98. /* Bit definitions for the TMR_PEVENT register */
  99. #define TXP2 (1<<9) /* PTP transmitted timestamp im TXTS2 */
  100. #define TXP1 (1<<8) /* PTP transmitted timestamp in TXTS1 */
  101. #define RXP (1<<0) /* PTP frame has been received */
  102. /* Bit definitions for the TMR_PEMASK register */
  103. #define TXP2EN (1<<9) /* Transmit PTP packet event 2 enable */
  104. #define TXP1EN (1<<8) /* Transmit PTP packet event 1 enable */
  105. #define RXPEN (1<<0) /* Receive PTP packet event enable */
  106. /* Bit definitions for the TMR_STAT register */
  107. #define STAT_VEC_SHIFT (0) /* Timer general purpose status vector */
  108. #define STAT_VEC_MASK (0x3f)
  109. #define ETS1_VLD (1<<24)
  110. #define ETS2_VLD (1<<25)
  111. /* Bit definitions for the TMR_PRSC register */
  112. #define PRSC_OCK_SHIFT (0) /* Output clock division/prescale factor. */
  113. #define PRSC_OCK_MASK (0xffff)
  114. #define DRIVER "ptp_qoriq"
  115. #define N_EXT_TS 2
  116. #define DEFAULT_CKSEL 1
  117. #define DEFAULT_TMR_PRSC 2
  118. #define DEFAULT_FIPER1_PERIOD 1000000000
  119. #define DEFAULT_FIPER2_PERIOD 1000000000
  120. #define DEFAULT_FIPER3_PERIOD 1000000000
  121. struct ptp_qoriq {
  122. void __iomem *base;
  123. struct ptp_qoriq_registers regs;
  124. spinlock_t lock; /* protects regs */
  125. struct ptp_clock *clock;
  126. struct ptp_clock_info caps;
  127. struct resource *rsrc;
  128. struct dentry *debugfs_root;
  129. struct device *dev;
  130. bool extts_fifo_support;
  131. bool fiper3_support;
  132. int irq;
  133. int phc_index;
  134. u32 tclk_period; /* nanoseconds */
  135. u32 tmr_prsc;
  136. u32 tmr_add;
  137. u32 cksel;
  138. u32 tmr_fiper1;
  139. u32 tmr_fiper2;
  140. u32 tmr_fiper3;
  141. u32 (*read)(unsigned __iomem *addr);
  142. void (*write)(unsigned __iomem *addr, u32 val);
  143. };
  144. static inline u32 qoriq_read_be(unsigned __iomem *addr)
  145. {
  146. return ioread32be(addr);
  147. }
  148. static inline void qoriq_write_be(unsigned __iomem *addr, u32 val)
  149. {
  150. iowrite32be(val, addr);
  151. }
  152. static inline u32 qoriq_read_le(unsigned __iomem *addr)
  153. {
  154. return ioread32(addr);
  155. }
  156. static inline void qoriq_write_le(unsigned __iomem *addr, u32 val)
  157. {
  158. iowrite32(val, addr);
  159. }
  160. irqreturn_t ptp_qoriq_isr(int irq, void *priv);
  161. int ptp_qoriq_init(struct ptp_qoriq *ptp_qoriq, void __iomem *base,
  162. const struct ptp_clock_info *caps);
  163. void ptp_qoriq_free(struct ptp_qoriq *ptp_qoriq);
  164. int ptp_qoriq_adjfine(struct ptp_clock_info *ptp, long scaled_ppm);
  165. int ptp_qoriq_adjtime(struct ptp_clock_info *ptp, s64 delta);
  166. int ptp_qoriq_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts);
  167. int ptp_qoriq_settime(struct ptp_clock_info *ptp,
  168. const struct timespec64 *ts);
  169. int ptp_qoriq_enable(struct ptp_clock_info *ptp,
  170. struct ptp_clock_request *rq, int on);
  171. int extts_clean_up(struct ptp_qoriq *ptp_qoriq, int index, bool update_event);
  172. #ifdef CONFIG_DEBUG_FS
  173. void ptp_qoriq_create_debugfs(struct ptp_qoriq *ptp_qoriq);
  174. void ptp_qoriq_remove_debugfs(struct ptp_qoriq *ptp_qoriq);
  175. #else
  176. static inline void ptp_qoriq_create_debugfs(struct ptp_qoriq *ptp_qoriq)
  177. { }
  178. static inline void ptp_qoriq_remove_debugfs(struct ptp_qoriq *ptp_qoriq)
  179. { }
  180. #endif
  181. #endif