enetc_mdio.h 1.6 KB

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  1. /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
  2. /* Copyright 2019 NXP */
  3. #ifndef _FSL_ENETC_MDIO_H_
  4. #define _FSL_ENETC_MDIO_H_
  5. #include <linux/phy.h>
  6. /* PCS registers */
  7. #define ENETC_PCS_LINK_TIMER1 0x12
  8. #define ENETC_PCS_LINK_TIMER1_VAL 0x06a0
  9. #define ENETC_PCS_LINK_TIMER2 0x13
  10. #define ENETC_PCS_LINK_TIMER2_VAL 0x0003
  11. #define ENETC_PCS_IF_MODE 0x14
  12. #define ENETC_PCS_IF_MODE_SGMII_EN BIT(0)
  13. #define ENETC_PCS_IF_MODE_USE_SGMII_AN BIT(1)
  14. #define ENETC_PCS_IF_MODE_SGMII_SPEED(x) (((x) << 2) & GENMASK(3, 2))
  15. #define ENETC_PCS_IF_MODE_DUPLEX_HALF BIT(3)
  16. /* Not a mistake, the SerDes PLL needs to be set at 3.125 GHz by Reset
  17. * Configuration Word (RCW, outside Linux control) for 2.5G SGMII mode. The PCS
  18. * still thinks it's at gigabit.
  19. */
  20. enum enetc_pcs_speed {
  21. ENETC_PCS_SPEED_10 = 0,
  22. ENETC_PCS_SPEED_100 = 1,
  23. ENETC_PCS_SPEED_1000 = 2,
  24. ENETC_PCS_SPEED_2500 = 2,
  25. };
  26. struct enetc_hw;
  27. struct enetc_mdio_priv {
  28. struct enetc_hw *hw;
  29. int mdio_base;
  30. };
  31. #if IS_REACHABLE(CONFIG_FSL_ENETC_MDIO)
  32. int enetc_mdio_read(struct mii_bus *bus, int phy_id, int regnum);
  33. int enetc_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value);
  34. struct enetc_hw *enetc_hw_alloc(struct device *dev, void __iomem *port_regs);
  35. #else
  36. static inline int enetc_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
  37. { return -EINVAL; }
  38. static inline int enetc_mdio_write(struct mii_bus *bus, int phy_id, int regnum,
  39. u16 value)
  40. { return -EINVAL; }
  41. struct enetc_hw *enetc_hw_alloc(struct device *dev, void __iomem *port_regs)
  42. { return ERR_PTR(-EINVAL); }
  43. #endif
  44. #endif