xlnx-zynqmp.h 13 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Xilinx Zynq MPSoC Firmware layer
  4. *
  5. * Copyright (C) 2014-2019 Xilinx
  6. *
  7. * Michal Simek <michal.simek@xilinx.com>
  8. * Davorin Mista <davorin.mista@aggios.com>
  9. * Jolly Shah <jollys@xilinx.com>
  10. * Rajan Vaja <rajanv@xilinx.com>
  11. */
  12. #ifndef __FIRMWARE_ZYNQMP_H__
  13. #define __FIRMWARE_ZYNQMP_H__
  14. #define ZYNQMP_PM_VERSION_MAJOR 1
  15. #define ZYNQMP_PM_VERSION_MINOR 0
  16. #define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
  17. ZYNQMP_PM_VERSION_MINOR)
  18. #define ZYNQMP_TZ_VERSION_MAJOR 1
  19. #define ZYNQMP_TZ_VERSION_MINOR 0
  20. #define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
  21. ZYNQMP_TZ_VERSION_MINOR)
  22. /* SMC SIP service Call Function Identifier Prefix */
  23. #define PM_SIP_SVC 0xC2000000
  24. #define PM_GET_TRUSTZONE_VERSION 0xa03
  25. #define PM_SET_SUSPEND_MODE 0xa02
  26. #define GET_CALLBACK_DATA 0xa01
  27. /* Number of 32bits values in payload */
  28. #define PAYLOAD_ARG_CNT 4U
  29. /* Number of arguments for a callback */
  30. #define CB_ARG_CNT 4
  31. /* Payload size (consists of callback API ID + arguments) */
  32. #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
  33. #define ZYNQMP_PM_MAX_QOS 100U
  34. #define GSS_NUM_REGS (4)
  35. /* Node capabilities */
  36. #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
  37. #define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
  38. #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
  39. #define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
  40. /*
  41. * Firmware FPGA Manager flags
  42. * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
  43. * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
  44. */
  45. #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
  46. #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
  47. enum pm_api_id {
  48. PM_GET_API_VERSION = 1,
  49. PM_SYSTEM_SHUTDOWN = 12,
  50. PM_REQUEST_NODE = 13,
  51. PM_RELEASE_NODE,
  52. PM_SET_REQUIREMENT,
  53. PM_RESET_ASSERT = 17,
  54. PM_RESET_GET_STATUS,
  55. PM_PM_INIT_FINALIZE = 21,
  56. PM_FPGA_LOAD,
  57. PM_FPGA_GET_STATUS,
  58. PM_GET_CHIPID = 24,
  59. PM_IOCTL = 34,
  60. PM_QUERY_DATA,
  61. PM_CLOCK_ENABLE,
  62. PM_CLOCK_DISABLE,
  63. PM_CLOCK_GETSTATE,
  64. PM_CLOCK_SETDIVIDER,
  65. PM_CLOCK_GETDIVIDER,
  66. PM_CLOCK_SETRATE,
  67. PM_CLOCK_GETRATE,
  68. PM_CLOCK_SETPARENT,
  69. PM_CLOCK_GETPARENT,
  70. PM_SECURE_AES = 47,
  71. PM_FEATURE_CHECK = 63,
  72. PM_API_MAX,
  73. };
  74. /* PMU-FW return status codes */
  75. enum pm_ret_status {
  76. XST_PM_SUCCESS = 0,
  77. XST_PM_NO_FEATURE = 19,
  78. XST_PM_INTERNAL = 2000,
  79. XST_PM_CONFLICT,
  80. XST_PM_NO_ACCESS,
  81. XST_PM_INVALID_NODE,
  82. XST_PM_DOUBLE_REQ,
  83. XST_PM_ABORT_SUSPEND,
  84. XST_PM_MULT_USER = 2008,
  85. };
  86. enum pm_ioctl_id {
  87. IOCTL_SD_DLL_RESET = 6,
  88. IOCTL_SET_SD_TAPDELAY,
  89. IOCTL_SET_PLL_FRAC_MODE,
  90. IOCTL_GET_PLL_FRAC_MODE,
  91. IOCTL_SET_PLL_FRAC_DATA,
  92. IOCTL_GET_PLL_FRAC_DATA,
  93. IOCTL_WRITE_GGS = 12,
  94. IOCTL_READ_GGS = 13,
  95. IOCTL_WRITE_PGGS = 14,
  96. IOCTL_READ_PGGS = 15,
  97. /* Set healthy bit value */
  98. IOCTL_SET_BOOT_HEALTH_STATUS = 17,
  99. };
  100. enum pm_query_id {
  101. PM_QID_INVALID,
  102. PM_QID_CLOCK_GET_NAME,
  103. PM_QID_CLOCK_GET_TOPOLOGY,
  104. PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
  105. PM_QID_CLOCK_GET_PARENTS,
  106. PM_QID_CLOCK_GET_ATTRIBUTES,
  107. PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
  108. PM_QID_CLOCK_GET_MAX_DIVISOR,
  109. };
  110. enum zynqmp_pm_reset_action {
  111. PM_RESET_ACTION_RELEASE,
  112. PM_RESET_ACTION_ASSERT,
  113. PM_RESET_ACTION_PULSE,
  114. };
  115. enum zynqmp_pm_reset {
  116. ZYNQMP_PM_RESET_START = 1000,
  117. ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
  118. ZYNQMP_PM_RESET_PCIE_BRIDGE,
  119. ZYNQMP_PM_RESET_PCIE_CTRL,
  120. ZYNQMP_PM_RESET_DP,
  121. ZYNQMP_PM_RESET_SWDT_CRF,
  122. ZYNQMP_PM_RESET_AFI_FM5,
  123. ZYNQMP_PM_RESET_AFI_FM4,
  124. ZYNQMP_PM_RESET_AFI_FM3,
  125. ZYNQMP_PM_RESET_AFI_FM2,
  126. ZYNQMP_PM_RESET_AFI_FM1,
  127. ZYNQMP_PM_RESET_AFI_FM0,
  128. ZYNQMP_PM_RESET_GDMA,
  129. ZYNQMP_PM_RESET_GPU_PP1,
  130. ZYNQMP_PM_RESET_GPU_PP0,
  131. ZYNQMP_PM_RESET_GPU,
  132. ZYNQMP_PM_RESET_GT,
  133. ZYNQMP_PM_RESET_SATA,
  134. ZYNQMP_PM_RESET_ACPU3_PWRON,
  135. ZYNQMP_PM_RESET_ACPU2_PWRON,
  136. ZYNQMP_PM_RESET_ACPU1_PWRON,
  137. ZYNQMP_PM_RESET_ACPU0_PWRON,
  138. ZYNQMP_PM_RESET_APU_L2,
  139. ZYNQMP_PM_RESET_ACPU3,
  140. ZYNQMP_PM_RESET_ACPU2,
  141. ZYNQMP_PM_RESET_ACPU1,
  142. ZYNQMP_PM_RESET_ACPU0,
  143. ZYNQMP_PM_RESET_DDR,
  144. ZYNQMP_PM_RESET_APM_FPD,
  145. ZYNQMP_PM_RESET_SOFT,
  146. ZYNQMP_PM_RESET_GEM0,
  147. ZYNQMP_PM_RESET_GEM1,
  148. ZYNQMP_PM_RESET_GEM2,
  149. ZYNQMP_PM_RESET_GEM3,
  150. ZYNQMP_PM_RESET_QSPI,
  151. ZYNQMP_PM_RESET_UART0,
  152. ZYNQMP_PM_RESET_UART1,
  153. ZYNQMP_PM_RESET_SPI0,
  154. ZYNQMP_PM_RESET_SPI1,
  155. ZYNQMP_PM_RESET_SDIO0,
  156. ZYNQMP_PM_RESET_SDIO1,
  157. ZYNQMP_PM_RESET_CAN0,
  158. ZYNQMP_PM_RESET_CAN1,
  159. ZYNQMP_PM_RESET_I2C0,
  160. ZYNQMP_PM_RESET_I2C1,
  161. ZYNQMP_PM_RESET_TTC0,
  162. ZYNQMP_PM_RESET_TTC1,
  163. ZYNQMP_PM_RESET_TTC2,
  164. ZYNQMP_PM_RESET_TTC3,
  165. ZYNQMP_PM_RESET_SWDT_CRL,
  166. ZYNQMP_PM_RESET_NAND,
  167. ZYNQMP_PM_RESET_ADMA,
  168. ZYNQMP_PM_RESET_GPIO,
  169. ZYNQMP_PM_RESET_IOU_CC,
  170. ZYNQMP_PM_RESET_TIMESTAMP,
  171. ZYNQMP_PM_RESET_RPU_R50,
  172. ZYNQMP_PM_RESET_RPU_R51,
  173. ZYNQMP_PM_RESET_RPU_AMBA,
  174. ZYNQMP_PM_RESET_OCM,
  175. ZYNQMP_PM_RESET_RPU_PGE,
  176. ZYNQMP_PM_RESET_USB0_CORERESET,
  177. ZYNQMP_PM_RESET_USB1_CORERESET,
  178. ZYNQMP_PM_RESET_USB0_HIBERRESET,
  179. ZYNQMP_PM_RESET_USB1_HIBERRESET,
  180. ZYNQMP_PM_RESET_USB0_APB,
  181. ZYNQMP_PM_RESET_USB1_APB,
  182. ZYNQMP_PM_RESET_IPI,
  183. ZYNQMP_PM_RESET_APM_LPD,
  184. ZYNQMP_PM_RESET_RTC,
  185. ZYNQMP_PM_RESET_SYSMON,
  186. ZYNQMP_PM_RESET_AFI_FM6,
  187. ZYNQMP_PM_RESET_LPD_SWDT,
  188. ZYNQMP_PM_RESET_FPD,
  189. ZYNQMP_PM_RESET_RPU_DBG1,
  190. ZYNQMP_PM_RESET_RPU_DBG0,
  191. ZYNQMP_PM_RESET_DBG_LPD,
  192. ZYNQMP_PM_RESET_DBG_FPD,
  193. ZYNQMP_PM_RESET_APLL,
  194. ZYNQMP_PM_RESET_DPLL,
  195. ZYNQMP_PM_RESET_VPLL,
  196. ZYNQMP_PM_RESET_IOPLL,
  197. ZYNQMP_PM_RESET_RPLL,
  198. ZYNQMP_PM_RESET_GPO3_PL_0,
  199. ZYNQMP_PM_RESET_GPO3_PL_1,
  200. ZYNQMP_PM_RESET_GPO3_PL_2,
  201. ZYNQMP_PM_RESET_GPO3_PL_3,
  202. ZYNQMP_PM_RESET_GPO3_PL_4,
  203. ZYNQMP_PM_RESET_GPO3_PL_5,
  204. ZYNQMP_PM_RESET_GPO3_PL_6,
  205. ZYNQMP_PM_RESET_GPO3_PL_7,
  206. ZYNQMP_PM_RESET_GPO3_PL_8,
  207. ZYNQMP_PM_RESET_GPO3_PL_9,
  208. ZYNQMP_PM_RESET_GPO3_PL_10,
  209. ZYNQMP_PM_RESET_GPO3_PL_11,
  210. ZYNQMP_PM_RESET_GPO3_PL_12,
  211. ZYNQMP_PM_RESET_GPO3_PL_13,
  212. ZYNQMP_PM_RESET_GPO3_PL_14,
  213. ZYNQMP_PM_RESET_GPO3_PL_15,
  214. ZYNQMP_PM_RESET_GPO3_PL_16,
  215. ZYNQMP_PM_RESET_GPO3_PL_17,
  216. ZYNQMP_PM_RESET_GPO3_PL_18,
  217. ZYNQMP_PM_RESET_GPO3_PL_19,
  218. ZYNQMP_PM_RESET_GPO3_PL_20,
  219. ZYNQMP_PM_RESET_GPO3_PL_21,
  220. ZYNQMP_PM_RESET_GPO3_PL_22,
  221. ZYNQMP_PM_RESET_GPO3_PL_23,
  222. ZYNQMP_PM_RESET_GPO3_PL_24,
  223. ZYNQMP_PM_RESET_GPO3_PL_25,
  224. ZYNQMP_PM_RESET_GPO3_PL_26,
  225. ZYNQMP_PM_RESET_GPO3_PL_27,
  226. ZYNQMP_PM_RESET_GPO3_PL_28,
  227. ZYNQMP_PM_RESET_GPO3_PL_29,
  228. ZYNQMP_PM_RESET_GPO3_PL_30,
  229. ZYNQMP_PM_RESET_GPO3_PL_31,
  230. ZYNQMP_PM_RESET_RPU_LS,
  231. ZYNQMP_PM_RESET_PS_ONLY,
  232. ZYNQMP_PM_RESET_PL,
  233. ZYNQMP_PM_RESET_PS_PL0,
  234. ZYNQMP_PM_RESET_PS_PL1,
  235. ZYNQMP_PM_RESET_PS_PL2,
  236. ZYNQMP_PM_RESET_PS_PL3,
  237. ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
  238. };
  239. enum zynqmp_pm_suspend_reason {
  240. SUSPEND_POWER_REQUEST = 201,
  241. SUSPEND_ALERT,
  242. SUSPEND_SYSTEM_SHUTDOWN,
  243. };
  244. enum zynqmp_pm_request_ack {
  245. ZYNQMP_PM_REQUEST_ACK_NO = 1,
  246. ZYNQMP_PM_REQUEST_ACK_BLOCKING,
  247. ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING,
  248. };
  249. enum pm_node_id {
  250. NODE_SD_0 = 39,
  251. NODE_SD_1,
  252. };
  253. enum tap_delay_type {
  254. PM_TAPDELAY_INPUT = 0,
  255. PM_TAPDELAY_OUTPUT,
  256. };
  257. enum dll_reset_type {
  258. PM_DLL_RESET_ASSERT,
  259. PM_DLL_RESET_RELEASE,
  260. PM_DLL_RESET_PULSE,
  261. };
  262. enum zynqmp_pm_shutdown_type {
  263. ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN,
  264. ZYNQMP_PM_SHUTDOWN_TYPE_RESET,
  265. ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY,
  266. };
  267. enum zynqmp_pm_shutdown_subtype {
  268. ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM,
  269. ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY,
  270. ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM,
  271. };
  272. /**
  273. * struct zynqmp_pm_query_data - PM query data
  274. * @qid: query ID
  275. * @arg1: Argument 1 of query data
  276. * @arg2: Argument 2 of query data
  277. * @arg3: Argument 3 of query data
  278. */
  279. struct zynqmp_pm_query_data {
  280. u32 qid;
  281. u32 arg1;
  282. u32 arg2;
  283. u32 arg3;
  284. };
  285. int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
  286. u32 arg2, u32 arg3, u32 *ret_payload);
  287. #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
  288. int zynqmp_pm_get_api_version(u32 *version);
  289. int zynqmp_pm_get_chipid(u32 *idcode, u32 *version);
  290. int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
  291. int zynqmp_pm_clock_enable(u32 clock_id);
  292. int zynqmp_pm_clock_disable(u32 clock_id);
  293. int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
  294. int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
  295. int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider);
  296. int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate);
  297. int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate);
  298. int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id);
  299. int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id);
  300. int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode);
  301. int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode);
  302. int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data);
  303. int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data);
  304. int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value);
  305. int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type);
  306. int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
  307. const enum zynqmp_pm_reset_action assert_flag);
  308. int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status);
  309. int zynqmp_pm_init_finalize(void);
  310. int zynqmp_pm_set_suspend_mode(u32 mode);
  311. int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
  312. const u32 qos, const enum zynqmp_pm_request_ack ack);
  313. int zynqmp_pm_release_node(const u32 node);
  314. int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
  315. const u32 qos,
  316. const enum zynqmp_pm_request_ack ack);
  317. int zynqmp_pm_aes_engine(const u64 address, u32 *out);
  318. int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
  319. int zynqmp_pm_fpga_get_status(u32 *value);
  320. int zynqmp_pm_write_ggs(u32 index, u32 value);
  321. int zynqmp_pm_read_ggs(u32 index, u32 *value);
  322. int zynqmp_pm_write_pggs(u32 index, u32 value);
  323. int zynqmp_pm_read_pggs(u32 index, u32 *value);
  324. int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
  325. int zynqmp_pm_set_boot_health_status(u32 value);
  326. #else
  327. static inline int zynqmp_pm_get_api_version(u32 *version)
  328. {
  329. return -ENODEV;
  330. }
  331. static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
  332. {
  333. return -ENODEV;
  334. }
  335. static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,
  336. u32 *out)
  337. {
  338. return -ENODEV;
  339. }
  340. static inline int zynqmp_pm_clock_enable(u32 clock_id)
  341. {
  342. return -ENODEV;
  343. }
  344. static inline int zynqmp_pm_clock_disable(u32 clock_id)
  345. {
  346. return -ENODEV;
  347. }
  348. static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
  349. {
  350. return -ENODEV;
  351. }
  352. static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
  353. {
  354. return -ENODEV;
  355. }
  356. static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
  357. {
  358. return -ENODEV;
  359. }
  360. static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate)
  361. {
  362. return -ENODEV;
  363. }
  364. static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate)
  365. {
  366. return -ENODEV;
  367. }
  368. static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
  369. {
  370. return -ENODEV;
  371. }
  372. static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
  373. {
  374. return -ENODEV;
  375. }
  376. static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode)
  377. {
  378. return -ENODEV;
  379. }
  380. static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode)
  381. {
  382. return -ENODEV;
  383. }
  384. static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data)
  385. {
  386. return -ENODEV;
  387. }
  388. static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data)
  389. {
  390. return -ENODEV;
  391. }
  392. static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)
  393. {
  394. return -ENODEV;
  395. }
  396. static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
  397. {
  398. return -ENODEV;
  399. }
  400. static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
  401. const enum zynqmp_pm_reset_action assert_flag)
  402. {
  403. return -ENODEV;
  404. }
  405. static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,
  406. u32 *status)
  407. {
  408. return -ENODEV;
  409. }
  410. static inline int zynqmp_pm_init_finalize(void)
  411. {
  412. return -ENODEV;
  413. }
  414. static inline int zynqmp_pm_set_suspend_mode(u32 mode)
  415. {
  416. return -ENODEV;
  417. }
  418. static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
  419. const u32 qos,
  420. const enum zynqmp_pm_request_ack ack)
  421. {
  422. return -ENODEV;
  423. }
  424. static inline int zynqmp_pm_release_node(const u32 node)
  425. {
  426. return -ENODEV;
  427. }
  428. static inline int zynqmp_pm_set_requirement(const u32 node,
  429. const u32 capabilities,
  430. const u32 qos,
  431. const enum zynqmp_pm_request_ack ack)
  432. {
  433. return -ENODEV;
  434. }
  435. static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
  436. {
  437. return -ENODEV;
  438. }
  439. static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
  440. const u32 flags)
  441. {
  442. return -ENODEV;
  443. }
  444. static inline int zynqmp_pm_fpga_get_status(u32 *value)
  445. {
  446. return -ENODEV;
  447. }
  448. static inline int zynqmp_pm_write_ggs(u32 index, u32 value)
  449. {
  450. return -ENODEV;
  451. }
  452. static inline int zynqmp_pm_read_ggs(u32 index, u32 *value)
  453. {
  454. return -ENODEV;
  455. }
  456. static inline int zynqmp_pm_write_pggs(u32 index, u32 value)
  457. {
  458. return -ENODEV;
  459. }
  460. static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
  461. {
  462. return -ENODEV;
  463. }
  464. static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
  465. {
  466. return -ENODEV;
  467. }
  468. static inline int zynqmp_pm_set_boot_health_status(u32 value)
  469. {
  470. return -ENODEV;
  471. }
  472. #endif
  473. #endif /* __FIRMWARE_ZYNQMP_H__ */