edac.h 19 KB

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  1. /*
  2. * Generic EDAC defs
  3. *
  4. * Author: Dave Jiang <djiang@mvista.com>
  5. *
  6. * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
  7. * the terms of the GNU General Public License version 2. This program
  8. * is licensed "as is" without any warranty of any kind, whether express
  9. * or implied.
  10. *
  11. */
  12. #ifndef _LINUX_EDAC_H_
  13. #define _LINUX_EDAC_H_
  14. #include <linux/atomic.h>
  15. #include <linux/device.h>
  16. #include <linux/completion.h>
  17. #include <linux/workqueue.h>
  18. #include <linux/debugfs.h>
  19. #include <linux/numa.h>
  20. #define EDAC_DEVICE_NAME_LEN 31
  21. struct device;
  22. #define EDAC_OPSTATE_INVAL -1
  23. #define EDAC_OPSTATE_POLL 0
  24. #define EDAC_OPSTATE_NMI 1
  25. #define EDAC_OPSTATE_INT 2
  26. extern int edac_op_state;
  27. struct bus_type *edac_get_sysfs_subsys(void);
  28. static inline void opstate_init(void)
  29. {
  30. switch (edac_op_state) {
  31. case EDAC_OPSTATE_POLL:
  32. case EDAC_OPSTATE_NMI:
  33. break;
  34. default:
  35. edac_op_state = EDAC_OPSTATE_POLL;
  36. }
  37. return;
  38. }
  39. /* Max length of a DIMM label*/
  40. #define EDAC_MC_LABEL_LEN 31
  41. /* Maximum size of the location string */
  42. #define LOCATION_SIZE 256
  43. /* Defines the maximum number of labels that can be reported */
  44. #define EDAC_MAX_LABELS 8
  45. /* String used to join two or more labels */
  46. #define OTHER_LABEL " or "
  47. /**
  48. * enum dev_type - describe the type of memory DRAM chips used at the stick
  49. * @DEV_UNKNOWN: Can't be determined, or MC doesn't support detect it
  50. * @DEV_X1: 1 bit for data
  51. * @DEV_X2: 2 bits for data
  52. * @DEV_X4: 4 bits for data
  53. * @DEV_X8: 8 bits for data
  54. * @DEV_X16: 16 bits for data
  55. * @DEV_X32: 32 bits for data
  56. * @DEV_X64: 64 bits for data
  57. *
  58. * Typical values are x4 and x8.
  59. */
  60. enum dev_type {
  61. DEV_UNKNOWN = 0,
  62. DEV_X1,
  63. DEV_X2,
  64. DEV_X4,
  65. DEV_X8,
  66. DEV_X16,
  67. DEV_X32, /* Do these parts exist? */
  68. DEV_X64 /* Do these parts exist? */
  69. };
  70. #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
  71. #define DEV_FLAG_X1 BIT(DEV_X1)
  72. #define DEV_FLAG_X2 BIT(DEV_X2)
  73. #define DEV_FLAG_X4 BIT(DEV_X4)
  74. #define DEV_FLAG_X8 BIT(DEV_X8)
  75. #define DEV_FLAG_X16 BIT(DEV_X16)
  76. #define DEV_FLAG_X32 BIT(DEV_X32)
  77. #define DEV_FLAG_X64 BIT(DEV_X64)
  78. /**
  79. * enum hw_event_mc_err_type - type of the detected error
  80. *
  81. * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC
  82. * corrected error was detected
  83. * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that
  84. * can't be corrected by ECC, but it is not
  85. * fatal (maybe it is on an unused memory area,
  86. * or the memory controller could recover from
  87. * it for example, by re-trying the operation).
  88. * @HW_EVENT_ERR_DEFERRED: Deferred Error - Indicates an uncorrectable
  89. * error whose handling is not urgent. This could
  90. * be due to hardware data poisoning where the
  91. * system can continue operation until the poisoned
  92. * data is consumed. Preemptive measures may also
  93. * be taken, e.g. offlining pages, etc.
  94. * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not
  95. * be recovered.
  96. * @HW_EVENT_ERR_INFO: Informational - The CPER spec defines a forth
  97. * type of error: informational logs.
  98. */
  99. enum hw_event_mc_err_type {
  100. HW_EVENT_ERR_CORRECTED,
  101. HW_EVENT_ERR_UNCORRECTED,
  102. HW_EVENT_ERR_DEFERRED,
  103. HW_EVENT_ERR_FATAL,
  104. HW_EVENT_ERR_INFO,
  105. };
  106. static inline char *mc_event_error_type(const unsigned int err_type)
  107. {
  108. switch (err_type) {
  109. case HW_EVENT_ERR_CORRECTED:
  110. return "Corrected";
  111. case HW_EVENT_ERR_UNCORRECTED:
  112. return "Uncorrected";
  113. case HW_EVENT_ERR_DEFERRED:
  114. return "Deferred";
  115. case HW_EVENT_ERR_FATAL:
  116. return "Fatal";
  117. default:
  118. case HW_EVENT_ERR_INFO:
  119. return "Info";
  120. }
  121. }
  122. /**
  123. * enum mem_type - memory types. For a more detailed reference, please see
  124. * http://en.wikipedia.org/wiki/DRAM
  125. *
  126. * @MEM_EMPTY: Empty csrow
  127. * @MEM_RESERVED: Reserved csrow type
  128. * @MEM_UNKNOWN: Unknown csrow type
  129. * @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995.
  130. * @MEM_EDO: EDO - Extended data out, used on systems up to 1998.
  131. * @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant.
  132. * @MEM_SDR: SDR - Single data rate SDRAM
  133. * http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
  134. * They use 3 pins for chip select: Pins 0 and 2 are
  135. * for rank 0; pins 1 and 3 are for rank 1, if the memory
  136. * is dual-rank.
  137. * @MEM_RDR: Registered SDR SDRAM
  138. * @MEM_DDR: Double data rate SDRAM
  139. * http://en.wikipedia.org/wiki/DDR_SDRAM
  140. * @MEM_RDDR: Registered Double data rate SDRAM
  141. * This is a variant of the DDR memories.
  142. * A registered memory has a buffer inside it, hiding
  143. * part of the memory details to the memory controller.
  144. * @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers.
  145. * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F.
  146. * Those memories are labeled as "PC2-" instead of "PC" to
  147. * differentiate from DDR.
  148. * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205
  149. * and JESD206.
  150. * Those memories are accessed per DIMM slot, and not by
  151. * a chip select signal.
  152. * @MEM_RDDR2: Registered DDR2 RAM
  153. * This is a variant of the DDR2 memories.
  154. * @MEM_XDR: Rambus XDR
  155. * It is an evolution of the original RAMBUS memories,
  156. * created to compete with DDR2. Weren't used on any
  157. * x86 arch, but cell_edac PPC memory controller uses it.
  158. * @MEM_DDR3: DDR3 RAM
  159. * @MEM_RDDR3: Registered DDR3 RAM
  160. * This is a variant of the DDR3 memories.
  161. * @MEM_LRDDR3: Load-Reduced DDR3 memory.
  162. * @MEM_DDR4: Unbuffered DDR4 RAM
  163. * @MEM_RDDR4: Registered DDR4 RAM
  164. * This is a variant of the DDR4 memories.
  165. * @MEM_LRDDR4: Load-Reduced DDR4 memory.
  166. * @MEM_NVDIMM: Non-volatile RAM
  167. */
  168. enum mem_type {
  169. MEM_EMPTY = 0,
  170. MEM_RESERVED,
  171. MEM_UNKNOWN,
  172. MEM_FPM,
  173. MEM_EDO,
  174. MEM_BEDO,
  175. MEM_SDR,
  176. MEM_RDR,
  177. MEM_DDR,
  178. MEM_RDDR,
  179. MEM_RMBS,
  180. MEM_DDR2,
  181. MEM_FB_DDR2,
  182. MEM_RDDR2,
  183. MEM_XDR,
  184. MEM_DDR3,
  185. MEM_RDDR3,
  186. MEM_LRDDR3,
  187. MEM_DDR4,
  188. MEM_RDDR4,
  189. MEM_LRDDR4,
  190. MEM_NVDIMM,
  191. };
  192. #define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
  193. #define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
  194. #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
  195. #define MEM_FLAG_FPM BIT(MEM_FPM)
  196. #define MEM_FLAG_EDO BIT(MEM_EDO)
  197. #define MEM_FLAG_BEDO BIT(MEM_BEDO)
  198. #define MEM_FLAG_SDR BIT(MEM_SDR)
  199. #define MEM_FLAG_RDR BIT(MEM_RDR)
  200. #define MEM_FLAG_DDR BIT(MEM_DDR)
  201. #define MEM_FLAG_RDDR BIT(MEM_RDDR)
  202. #define MEM_FLAG_RMBS BIT(MEM_RMBS)
  203. #define MEM_FLAG_DDR2 BIT(MEM_DDR2)
  204. #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
  205. #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
  206. #define MEM_FLAG_XDR BIT(MEM_XDR)
  207. #define MEM_FLAG_DDR3 BIT(MEM_DDR3)
  208. #define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
  209. #define MEM_FLAG_DDR4 BIT(MEM_DDR4)
  210. #define MEM_FLAG_RDDR4 BIT(MEM_RDDR4)
  211. #define MEM_FLAG_LRDDR4 BIT(MEM_LRDDR4)
  212. #define MEM_FLAG_NVDIMM BIT(MEM_NVDIMM)
  213. /**
  214. * enum edac-type - Error Detection and Correction capabilities and mode
  215. * @EDAC_UNKNOWN: Unknown if ECC is available
  216. * @EDAC_NONE: Doesn't support ECC
  217. * @EDAC_RESERVED: Reserved ECC type
  218. * @EDAC_PARITY: Detects parity errors
  219. * @EDAC_EC: Error Checking - no correction
  220. * @EDAC_SECDED: Single bit error correction, Double detection
  221. * @EDAC_S2ECD2ED: Chipkill x2 devices - do these exist?
  222. * @EDAC_S4ECD4ED: Chipkill x4 devices
  223. * @EDAC_S8ECD8ED: Chipkill x8 devices
  224. * @EDAC_S16ECD16ED: Chipkill x16 devices
  225. */
  226. enum edac_type {
  227. EDAC_UNKNOWN = 0,
  228. EDAC_NONE,
  229. EDAC_RESERVED,
  230. EDAC_PARITY,
  231. EDAC_EC,
  232. EDAC_SECDED,
  233. EDAC_S2ECD2ED,
  234. EDAC_S4ECD4ED,
  235. EDAC_S8ECD8ED,
  236. EDAC_S16ECD16ED,
  237. };
  238. #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
  239. #define EDAC_FLAG_NONE BIT(EDAC_NONE)
  240. #define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
  241. #define EDAC_FLAG_EC BIT(EDAC_EC)
  242. #define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
  243. #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
  244. #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
  245. #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
  246. #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
  247. /**
  248. * enum scrub_type - scrubbing capabilities
  249. * @SCRUB_UNKNOWN: Unknown if scrubber is available
  250. * @SCRUB_NONE: No scrubber
  251. * @SCRUB_SW_PROG: SW progressive (sequential) scrubbing
  252. * @SCRUB_SW_SRC: Software scrub only errors
  253. * @SCRUB_SW_PROG_SRC: Progressive software scrub from an error
  254. * @SCRUB_SW_TUNABLE: Software scrub frequency is tunable
  255. * @SCRUB_HW_PROG: HW progressive (sequential) scrubbing
  256. * @SCRUB_HW_SRC: Hardware scrub only errors
  257. * @SCRUB_HW_PROG_SRC: Progressive hardware scrub from an error
  258. * @SCRUB_HW_TUNABLE: Hardware scrub frequency is tunable
  259. */
  260. enum scrub_type {
  261. SCRUB_UNKNOWN = 0,
  262. SCRUB_NONE,
  263. SCRUB_SW_PROG,
  264. SCRUB_SW_SRC,
  265. SCRUB_SW_PROG_SRC,
  266. SCRUB_SW_TUNABLE,
  267. SCRUB_HW_PROG,
  268. SCRUB_HW_SRC,
  269. SCRUB_HW_PROG_SRC,
  270. SCRUB_HW_TUNABLE
  271. };
  272. #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
  273. #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
  274. #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
  275. #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
  276. #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
  277. #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
  278. #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
  279. #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
  280. /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
  281. /* EDAC internal operation states */
  282. #define OP_ALLOC 0x100
  283. #define OP_RUNNING_POLL 0x201
  284. #define OP_RUNNING_INTERRUPT 0x202
  285. #define OP_RUNNING_POLL_INTR 0x203
  286. #define OP_OFFLINE 0x300
  287. /**
  288. * enum edac_mc_layer - memory controller hierarchy layer
  289. *
  290. * @EDAC_MC_LAYER_BRANCH: memory layer is named "branch"
  291. * @EDAC_MC_LAYER_CHANNEL: memory layer is named "channel"
  292. * @EDAC_MC_LAYER_SLOT: memory layer is named "slot"
  293. * @EDAC_MC_LAYER_CHIP_SELECT: memory layer is named "chip select"
  294. * @EDAC_MC_LAYER_ALL_MEM: memory layout is unknown. All memory is mapped
  295. * as a single memory area. This is used when
  296. * retrieving errors from a firmware driven driver.
  297. *
  298. * This enum is used by the drivers to tell edac_mc_sysfs what name should
  299. * be used when describing a memory stick location.
  300. */
  301. enum edac_mc_layer_type {
  302. EDAC_MC_LAYER_BRANCH,
  303. EDAC_MC_LAYER_CHANNEL,
  304. EDAC_MC_LAYER_SLOT,
  305. EDAC_MC_LAYER_CHIP_SELECT,
  306. EDAC_MC_LAYER_ALL_MEM,
  307. };
  308. /**
  309. * struct edac_mc_layer - describes the memory controller hierarchy
  310. * @type: layer type
  311. * @size: number of components per layer. For example,
  312. * if the channel layer has two channels, size = 2
  313. * @is_virt_csrow: This layer is part of the "csrow" when old API
  314. * compatibility mode is enabled. Otherwise, it is
  315. * a channel
  316. */
  317. struct edac_mc_layer {
  318. enum edac_mc_layer_type type;
  319. unsigned size;
  320. bool is_virt_csrow;
  321. };
  322. /*
  323. * Maximum number of layers used by the memory controller to uniquely
  324. * identify a single memory stick.
  325. * NOTE: Changing this constant requires not only to change the constant
  326. * below, but also to change the existing code at the core, as there are
  327. * some code there that are optimized for 3 layers.
  328. */
  329. #define EDAC_MAX_LAYERS 3
  330. struct dimm_info {
  331. struct device dev;
  332. char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
  333. /* Memory location data */
  334. unsigned int location[EDAC_MAX_LAYERS];
  335. struct mem_ctl_info *mci; /* the parent */
  336. unsigned int idx; /* index within the parent dimm array */
  337. u32 grain; /* granularity of reported error in bytes */
  338. enum dev_type dtype; /* memory device type */
  339. enum mem_type mtype; /* memory dimm type */
  340. enum edac_type edac_mode; /* EDAC mode for this dimm */
  341. u32 nr_pages; /* number of pages on this dimm */
  342. unsigned int csrow, cschannel; /* Points to the old API data */
  343. u16 smbios_handle; /* Handle for SMBIOS type 17 */
  344. u32 ce_count;
  345. u32 ue_count;
  346. };
  347. /**
  348. * struct rank_info - contains the information for one DIMM rank
  349. *
  350. * @chan_idx: channel number where the rank is (typically, 0 or 1)
  351. * @ce_count: number of correctable errors for this rank
  352. * @csrow: A pointer to the chip select row structure (the parent
  353. * structure). The location of the rank is given by
  354. * the (csrow->csrow_idx, chan_idx) vector.
  355. * @dimm: A pointer to the DIMM structure, where the DIMM label
  356. * information is stored.
  357. *
  358. * FIXME: Currently, the EDAC core model will assume one DIMM per rank.
  359. * This is a bad assumption, but it makes this patch easier. Later
  360. * patches in this series will fix this issue.
  361. */
  362. struct rank_info {
  363. int chan_idx;
  364. struct csrow_info *csrow;
  365. struct dimm_info *dimm;
  366. u32 ce_count; /* Correctable Errors for this csrow */
  367. };
  368. struct csrow_info {
  369. struct device dev;
  370. /* Used only by edac_mc_find_csrow_by_page() */
  371. unsigned long first_page; /* first page number in csrow */
  372. unsigned long last_page; /* last page number in csrow */
  373. unsigned long page_mask; /* used for interleaving -
  374. * 0UL for non intlv */
  375. int csrow_idx; /* the chip-select row */
  376. u32 ue_count; /* Uncorrectable Errors for this csrow */
  377. u32 ce_count; /* Correctable Errors for this csrow */
  378. struct mem_ctl_info *mci; /* the parent */
  379. /* channel information for this csrow */
  380. u32 nr_channels;
  381. struct rank_info **channels;
  382. };
  383. /*
  384. * struct errcount_attribute - used to store the several error counts
  385. */
  386. struct errcount_attribute_data {
  387. int n_layers;
  388. int pos[EDAC_MAX_LAYERS];
  389. int layer0, layer1, layer2;
  390. };
  391. /**
  392. * struct edac_raw_error_desc - Raw error report structure
  393. * @grain: minimum granularity for an error report, in bytes
  394. * @error_count: number of errors of the same type
  395. * @type: severity of the error (CE/UE/Fatal)
  396. * @top_layer: top layer of the error (layer[0])
  397. * @mid_layer: middle layer of the error (layer[1])
  398. * @low_layer: low layer of the error (layer[2])
  399. * @page_frame_number: page where the error happened
  400. * @offset_in_page: page offset
  401. * @syndrome: syndrome of the error (or 0 if unknown or if
  402. * the syndrome is not applicable)
  403. * @msg: error message
  404. * @location: location of the error
  405. * @label: label of the affected DIMM(s)
  406. * @other_detail: other driver-specific detail about the error
  407. */
  408. struct edac_raw_error_desc {
  409. char location[LOCATION_SIZE];
  410. char label[(EDAC_MC_LABEL_LEN + 1 + sizeof(OTHER_LABEL)) * EDAC_MAX_LABELS];
  411. long grain;
  412. u16 error_count;
  413. enum hw_event_mc_err_type type;
  414. int top_layer;
  415. int mid_layer;
  416. int low_layer;
  417. unsigned long page_frame_number;
  418. unsigned long offset_in_page;
  419. unsigned long syndrome;
  420. const char *msg;
  421. const char *other_detail;
  422. };
  423. /* MEMORY controller information structure
  424. */
  425. struct mem_ctl_info {
  426. struct device dev;
  427. struct bus_type *bus;
  428. struct list_head link; /* for global list of mem_ctl_info structs */
  429. struct module *owner; /* Module owner of this control struct */
  430. unsigned long mtype_cap; /* memory types supported by mc */
  431. unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
  432. unsigned long edac_cap; /* configuration capabilities - this is
  433. * closely related to edac_ctl_cap. The
  434. * difference is that the controller may be
  435. * capable of s4ecd4ed which would be listed
  436. * in edac_ctl_cap, but if channels aren't
  437. * capable of s4ecd4ed then the edac_cap would
  438. * not have that capability.
  439. */
  440. unsigned long scrub_cap; /* chipset scrub capabilities */
  441. enum scrub_type scrub_mode; /* current scrub mode */
  442. /* Translates sdram memory scrub rate given in bytes/sec to the
  443. internal representation and configures whatever else needs
  444. to be configured.
  445. */
  446. int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
  447. /* Get the current sdram memory scrub rate from the internal
  448. representation and converts it to the closest matching
  449. bandwidth in bytes/sec.
  450. */
  451. int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
  452. /* pointer to edac checking routine */
  453. void (*edac_check) (struct mem_ctl_info * mci);
  454. /*
  455. * Remaps memory pages: controller pages to physical pages.
  456. * For most MC's, this will be NULL.
  457. */
  458. /* FIXME - why not send the phys page to begin with? */
  459. unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
  460. unsigned long page);
  461. int mc_idx;
  462. struct csrow_info **csrows;
  463. unsigned int nr_csrows, num_cschannel;
  464. /*
  465. * Memory Controller hierarchy
  466. *
  467. * There are basically two types of memory controller: the ones that
  468. * sees memory sticks ("dimms"), and the ones that sees memory ranks.
  469. * All old memory controllers enumerate memories per rank, but most
  470. * of the recent drivers enumerate memories per DIMM, instead.
  471. * When the memory controller is per rank, csbased is true.
  472. */
  473. unsigned int n_layers;
  474. struct edac_mc_layer *layers;
  475. bool csbased;
  476. /*
  477. * DIMM info. Will eventually remove the entire csrows_info some day
  478. */
  479. unsigned int tot_dimms;
  480. struct dimm_info **dimms;
  481. /*
  482. * FIXME - what about controllers on other busses? - IDs must be
  483. * unique. dev pointer should be sufficiently unique, but
  484. * BUS:SLOT.FUNC numbers may not be unique.
  485. */
  486. struct device *pdev;
  487. const char *mod_name;
  488. const char *ctl_name;
  489. const char *dev_name;
  490. void *pvt_info;
  491. unsigned long start_time; /* mci load start time (in jiffies) */
  492. /*
  493. * drivers shouldn't access those fields directly, as the core
  494. * already handles that.
  495. */
  496. u32 ce_noinfo_count, ue_noinfo_count;
  497. u32 ue_mc, ce_mc;
  498. struct completion complete;
  499. /* Additional top controller level attributes, but specified
  500. * by the low level driver.
  501. *
  502. * Set by the low level driver to provide attributes at the
  503. * controller level.
  504. * An array of structures, NULL terminated
  505. *
  506. * If attributes are desired, then set to array of attributes
  507. * If no attributes are desired, leave NULL
  508. */
  509. const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
  510. /* work struct for this MC */
  511. struct delayed_work work;
  512. /*
  513. * Used to report an error - by being at the global struct
  514. * makes the memory allocated by the EDAC core
  515. */
  516. struct edac_raw_error_desc error_desc;
  517. /* the internal state of this controller instance */
  518. int op_state;
  519. struct dentry *debugfs;
  520. u8 fake_inject_layer[EDAC_MAX_LAYERS];
  521. bool fake_inject_ue;
  522. u16 fake_inject_count;
  523. };
  524. #define mci_for_each_dimm(mci, dimm) \
  525. for ((dimm) = (mci)->dimms[0]; \
  526. (dimm); \
  527. (dimm) = (dimm)->idx + 1 < (mci)->tot_dimms \
  528. ? (mci)->dimms[(dimm)->idx + 1] \
  529. : NULL)
  530. /**
  531. * edac_get_dimm - Get DIMM info from a memory controller given by
  532. * [layer0,layer1,layer2] position
  533. *
  534. * @mci: MC descriptor struct mem_ctl_info
  535. * @layer0: layer0 position
  536. * @layer1: layer1 position. Unused if n_layers < 2
  537. * @layer2: layer2 position. Unused if n_layers < 3
  538. *
  539. * For 1 layer, this function returns "dimms[layer0]";
  540. *
  541. * For 2 layers, this function is similar to allocating a two-dimensional
  542. * array and returning "dimms[layer0][layer1]";
  543. *
  544. * For 3 layers, this function is similar to allocating a tri-dimensional
  545. * array and returning "dimms[layer0][layer1][layer2]";
  546. */
  547. static inline struct dimm_info *edac_get_dimm(struct mem_ctl_info *mci,
  548. int layer0, int layer1, int layer2)
  549. {
  550. int index;
  551. if (layer0 < 0
  552. || (mci->n_layers > 1 && layer1 < 0)
  553. || (mci->n_layers > 2 && layer2 < 0))
  554. return NULL;
  555. index = layer0;
  556. if (mci->n_layers > 1)
  557. index = index * mci->layers[1].size + layer1;
  558. if (mci->n_layers > 2)
  559. index = index * mci->layers[2].size + layer2;
  560. if (index < 0 || index >= mci->tot_dimms)
  561. return NULL;
  562. if (WARN_ON_ONCE(mci->dimms[index]->idx != index))
  563. return NULL;
  564. return mci->dimms[index];
  565. }
  566. #endif /* _LINUX_EDAC_H_ */