dmaengine.h 53 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
  4. */
  5. #ifndef LINUX_DMAENGINE_H
  6. #define LINUX_DMAENGINE_H
  7. #include <linux/device.h>
  8. #include <linux/err.h>
  9. #include <linux/uio.h>
  10. #include <linux/bug.h>
  11. #include <linux/scatterlist.h>
  12. #include <linux/bitmap.h>
  13. #include <linux/types.h>
  14. #include <linux/android_kabi.h>
  15. #include <asm/page.h>
  16. /**
  17. * typedef dma_cookie_t - an opaque DMA cookie
  18. *
  19. * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
  20. */
  21. typedef s32 dma_cookie_t;
  22. #define DMA_MIN_COOKIE 1
  23. static inline int dma_submit_error(dma_cookie_t cookie)
  24. {
  25. return cookie < 0 ? cookie : 0;
  26. }
  27. /**
  28. * enum dma_status - DMA transaction status
  29. * @DMA_COMPLETE: transaction completed
  30. * @DMA_IN_PROGRESS: transaction not yet processed
  31. * @DMA_PAUSED: transaction is paused
  32. * @DMA_ERROR: transaction failed
  33. */
  34. enum dma_status {
  35. DMA_COMPLETE,
  36. DMA_IN_PROGRESS,
  37. DMA_PAUSED,
  38. DMA_ERROR,
  39. DMA_OUT_OF_ORDER,
  40. };
  41. /**
  42. * enum dma_transaction_type - DMA transaction types/indexes
  43. *
  44. * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
  45. * automatically set as dma devices are registered.
  46. */
  47. enum dma_transaction_type {
  48. DMA_MEMCPY,
  49. DMA_XOR,
  50. DMA_PQ,
  51. DMA_XOR_VAL,
  52. DMA_PQ_VAL,
  53. DMA_MEMSET,
  54. DMA_MEMSET_SG,
  55. DMA_INTERRUPT,
  56. DMA_PRIVATE,
  57. DMA_ASYNC_TX,
  58. DMA_SLAVE,
  59. DMA_CYCLIC,
  60. DMA_INTERLEAVE,
  61. DMA_COMPLETION_NO_ORDER,
  62. DMA_REPEAT,
  63. DMA_LOAD_EOT,
  64. /* last transaction type for creation of the capabilities mask */
  65. DMA_TX_TYPE_END,
  66. };
  67. /**
  68. * enum dma_transfer_direction - dma transfer mode and direction indicator
  69. * @DMA_MEM_TO_MEM: Async/Memcpy mode
  70. * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
  71. * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
  72. * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
  73. */
  74. enum dma_transfer_direction {
  75. DMA_MEM_TO_MEM,
  76. DMA_MEM_TO_DEV,
  77. DMA_DEV_TO_MEM,
  78. DMA_DEV_TO_DEV,
  79. DMA_TRANS_NONE,
  80. };
  81. /**
  82. * Interleaved Transfer Request
  83. * ----------------------------
  84. * A chunk is collection of contiguous bytes to be transferred.
  85. * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
  86. * ICGs may or may not change between chunks.
  87. * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
  88. * that when repeated an integral number of times, specifies the transfer.
  89. * A transfer template is specification of a Frame, the number of times
  90. * it is to be repeated and other per-transfer attributes.
  91. *
  92. * Practically, a client driver would have ready a template for each
  93. * type of transfer it is going to need during its lifetime and
  94. * set only 'src_start' and 'dst_start' before submitting the requests.
  95. *
  96. *
  97. * | Frame-1 | Frame-2 | ~ | Frame-'numf' |
  98. * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
  99. *
  100. * == Chunk size
  101. * ... ICG
  102. */
  103. /**
  104. * struct data_chunk - Element of scatter-gather list that makes a frame.
  105. * @size: Number of bytes to read from source.
  106. * size_dst := fn(op, size_src), so doesn't mean much for destination.
  107. * @icg: Number of bytes to jump after last src/dst address of this
  108. * chunk and before first src/dst address for next chunk.
  109. * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
  110. * Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
  111. * @dst_icg: Number of bytes to jump after last dst address of this
  112. * chunk and before the first dst address for next chunk.
  113. * Ignored if dst_inc is true and dst_sgl is false.
  114. * @src_icg: Number of bytes to jump after last src address of this
  115. * chunk and before the first src address for next chunk.
  116. * Ignored if src_inc is true and src_sgl is false.
  117. */
  118. struct data_chunk {
  119. size_t size;
  120. size_t icg;
  121. size_t dst_icg;
  122. size_t src_icg;
  123. };
  124. /**
  125. * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
  126. * and attributes.
  127. * @src_start: Bus address of source for the first chunk.
  128. * @dst_start: Bus address of destination for the first chunk.
  129. * @dir: Specifies the type of Source and Destination.
  130. * @src_inc: If the source address increments after reading from it.
  131. * @dst_inc: If the destination address increments after writing to it.
  132. * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
  133. * Otherwise, source is read contiguously (icg ignored).
  134. * Ignored if src_inc is false.
  135. * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
  136. * Otherwise, destination is filled contiguously (icg ignored).
  137. * Ignored if dst_inc is false.
  138. * @numf: Number of frames in this template.
  139. * @frame_size: Number of chunks in a frame i.e, size of sgl[].
  140. * @sgl: Array of {chunk,icg} pairs that make up a frame.
  141. */
  142. struct dma_interleaved_template {
  143. dma_addr_t src_start;
  144. dma_addr_t dst_start;
  145. enum dma_transfer_direction dir;
  146. bool src_inc;
  147. bool dst_inc;
  148. bool src_sgl;
  149. bool dst_sgl;
  150. size_t numf;
  151. size_t frame_size;
  152. struct data_chunk sgl[];
  153. };
  154. /**
  155. * enum dma_ctrl_flags - DMA flags to augment operation preparation,
  156. * control completion, and communicate status.
  157. * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
  158. * this transaction
  159. * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
  160. * acknowledges receipt, i.e. has a chance to establish any dependency
  161. * chains
  162. * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
  163. * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
  164. * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
  165. * sources that were the result of a previous operation, in the case of a PQ
  166. * operation it continues the calculation with new sources
  167. * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
  168. * on the result of this operation
  169. * @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till
  170. * cleared or freed
  171. * @DMA_PREP_CMD: tell the driver that the data passed to DMA API is command
  172. * data and the descriptor should be in different format from normal
  173. * data descriptors.
  174. * @DMA_PREP_REPEAT: tell the driver that the transaction shall be automatically
  175. * repeated when it ends until a transaction is issued on the same channel
  176. * with the DMA_PREP_LOAD_EOT flag set. This flag is only applicable to
  177. * interleaved transactions and is ignored for all other transaction types.
  178. * @DMA_PREP_LOAD_EOT: tell the driver that the transaction shall replace any
  179. * active repeated (as indicated by DMA_PREP_REPEAT) transaction when the
  180. * repeated transaction ends. Not setting this flag when the previously queued
  181. * transaction is marked with DMA_PREP_REPEAT will cause the new transaction
  182. * to never be processed and stay in the issued queue forever. The flag is
  183. * ignored if the previous transaction is not a repeated transaction.
  184. */
  185. enum dma_ctrl_flags {
  186. DMA_PREP_INTERRUPT = (1 << 0),
  187. DMA_CTRL_ACK = (1 << 1),
  188. DMA_PREP_PQ_DISABLE_P = (1 << 2),
  189. DMA_PREP_PQ_DISABLE_Q = (1 << 3),
  190. DMA_PREP_CONTINUE = (1 << 4),
  191. DMA_PREP_FENCE = (1 << 5),
  192. DMA_CTRL_REUSE = (1 << 6),
  193. DMA_PREP_CMD = (1 << 7),
  194. DMA_PREP_REPEAT = (1 << 8),
  195. DMA_PREP_LOAD_EOT = (1 << 9),
  196. };
  197. /**
  198. * enum sum_check_bits - bit position of pq_check_flags
  199. */
  200. enum sum_check_bits {
  201. SUM_CHECK_P = 0,
  202. SUM_CHECK_Q = 1,
  203. };
  204. /**
  205. * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
  206. * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
  207. * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
  208. */
  209. enum sum_check_flags {
  210. SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
  211. SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
  212. };
  213. /**
  214. * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
  215. * See linux/cpumask.h
  216. */
  217. typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
  218. /**
  219. * struct dma_chan_percpu - the per-CPU part of struct dma_chan
  220. * @memcpy_count: transaction counter
  221. * @bytes_transferred: byte counter
  222. */
  223. /**
  224. * enum dma_desc_metadata_mode - per descriptor metadata mode types supported
  225. * @DESC_METADATA_CLIENT - the metadata buffer is allocated/provided by the
  226. * client driver and it is attached (via the dmaengine_desc_attach_metadata()
  227. * helper) to the descriptor.
  228. *
  229. * Client drivers interested to use this mode can follow:
  230. * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
  231. * 1. prepare the descriptor (dmaengine_prep_*)
  232. * construct the metadata in the client's buffer
  233. * 2. use dmaengine_desc_attach_metadata() to attach the buffer to the
  234. * descriptor
  235. * 3. submit the transfer
  236. * - DMA_DEV_TO_MEM:
  237. * 1. prepare the descriptor (dmaengine_prep_*)
  238. * 2. use dmaengine_desc_attach_metadata() to attach the buffer to the
  239. * descriptor
  240. * 3. submit the transfer
  241. * 4. when the transfer is completed, the metadata should be available in the
  242. * attached buffer
  243. *
  244. * @DESC_METADATA_ENGINE - the metadata buffer is allocated/managed by the DMA
  245. * driver. The client driver can ask for the pointer, maximum size and the
  246. * currently used size of the metadata and can directly update or read it.
  247. * dmaengine_desc_get_metadata_ptr() and dmaengine_desc_set_metadata_len() is
  248. * provided as helper functions.
  249. *
  250. * Note: the metadata area for the descriptor is no longer valid after the
  251. * transfer has been completed (valid up to the point when the completion
  252. * callback returns if used).
  253. *
  254. * Client drivers interested to use this mode can follow:
  255. * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
  256. * 1. prepare the descriptor (dmaengine_prep_*)
  257. * 2. use dmaengine_desc_get_metadata_ptr() to get the pointer to the engine's
  258. * metadata area
  259. * 3. update the metadata at the pointer
  260. * 4. use dmaengine_desc_set_metadata_len() to tell the DMA engine the amount
  261. * of data the client has placed into the metadata buffer
  262. * 5. submit the transfer
  263. * - DMA_DEV_TO_MEM:
  264. * 1. prepare the descriptor (dmaengine_prep_*)
  265. * 2. submit the transfer
  266. * 3. on transfer completion, use dmaengine_desc_get_metadata_ptr() to get the
  267. * pointer to the engine's metadata area
  268. * 4. Read out the metadata from the pointer
  269. *
  270. * Note: the two mode is not compatible and clients must use one mode for a
  271. * descriptor.
  272. */
  273. enum dma_desc_metadata_mode {
  274. DESC_METADATA_NONE = 0,
  275. DESC_METADATA_CLIENT = BIT(0),
  276. DESC_METADATA_ENGINE = BIT(1),
  277. };
  278. struct dma_chan_percpu {
  279. /* stats */
  280. unsigned long memcpy_count;
  281. unsigned long bytes_transferred;
  282. };
  283. /**
  284. * struct dma_router - DMA router structure
  285. * @dev: pointer to the DMA router device
  286. * @route_free: function to be called when the route can be disconnected
  287. */
  288. struct dma_router {
  289. struct device *dev;
  290. void (*route_free)(struct device *dev, void *route_data);
  291. };
  292. /**
  293. * struct dma_chan - devices supply DMA channels, clients use them
  294. * @device: ptr to the dma device who supplies this channel, always !%NULL
  295. * @slave: ptr to the device using this channel
  296. * @cookie: last cookie value returned to client
  297. * @completed_cookie: last completed cookie for this channel
  298. * @chan_id: channel ID for sysfs
  299. * @dev: class device for sysfs
  300. * @name: backlink name for sysfs
  301. * @dbg_client_name: slave name for debugfs in format:
  302. * dev_name(requester's dev):channel name, for example: "2b00000.mcasp:tx"
  303. * @device_node: used to add this to the device chan list
  304. * @local: per-cpu pointer to a struct dma_chan_percpu
  305. * @client_count: how many clients are using this channel
  306. * @table_count: number of appearances in the mem-to-mem allocation table
  307. * @router: pointer to the DMA router structure
  308. * @route_data: channel specific data for the router
  309. * @private: private data for certain client-channel associations
  310. */
  311. struct dma_chan {
  312. struct dma_device *device;
  313. struct device *slave;
  314. dma_cookie_t cookie;
  315. dma_cookie_t completed_cookie;
  316. /* sysfs */
  317. int chan_id;
  318. struct dma_chan_dev *dev;
  319. const char *name;
  320. #ifdef CONFIG_DEBUG_FS
  321. char *dbg_client_name;
  322. #endif
  323. struct list_head device_node;
  324. struct dma_chan_percpu __percpu *local;
  325. int client_count;
  326. int table_count;
  327. /* DMA router */
  328. struct dma_router *router;
  329. void *route_data;
  330. void *private;
  331. };
  332. /**
  333. * struct dma_chan_dev - relate sysfs device node to backing channel device
  334. * @chan: driver channel device
  335. * @device: sysfs device
  336. * @dev_id: parent dma_device dev_id
  337. */
  338. struct dma_chan_dev {
  339. struct dma_chan *chan;
  340. struct device device;
  341. int dev_id;
  342. };
  343. /**
  344. * enum dma_slave_buswidth - defines bus width of the DMA slave
  345. * device, source or target buses
  346. */
  347. enum dma_slave_buswidth {
  348. DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
  349. DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
  350. DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
  351. DMA_SLAVE_BUSWIDTH_3_BYTES = 3,
  352. DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
  353. DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
  354. DMA_SLAVE_BUSWIDTH_16_BYTES = 16,
  355. DMA_SLAVE_BUSWIDTH_32_BYTES = 32,
  356. DMA_SLAVE_BUSWIDTH_64_BYTES = 64,
  357. };
  358. /**
  359. * struct dma_slave_config - dma slave channel runtime config
  360. * @direction: whether the data shall go in or out on this slave
  361. * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
  362. * legal values. DEPRECATED, drivers should use the direction argument
  363. * to the device_prep_slave_sg and device_prep_dma_cyclic functions or
  364. * the dir field in the dma_interleaved_template structure.
  365. * @src_addr: this is the physical address where DMA slave data
  366. * should be read (RX), if the source is memory this argument is
  367. * ignored.
  368. * @dst_addr: this is the physical address where DMA slave data
  369. * should be written (TX), if the source is memory this argument
  370. * is ignored.
  371. * @src_addr_width: this is the width in bytes of the source (RX)
  372. * register where DMA data shall be read. If the source
  373. * is memory this may be ignored depending on architecture.
  374. * Legal values: 1, 2, 3, 4, 8, 16, 32, 64.
  375. * @dst_addr_width: same as src_addr_width but for destination
  376. * target (TX) mutatis mutandis.
  377. * @src_maxburst: the maximum number of words (note: words, as in
  378. * units of the src_addr_width member, not bytes) that can be sent
  379. * in one burst to the device. Typically something like half the
  380. * FIFO depth on I/O peripherals so you don't overflow it. This
  381. * may or may not be applicable on memory sources.
  382. * @dst_maxburst: same as src_maxburst but for destination target
  383. * mutatis mutandis.
  384. * @src_port_window_size: The length of the register area in words the data need
  385. * to be accessed on the device side. It is only used for devices which is using
  386. * an area instead of a single register to receive the data. Typically the DMA
  387. * loops in this area in order to transfer the data.
  388. * @dst_port_window_size: same as src_port_window_size but for the destination
  389. * port.
  390. * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
  391. * with 'true' if peripheral should be flow controller. Direction will be
  392. * selected at Runtime.
  393. * @slave_id: Slave requester id. Only valid for slave channels. The dma
  394. * slave peripheral will have unique id as dma requester which need to be
  395. * pass as slave config.
  396. * @peripheral_config: peripheral configuration for programming peripheral
  397. * for dmaengine transfer
  398. * @peripheral_size: peripheral configuration buffer size
  399. *
  400. * This struct is passed in as configuration data to a DMA engine
  401. * in order to set up a certain channel for DMA transport at runtime.
  402. * The DMA device/engine has to provide support for an additional
  403. * callback in the dma_device structure, device_config and this struct
  404. * will then be passed in as an argument to the function.
  405. *
  406. * The rationale for adding configuration information to this struct is as
  407. * follows: if it is likely that more than one DMA slave controllers in
  408. * the world will support the configuration option, then make it generic.
  409. * If not: if it is fixed so that it be sent in static from the platform
  410. * data, then prefer to do that.
  411. */
  412. struct dma_slave_config {
  413. enum dma_transfer_direction direction;
  414. phys_addr_t src_addr;
  415. phys_addr_t dst_addr;
  416. enum dma_slave_buswidth src_addr_width;
  417. enum dma_slave_buswidth dst_addr_width;
  418. u32 src_maxburst;
  419. u32 dst_maxburst;
  420. u32 src_port_window_size;
  421. u32 dst_port_window_size;
  422. bool device_fc;
  423. unsigned int slave_id;
  424. void *peripheral_config;
  425. size_t peripheral_size;
  426. };
  427. /**
  428. * enum dma_residue_granularity - Granularity of the reported transfer residue
  429. * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
  430. * DMA channel is only able to tell whether a descriptor has been completed or
  431. * not, which means residue reporting is not supported by this channel. The
  432. * residue field of the dma_tx_state field will always be 0.
  433. * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
  434. * completed segment of the transfer (For cyclic transfers this is after each
  435. * period). This is typically implemented by having the hardware generate an
  436. * interrupt after each transferred segment and then the drivers updates the
  437. * outstanding residue by the size of the segment. Another possibility is if
  438. * the hardware supports scatter-gather and the segment descriptor has a field
  439. * which gets set after the segment has been completed. The driver then counts
  440. * the number of segments without the flag set to compute the residue.
  441. * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
  442. * burst. This is typically only supported if the hardware has a progress
  443. * register of some sort (E.g. a register with the current read/write address
  444. * or a register with the amount of bursts/beats/bytes that have been
  445. * transferred or still need to be transferred).
  446. */
  447. enum dma_residue_granularity {
  448. DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,
  449. DMA_RESIDUE_GRANULARITY_SEGMENT = 1,
  450. DMA_RESIDUE_GRANULARITY_BURST = 2,
  451. };
  452. /**
  453. * struct dma_slave_caps - expose capabilities of a slave channel only
  454. * @src_addr_widths: bit mask of src addr widths the channel supports.
  455. * Width is specified in bytes, e.g. for a channel supporting
  456. * a width of 4 the mask should have BIT(4) set.
  457. * @dst_addr_widths: bit mask of dst addr widths the channel supports
  458. * @directions: bit mask of slave directions the channel supports.
  459. * Since the enum dma_transfer_direction is not defined as bit flag for
  460. * each type, the dma controller should set BIT(<TYPE>) and same
  461. * should be checked by controller as well
  462. * @min_burst: min burst capability per-transfer
  463. * @max_burst: max burst capability per-transfer
  464. * @max_sg_burst: max number of SG list entries executed in a single burst
  465. * DMA tansaction with no software intervention for reinitialization.
  466. * Zero value means unlimited number of entries.
  467. * @cmd_pause: true, if pause is supported (i.e. for reading residue or
  468. * for resume later)
  469. * @cmd_resume: true, if resume is supported
  470. * @cmd_terminate: true, if terminate cmd is supported
  471. * @residue_granularity: granularity of the reported transfer residue
  472. * @descriptor_reuse: if a descriptor can be reused by client and
  473. * resubmitted multiple times
  474. */
  475. struct dma_slave_caps {
  476. u32 src_addr_widths;
  477. u32 dst_addr_widths;
  478. u32 directions;
  479. u32 min_burst;
  480. u32 max_burst;
  481. u32 max_sg_burst;
  482. bool cmd_pause;
  483. bool cmd_resume;
  484. bool cmd_terminate;
  485. enum dma_residue_granularity residue_granularity;
  486. bool descriptor_reuse;
  487. };
  488. static inline const char *dma_chan_name(struct dma_chan *chan)
  489. {
  490. return dev_name(&chan->dev->device);
  491. }
  492. void dma_chan_cleanup(struct kref *kref);
  493. /**
  494. * typedef dma_filter_fn - callback filter for dma_request_channel
  495. * @chan: channel to be reviewed
  496. * @filter_param: opaque parameter passed through dma_request_channel
  497. *
  498. * When this optional parameter is specified in a call to dma_request_channel a
  499. * suitable channel is passed to this routine for further dispositioning before
  500. * being returned. Where 'suitable' indicates a non-busy channel that
  501. * satisfies the given capability mask. It returns 'true' to indicate that the
  502. * channel is suitable.
  503. */
  504. typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
  505. typedef void (*dma_async_tx_callback)(void *dma_async_param);
  506. enum dmaengine_tx_result {
  507. DMA_TRANS_NOERROR = 0, /* SUCCESS */
  508. DMA_TRANS_READ_FAILED, /* Source DMA read failed */
  509. DMA_TRANS_WRITE_FAILED, /* Destination DMA write failed */
  510. DMA_TRANS_ABORTED, /* Op never submitted / aborted */
  511. };
  512. struct dmaengine_result {
  513. enum dmaengine_tx_result result;
  514. u32 residue;
  515. };
  516. typedef void (*dma_async_tx_callback_result)(void *dma_async_param,
  517. const struct dmaengine_result *result);
  518. struct dmaengine_unmap_data {
  519. #if IS_ENABLED(CONFIG_DMA_ENGINE_RAID)
  520. u16 map_cnt;
  521. #else
  522. u8 map_cnt;
  523. #endif
  524. u8 to_cnt;
  525. u8 from_cnt;
  526. u8 bidi_cnt;
  527. struct device *dev;
  528. struct kref kref;
  529. size_t len;
  530. dma_addr_t addr[];
  531. };
  532. struct dma_async_tx_descriptor;
  533. struct dma_descriptor_metadata_ops {
  534. int (*attach)(struct dma_async_tx_descriptor *desc, void *data,
  535. size_t len);
  536. void *(*get_ptr)(struct dma_async_tx_descriptor *desc,
  537. size_t *payload_len, size_t *max_len);
  538. int (*set_len)(struct dma_async_tx_descriptor *desc,
  539. size_t payload_len);
  540. };
  541. /**
  542. * struct dma_async_tx_descriptor - async transaction descriptor
  543. * ---dma generic offload fields---
  544. * @cookie: tracking cookie for this transaction, set to -EBUSY if
  545. * this tx is sitting on a dependency list
  546. * @flags: flags to augment operation preparation, control completion, and
  547. * communicate status
  548. * @phys: physical address of the descriptor
  549. * @chan: target channel for this operation
  550. * @tx_submit: accept the descriptor, assign ordered cookie and mark the
  551. * descriptor pending. To be pushed on .issue_pending() call
  552. * @callback: routine to call after this operation is complete
  553. * @callback_param: general parameter to pass to the callback routine
  554. * @desc_metadata_mode: core managed metadata mode to protect mixed use of
  555. * DESC_METADATA_CLIENT or DESC_METADATA_ENGINE. Otherwise
  556. * DESC_METADATA_NONE
  557. * @metadata_ops: DMA driver provided metadata mode ops, need to be set by the
  558. * DMA driver if metadata mode is supported with the descriptor
  559. * ---async_tx api specific fields---
  560. * @next: at completion submit this descriptor
  561. * @parent: pointer to the next level up in the dependency chain
  562. * @lock: protect the parent and next pointers
  563. */
  564. struct dma_async_tx_descriptor {
  565. dma_cookie_t cookie;
  566. enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
  567. dma_addr_t phys;
  568. struct dma_chan *chan;
  569. dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
  570. int (*desc_free)(struct dma_async_tx_descriptor *tx);
  571. dma_async_tx_callback callback;
  572. dma_async_tx_callback_result callback_result;
  573. void *callback_param;
  574. struct dmaengine_unmap_data *unmap;
  575. enum dma_desc_metadata_mode desc_metadata_mode;
  576. struct dma_descriptor_metadata_ops *metadata_ops;
  577. #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
  578. struct dma_async_tx_descriptor *next;
  579. struct dma_async_tx_descriptor *parent;
  580. spinlock_t lock;
  581. #endif
  582. };
  583. #ifdef CONFIG_DMA_ENGINE
  584. static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
  585. struct dmaengine_unmap_data *unmap)
  586. {
  587. kref_get(&unmap->kref);
  588. tx->unmap = unmap;
  589. }
  590. struct dmaengine_unmap_data *
  591. dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags);
  592. void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap);
  593. #else
  594. static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
  595. struct dmaengine_unmap_data *unmap)
  596. {
  597. }
  598. static inline struct dmaengine_unmap_data *
  599. dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
  600. {
  601. return NULL;
  602. }
  603. static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
  604. {
  605. }
  606. #endif
  607. static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx)
  608. {
  609. if (!tx->unmap)
  610. return;
  611. dmaengine_unmap_put(tx->unmap);
  612. tx->unmap = NULL;
  613. }
  614. #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
  615. static inline void txd_lock(struct dma_async_tx_descriptor *txd)
  616. {
  617. }
  618. static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
  619. {
  620. }
  621. static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
  622. {
  623. BUG();
  624. }
  625. static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
  626. {
  627. }
  628. static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
  629. {
  630. }
  631. static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
  632. {
  633. return NULL;
  634. }
  635. static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
  636. {
  637. return NULL;
  638. }
  639. #else
  640. static inline void txd_lock(struct dma_async_tx_descriptor *txd)
  641. {
  642. spin_lock_bh(&txd->lock);
  643. }
  644. static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
  645. {
  646. spin_unlock_bh(&txd->lock);
  647. }
  648. static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
  649. {
  650. txd->next = next;
  651. next->parent = txd;
  652. }
  653. static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
  654. {
  655. txd->parent = NULL;
  656. }
  657. static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
  658. {
  659. txd->next = NULL;
  660. }
  661. static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
  662. {
  663. return txd->parent;
  664. }
  665. static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
  666. {
  667. return txd->next;
  668. }
  669. #endif
  670. /**
  671. * struct dma_tx_state - filled in to report the status of
  672. * a transfer.
  673. * @last: last completed DMA cookie
  674. * @used: last issued DMA cookie (i.e. the one in progress)
  675. * @residue: the remaining number of bytes left to transmit
  676. * on the selected transfer for states DMA_IN_PROGRESS and
  677. * DMA_PAUSED if this is implemented in the driver, else 0
  678. * @in_flight_bytes: amount of data in bytes cached by the DMA.
  679. */
  680. struct dma_tx_state {
  681. dma_cookie_t last;
  682. dma_cookie_t used;
  683. u32 residue;
  684. u32 in_flight_bytes;
  685. };
  686. /**
  687. * enum dmaengine_alignment - defines alignment of the DMA async tx
  688. * buffers
  689. */
  690. enum dmaengine_alignment {
  691. DMAENGINE_ALIGN_1_BYTE = 0,
  692. DMAENGINE_ALIGN_2_BYTES = 1,
  693. DMAENGINE_ALIGN_4_BYTES = 2,
  694. DMAENGINE_ALIGN_8_BYTES = 3,
  695. DMAENGINE_ALIGN_16_BYTES = 4,
  696. DMAENGINE_ALIGN_32_BYTES = 5,
  697. DMAENGINE_ALIGN_64_BYTES = 6,
  698. };
  699. /**
  700. * struct dma_slave_map - associates slave device and it's slave channel with
  701. * parameter to be used by a filter function
  702. * @devname: name of the device
  703. * @slave: slave channel name
  704. * @param: opaque parameter to pass to struct dma_filter.fn
  705. */
  706. struct dma_slave_map {
  707. const char *devname;
  708. const char *slave;
  709. void *param;
  710. };
  711. /**
  712. * struct dma_filter - information for slave device/channel to filter_fn/param
  713. * mapping
  714. * @fn: filter function callback
  715. * @mapcnt: number of slave device/channel in the map
  716. * @map: array of channel to filter mapping data
  717. */
  718. struct dma_filter {
  719. dma_filter_fn fn;
  720. int mapcnt;
  721. const struct dma_slave_map *map;
  722. };
  723. /**
  724. * struct dma_device - info on the entity supplying DMA services
  725. * @chancnt: how many DMA channels are supported
  726. * @privatecnt: how many DMA channels are requested by dma_request_channel
  727. * @channels: the list of struct dma_chan
  728. * @global_node: list_head for global dma_device_list
  729. * @filter: information for device/slave to filter function/param mapping
  730. * @cap_mask: one or more dma_capability flags
  731. * @desc_metadata_modes: supported metadata modes by the DMA device
  732. * @max_xor: maximum number of xor sources, 0 if no capability
  733. * @max_pq: maximum number of PQ sources and PQ-continue capability
  734. * @copy_align: alignment shift for memcpy operations
  735. * @xor_align: alignment shift for xor operations
  736. * @pq_align: alignment shift for pq operations
  737. * @fill_align: alignment shift for memset operations
  738. * @dev_id: unique device ID
  739. * @dev: struct device reference for dma mapping api
  740. * @owner: owner module (automatically set based on the provided dev)
  741. * @src_addr_widths: bit mask of src addr widths the device supports
  742. * Width is specified in bytes, e.g. for a device supporting
  743. * a width of 4 the mask should have BIT(4) set.
  744. * @dst_addr_widths: bit mask of dst addr widths the device supports
  745. * @directions: bit mask of slave directions the device supports.
  746. * Since the enum dma_transfer_direction is not defined as bit flag for
  747. * each type, the dma controller should set BIT(<TYPE>) and same
  748. * should be checked by controller as well
  749. * @min_burst: min burst capability per-transfer
  750. * @max_burst: max burst capability per-transfer
  751. * @max_sg_burst: max number of SG list entries executed in a single burst
  752. * DMA tansaction with no software intervention for reinitialization.
  753. * Zero value means unlimited number of entries.
  754. * @residue_granularity: granularity of the transfer residue reported
  755. * by tx_status
  756. * @device_alloc_chan_resources: allocate resources and return the
  757. * number of allocated descriptors
  758. * @device_free_chan_resources: release DMA channel's resources
  759. * @device_prep_dma_memcpy: prepares a memcpy operation
  760. * @device_prep_dma_xor: prepares a xor operation
  761. * @device_prep_dma_xor_val: prepares a xor validation operation
  762. * @device_prep_dma_pq: prepares a pq operation
  763. * @device_prep_dma_pq_val: prepares a pqzero_sum operation
  764. * @device_prep_dma_memset: prepares a memset operation
  765. * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list
  766. * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
  767. * @device_prep_slave_sg: prepares a slave dma operation
  768. * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
  769. * The function takes a buffer of size buf_len. The callback function will
  770. * be called after period_len bytes have been transferred.
  771. * @device_prep_interleaved_dma: Transfer expression in a generic way.
  772. * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address
  773. * @device_caps: May be used to override the generic DMA slave capabilities
  774. * with per-channel specific ones
  775. * @device_config: Pushes a new configuration to a channel, return 0 or an error
  776. * code
  777. * @device_pause: Pauses any transfer happening on a channel. Returns
  778. * 0 or an error code
  779. * @device_resume: Resumes any transfer on a channel previously
  780. * paused. Returns 0 or an error code
  781. * @device_terminate_all: Aborts all transfers on a channel. Returns 0
  782. * or an error code
  783. * @device_synchronize: Synchronizes the termination of a transfers to the
  784. * current context.
  785. * @device_tx_status: poll for transaction completion, the optional
  786. * txstate parameter can be supplied with a pointer to get a
  787. * struct with auxiliary transfer status information, otherwise the call
  788. * will just return a simple status code
  789. * @device_issue_pending: push pending transactions to hardware
  790. * @descriptor_reuse: a submitted transfer can be resubmitted after completion
  791. * @device_release: called sometime atfer dma_async_device_unregister() is
  792. * called and there are no further references to this structure. This
  793. * must be implemented to free resources however many existing drivers
  794. * do not and are therefore not safe to unbind while in use.
  795. * @dbg_summary_show: optional routine to show contents in debugfs; default code
  796. * will be used when this is omitted, but custom code can show extra,
  797. * controller specific information.
  798. */
  799. struct dma_device {
  800. struct kref ref;
  801. unsigned int chancnt;
  802. unsigned int privatecnt;
  803. struct list_head channels;
  804. struct list_head global_node;
  805. struct dma_filter filter;
  806. dma_cap_mask_t cap_mask;
  807. enum dma_desc_metadata_mode desc_metadata_modes;
  808. unsigned short max_xor;
  809. unsigned short max_pq;
  810. enum dmaengine_alignment copy_align;
  811. enum dmaengine_alignment xor_align;
  812. enum dmaengine_alignment pq_align;
  813. enum dmaengine_alignment fill_align;
  814. #define DMA_HAS_PQ_CONTINUE (1 << 15)
  815. int dev_id;
  816. struct device *dev;
  817. struct module *owner;
  818. struct ida chan_ida;
  819. struct mutex chan_mutex; /* to protect chan_ida */
  820. u32 src_addr_widths;
  821. u32 dst_addr_widths;
  822. u32 directions;
  823. u32 min_burst;
  824. u32 max_burst;
  825. u32 max_sg_burst;
  826. bool descriptor_reuse;
  827. enum dma_residue_granularity residue_granularity;
  828. int (*device_alloc_chan_resources)(struct dma_chan *chan);
  829. void (*device_free_chan_resources)(struct dma_chan *chan);
  830. struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
  831. struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
  832. size_t len, unsigned long flags);
  833. struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
  834. struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
  835. unsigned int src_cnt, size_t len, unsigned long flags);
  836. struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
  837. struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
  838. size_t len, enum sum_check_flags *result, unsigned long flags);
  839. struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
  840. struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
  841. unsigned int src_cnt, const unsigned char *scf,
  842. size_t len, unsigned long flags);
  843. struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
  844. struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
  845. unsigned int src_cnt, const unsigned char *scf, size_t len,
  846. enum sum_check_flags *pqres, unsigned long flags);
  847. struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
  848. struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
  849. unsigned long flags);
  850. struct dma_async_tx_descriptor *(*device_prep_dma_memset_sg)(
  851. struct dma_chan *chan, struct scatterlist *sg,
  852. unsigned int nents, int value, unsigned long flags);
  853. struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
  854. struct dma_chan *chan, unsigned long flags);
  855. struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
  856. struct dma_chan *chan, struct scatterlist *sgl,
  857. unsigned int sg_len, enum dma_transfer_direction direction,
  858. unsigned long flags, void *context);
  859. struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
  860. struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
  861. size_t period_len, enum dma_transfer_direction direction,
  862. unsigned long flags);
  863. struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
  864. struct dma_chan *chan, struct dma_interleaved_template *xt,
  865. unsigned long flags);
  866. struct dma_async_tx_descriptor *(*device_prep_dma_imm_data)(
  867. struct dma_chan *chan, dma_addr_t dst, u64 data,
  868. unsigned long flags);
  869. void (*device_caps)(struct dma_chan *chan,
  870. struct dma_slave_caps *caps);
  871. int (*device_config)(struct dma_chan *chan,
  872. struct dma_slave_config *config);
  873. int (*device_pause)(struct dma_chan *chan);
  874. int (*device_resume)(struct dma_chan *chan);
  875. int (*device_terminate_all)(struct dma_chan *chan);
  876. void (*device_synchronize)(struct dma_chan *chan);
  877. enum dma_status (*device_tx_status)(struct dma_chan *chan,
  878. dma_cookie_t cookie,
  879. struct dma_tx_state *txstate);
  880. void (*device_issue_pending)(struct dma_chan *chan);
  881. void (*device_release)(struct dma_device *dev);
  882. /* debugfs support */
  883. #ifdef CONFIG_DEBUG_FS
  884. void (*dbg_summary_show)(struct seq_file *s, struct dma_device *dev);
  885. struct dentry *dbg_dev_root;
  886. #endif
  887. ANDROID_KABI_RESERVE(1);
  888. ANDROID_KABI_RESERVE(2);
  889. ANDROID_KABI_RESERVE(3);
  890. ANDROID_KABI_RESERVE(4);
  891. };
  892. static inline int dmaengine_slave_config(struct dma_chan *chan,
  893. struct dma_slave_config *config)
  894. {
  895. if (chan->device->device_config)
  896. return chan->device->device_config(chan, config);
  897. return -ENOSYS;
  898. }
  899. static inline bool is_slave_direction(enum dma_transfer_direction direction)
  900. {
  901. return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM);
  902. }
  903. static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
  904. struct dma_chan *chan, dma_addr_t buf, size_t len,
  905. enum dma_transfer_direction dir, unsigned long flags)
  906. {
  907. struct scatterlist sg;
  908. sg_init_table(&sg, 1);
  909. sg_dma_address(&sg) = buf;
  910. sg_dma_len(&sg) = len;
  911. if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
  912. return NULL;
  913. return chan->device->device_prep_slave_sg(chan, &sg, 1,
  914. dir, flags, NULL);
  915. }
  916. static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
  917. struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
  918. enum dma_transfer_direction dir, unsigned long flags)
  919. {
  920. if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
  921. return NULL;
  922. return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
  923. dir, flags, NULL);
  924. }
  925. #ifdef CONFIG_RAPIDIO_DMA_ENGINE
  926. struct rio_dma_ext;
  927. static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg(
  928. struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
  929. enum dma_transfer_direction dir, unsigned long flags,
  930. struct rio_dma_ext *rio_ext)
  931. {
  932. if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
  933. return NULL;
  934. return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
  935. dir, flags, rio_ext);
  936. }
  937. #endif
  938. static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
  939. struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
  940. size_t period_len, enum dma_transfer_direction dir,
  941. unsigned long flags)
  942. {
  943. if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic)
  944. return NULL;
  945. return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
  946. period_len, dir, flags);
  947. }
  948. static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
  949. struct dma_chan *chan, struct dma_interleaved_template *xt,
  950. unsigned long flags)
  951. {
  952. if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma)
  953. return NULL;
  954. if (flags & DMA_PREP_REPEAT &&
  955. !test_bit(DMA_REPEAT, chan->device->cap_mask.bits))
  956. return NULL;
  957. return chan->device->device_prep_interleaved_dma(chan, xt, flags);
  958. }
  959. static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset(
  960. struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
  961. unsigned long flags)
  962. {
  963. if (!chan || !chan->device || !chan->device->device_prep_dma_memset)
  964. return NULL;
  965. return chan->device->device_prep_dma_memset(chan, dest, value,
  966. len, flags);
  967. }
  968. static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memcpy(
  969. struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
  970. size_t len, unsigned long flags)
  971. {
  972. if (!chan || !chan->device || !chan->device->device_prep_dma_memcpy)
  973. return NULL;
  974. return chan->device->device_prep_dma_memcpy(chan, dest, src,
  975. len, flags);
  976. }
  977. static inline bool dmaengine_is_metadata_mode_supported(struct dma_chan *chan,
  978. enum dma_desc_metadata_mode mode)
  979. {
  980. if (!chan)
  981. return false;
  982. return !!(chan->device->desc_metadata_modes & mode);
  983. }
  984. #ifdef CONFIG_DMA_ENGINE
  985. int dmaengine_desc_attach_metadata(struct dma_async_tx_descriptor *desc,
  986. void *data, size_t len);
  987. void *dmaengine_desc_get_metadata_ptr(struct dma_async_tx_descriptor *desc,
  988. size_t *payload_len, size_t *max_len);
  989. int dmaengine_desc_set_metadata_len(struct dma_async_tx_descriptor *desc,
  990. size_t payload_len);
  991. #else /* CONFIG_DMA_ENGINE */
  992. static inline int dmaengine_desc_attach_metadata(
  993. struct dma_async_tx_descriptor *desc, void *data, size_t len)
  994. {
  995. return -EINVAL;
  996. }
  997. static inline void *dmaengine_desc_get_metadata_ptr(
  998. struct dma_async_tx_descriptor *desc, size_t *payload_len,
  999. size_t *max_len)
  1000. {
  1001. return NULL;
  1002. }
  1003. static inline int dmaengine_desc_set_metadata_len(
  1004. struct dma_async_tx_descriptor *desc, size_t payload_len)
  1005. {
  1006. return -EINVAL;
  1007. }
  1008. #endif /* CONFIG_DMA_ENGINE */
  1009. /**
  1010. * dmaengine_terminate_all() - Terminate all active DMA transfers
  1011. * @chan: The channel for which to terminate the transfers
  1012. *
  1013. * This function is DEPRECATED use either dmaengine_terminate_sync() or
  1014. * dmaengine_terminate_async() instead.
  1015. */
  1016. static inline int dmaengine_terminate_all(struct dma_chan *chan)
  1017. {
  1018. if (chan->device->device_terminate_all)
  1019. return chan->device->device_terminate_all(chan);
  1020. return -ENOSYS;
  1021. }
  1022. /**
  1023. * dmaengine_terminate_async() - Terminate all active DMA transfers
  1024. * @chan: The channel for which to terminate the transfers
  1025. *
  1026. * Calling this function will terminate all active and pending descriptors
  1027. * that have previously been submitted to the channel. It is not guaranteed
  1028. * though that the transfer for the active descriptor has stopped when the
  1029. * function returns. Furthermore it is possible the complete callback of a
  1030. * submitted transfer is still running when this function returns.
  1031. *
  1032. * dmaengine_synchronize() needs to be called before it is safe to free
  1033. * any memory that is accessed by previously submitted descriptors or before
  1034. * freeing any resources accessed from within the completion callback of any
  1035. * previously submitted descriptors.
  1036. *
  1037. * This function can be called from atomic context as well as from within a
  1038. * complete callback of a descriptor submitted on the same channel.
  1039. *
  1040. * If none of the two conditions above apply consider using
  1041. * dmaengine_terminate_sync() instead.
  1042. */
  1043. static inline int dmaengine_terminate_async(struct dma_chan *chan)
  1044. {
  1045. if (chan->device->device_terminate_all)
  1046. return chan->device->device_terminate_all(chan);
  1047. return -EINVAL;
  1048. }
  1049. /**
  1050. * dmaengine_synchronize() - Synchronize DMA channel termination
  1051. * @chan: The channel to synchronize
  1052. *
  1053. * Synchronizes to the DMA channel termination to the current context. When this
  1054. * function returns it is guaranteed that all transfers for previously issued
  1055. * descriptors have stopped and it is safe to free the memory associated
  1056. * with them. Furthermore it is guaranteed that all complete callback functions
  1057. * for a previously submitted descriptor have finished running and it is safe to
  1058. * free resources accessed from within the complete callbacks.
  1059. *
  1060. * The behavior of this function is undefined if dma_async_issue_pending() has
  1061. * been called between dmaengine_terminate_async() and this function.
  1062. *
  1063. * This function must only be called from non-atomic context and must not be
  1064. * called from within a complete callback of a descriptor submitted on the same
  1065. * channel.
  1066. */
  1067. static inline void dmaengine_synchronize(struct dma_chan *chan)
  1068. {
  1069. might_sleep();
  1070. if (chan->device->device_synchronize)
  1071. chan->device->device_synchronize(chan);
  1072. }
  1073. /**
  1074. * dmaengine_terminate_sync() - Terminate all active DMA transfers
  1075. * @chan: The channel for which to terminate the transfers
  1076. *
  1077. * Calling this function will terminate all active and pending transfers
  1078. * that have previously been submitted to the channel. It is similar to
  1079. * dmaengine_terminate_async() but guarantees that the DMA transfer has actually
  1080. * stopped and that all complete callbacks have finished running when the
  1081. * function returns.
  1082. *
  1083. * This function must only be called from non-atomic context and must not be
  1084. * called from within a complete callback of a descriptor submitted on the same
  1085. * channel.
  1086. */
  1087. static inline int dmaengine_terminate_sync(struct dma_chan *chan)
  1088. {
  1089. int ret;
  1090. ret = dmaengine_terminate_async(chan);
  1091. if (ret)
  1092. return ret;
  1093. dmaengine_synchronize(chan);
  1094. return 0;
  1095. }
  1096. static inline int dmaengine_pause(struct dma_chan *chan)
  1097. {
  1098. if (chan->device->device_pause)
  1099. return chan->device->device_pause(chan);
  1100. return -ENOSYS;
  1101. }
  1102. static inline int dmaengine_resume(struct dma_chan *chan)
  1103. {
  1104. if (chan->device->device_resume)
  1105. return chan->device->device_resume(chan);
  1106. return -ENOSYS;
  1107. }
  1108. static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan,
  1109. dma_cookie_t cookie, struct dma_tx_state *state)
  1110. {
  1111. return chan->device->device_tx_status(chan, cookie, state);
  1112. }
  1113. static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
  1114. {
  1115. return desc->tx_submit(desc);
  1116. }
  1117. static inline bool dmaengine_check_align(enum dmaengine_alignment align,
  1118. size_t off1, size_t off2, size_t len)
  1119. {
  1120. return !(((1 << align) - 1) & (off1 | off2 | len));
  1121. }
  1122. static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
  1123. size_t off2, size_t len)
  1124. {
  1125. return dmaengine_check_align(dev->copy_align, off1, off2, len);
  1126. }
  1127. static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
  1128. size_t off2, size_t len)
  1129. {
  1130. return dmaengine_check_align(dev->xor_align, off1, off2, len);
  1131. }
  1132. static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
  1133. size_t off2, size_t len)
  1134. {
  1135. return dmaengine_check_align(dev->pq_align, off1, off2, len);
  1136. }
  1137. static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
  1138. size_t off2, size_t len)
  1139. {
  1140. return dmaengine_check_align(dev->fill_align, off1, off2, len);
  1141. }
  1142. static inline void
  1143. dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
  1144. {
  1145. dma->max_pq = maxpq;
  1146. if (has_pq_continue)
  1147. dma->max_pq |= DMA_HAS_PQ_CONTINUE;
  1148. }
  1149. static inline bool dmaf_continue(enum dma_ctrl_flags flags)
  1150. {
  1151. return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
  1152. }
  1153. static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
  1154. {
  1155. enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
  1156. return (flags & mask) == mask;
  1157. }
  1158. static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
  1159. {
  1160. return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
  1161. }
  1162. static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
  1163. {
  1164. return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
  1165. }
  1166. /* dma_maxpq - reduce maxpq in the face of continued operations
  1167. * @dma - dma device with PQ capability
  1168. * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
  1169. *
  1170. * When an engine does not support native continuation we need 3 extra
  1171. * source slots to reuse P and Q with the following coefficients:
  1172. * 1/ {00} * P : remove P from Q', but use it as a source for P'
  1173. * 2/ {01} * Q : use Q to continue Q' calculation
  1174. * 3/ {00} * Q : subtract Q from P' to cancel (2)
  1175. *
  1176. * In the case where P is disabled we only need 1 extra source:
  1177. * 1/ {01} * Q : use Q to continue Q' calculation
  1178. */
  1179. static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
  1180. {
  1181. if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
  1182. return dma_dev_to_maxpq(dma);
  1183. if (dmaf_p_disabled_continue(flags))
  1184. return dma_dev_to_maxpq(dma) - 1;
  1185. if (dmaf_continue(flags))
  1186. return dma_dev_to_maxpq(dma) - 3;
  1187. BUG();
  1188. }
  1189. static inline size_t dmaengine_get_icg(bool inc, bool sgl, size_t icg,
  1190. size_t dir_icg)
  1191. {
  1192. if (inc) {
  1193. if (dir_icg)
  1194. return dir_icg;
  1195. if (sgl)
  1196. return icg;
  1197. }
  1198. return 0;
  1199. }
  1200. static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template *xt,
  1201. struct data_chunk *chunk)
  1202. {
  1203. return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl,
  1204. chunk->icg, chunk->dst_icg);
  1205. }
  1206. static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template *xt,
  1207. struct data_chunk *chunk)
  1208. {
  1209. return dmaengine_get_icg(xt->src_inc, xt->src_sgl,
  1210. chunk->icg, chunk->src_icg);
  1211. }
  1212. /* --- public DMA engine API --- */
  1213. #ifdef CONFIG_DMA_ENGINE
  1214. void dmaengine_get(void);
  1215. void dmaengine_put(void);
  1216. #else
  1217. static inline void dmaengine_get(void)
  1218. {
  1219. }
  1220. static inline void dmaengine_put(void)
  1221. {
  1222. }
  1223. #endif
  1224. #ifdef CONFIG_ASYNC_TX_DMA
  1225. #define async_dmaengine_get() dmaengine_get()
  1226. #define async_dmaengine_put() dmaengine_put()
  1227. #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
  1228. #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
  1229. #else
  1230. #define async_dma_find_channel(type) dma_find_channel(type)
  1231. #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
  1232. #else
  1233. static inline void async_dmaengine_get(void)
  1234. {
  1235. }
  1236. static inline void async_dmaengine_put(void)
  1237. {
  1238. }
  1239. static inline struct dma_chan *
  1240. async_dma_find_channel(enum dma_transaction_type type)
  1241. {
  1242. return NULL;
  1243. }
  1244. #endif /* CONFIG_ASYNC_TX_DMA */
  1245. void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
  1246. struct dma_chan *chan);
  1247. static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
  1248. {
  1249. tx->flags |= DMA_CTRL_ACK;
  1250. }
  1251. static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
  1252. {
  1253. tx->flags &= ~DMA_CTRL_ACK;
  1254. }
  1255. static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
  1256. {
  1257. return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
  1258. }
  1259. #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
  1260. static inline void
  1261. __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
  1262. {
  1263. set_bit(tx_type, dstp->bits);
  1264. }
  1265. #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
  1266. static inline void
  1267. __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
  1268. {
  1269. clear_bit(tx_type, dstp->bits);
  1270. }
  1271. #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
  1272. static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
  1273. {
  1274. bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
  1275. }
  1276. #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
  1277. static inline int
  1278. __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
  1279. {
  1280. return test_bit(tx_type, srcp->bits);
  1281. }
  1282. #define for_each_dma_cap_mask(cap, mask) \
  1283. for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
  1284. /**
  1285. * dma_async_issue_pending - flush pending transactions to HW
  1286. * @chan: target DMA channel
  1287. *
  1288. * This allows drivers to push copies to HW in batches,
  1289. * reducing MMIO writes where possible.
  1290. */
  1291. static inline void dma_async_issue_pending(struct dma_chan *chan)
  1292. {
  1293. chan->device->device_issue_pending(chan);
  1294. }
  1295. /**
  1296. * dma_async_is_tx_complete - poll for transaction completion
  1297. * @chan: DMA channel
  1298. * @cookie: transaction identifier to check status of
  1299. * @last: returns last completed cookie, can be NULL
  1300. * @used: returns last issued cookie, can be NULL
  1301. *
  1302. * If @last and @used are passed in, upon return they reflect the driver
  1303. * internal state and can be used with dma_async_is_complete() to check
  1304. * the status of multiple cookies without re-checking hardware state.
  1305. */
  1306. static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
  1307. dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
  1308. {
  1309. struct dma_tx_state state;
  1310. enum dma_status status;
  1311. status = chan->device->device_tx_status(chan, cookie, &state);
  1312. if (last)
  1313. *last = state.last;
  1314. if (used)
  1315. *used = state.used;
  1316. return status;
  1317. }
  1318. /**
  1319. * dma_async_is_complete - test a cookie against chan state
  1320. * @cookie: transaction identifier to test status of
  1321. * @last_complete: last know completed transaction
  1322. * @last_used: last cookie value handed out
  1323. *
  1324. * dma_async_is_complete() is used in dma_async_is_tx_complete()
  1325. * the test logic is separated for lightweight testing of multiple cookies
  1326. */
  1327. static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
  1328. dma_cookie_t last_complete, dma_cookie_t last_used)
  1329. {
  1330. if (last_complete <= last_used) {
  1331. if ((cookie <= last_complete) || (cookie > last_used))
  1332. return DMA_COMPLETE;
  1333. } else {
  1334. if ((cookie <= last_complete) && (cookie > last_used))
  1335. return DMA_COMPLETE;
  1336. }
  1337. return DMA_IN_PROGRESS;
  1338. }
  1339. static inline void
  1340. dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
  1341. {
  1342. if (!st)
  1343. return;
  1344. st->last = last;
  1345. st->used = used;
  1346. st->residue = residue;
  1347. }
  1348. #ifdef CONFIG_DMA_ENGINE
  1349. struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
  1350. enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
  1351. enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
  1352. void dma_issue_pending_all(void);
  1353. struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
  1354. dma_filter_fn fn, void *fn_param,
  1355. struct device_node *np);
  1356. struct dma_chan *dma_request_chan(struct device *dev, const char *name);
  1357. struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask);
  1358. void dma_release_channel(struct dma_chan *chan);
  1359. int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps);
  1360. #else
  1361. static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
  1362. {
  1363. return NULL;
  1364. }
  1365. static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
  1366. {
  1367. return DMA_COMPLETE;
  1368. }
  1369. static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
  1370. {
  1371. return DMA_COMPLETE;
  1372. }
  1373. static inline void dma_issue_pending_all(void)
  1374. {
  1375. }
  1376. static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
  1377. dma_filter_fn fn,
  1378. void *fn_param,
  1379. struct device_node *np)
  1380. {
  1381. return NULL;
  1382. }
  1383. static inline struct dma_chan *dma_request_chan(struct device *dev,
  1384. const char *name)
  1385. {
  1386. return ERR_PTR(-ENODEV);
  1387. }
  1388. static inline struct dma_chan *dma_request_chan_by_mask(
  1389. const dma_cap_mask_t *mask)
  1390. {
  1391. return ERR_PTR(-ENODEV);
  1392. }
  1393. static inline void dma_release_channel(struct dma_chan *chan)
  1394. {
  1395. }
  1396. static inline int dma_get_slave_caps(struct dma_chan *chan,
  1397. struct dma_slave_caps *caps)
  1398. {
  1399. return -ENXIO;
  1400. }
  1401. #endif
  1402. static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor *tx)
  1403. {
  1404. struct dma_slave_caps caps;
  1405. int ret;
  1406. ret = dma_get_slave_caps(tx->chan, &caps);
  1407. if (ret)
  1408. return ret;
  1409. if (!caps.descriptor_reuse)
  1410. return -EPERM;
  1411. tx->flags |= DMA_CTRL_REUSE;
  1412. return 0;
  1413. }
  1414. static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor *tx)
  1415. {
  1416. tx->flags &= ~DMA_CTRL_REUSE;
  1417. }
  1418. static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor *tx)
  1419. {
  1420. return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE;
  1421. }
  1422. static inline int dmaengine_desc_free(struct dma_async_tx_descriptor *desc)
  1423. {
  1424. /* this is supported for reusable desc, so check that */
  1425. if (!dmaengine_desc_test_reuse(desc))
  1426. return -EPERM;
  1427. return desc->desc_free(desc);
  1428. }
  1429. /* --- DMA device --- */
  1430. int dma_async_device_register(struct dma_device *device);
  1431. int dmaenginem_async_device_register(struct dma_device *device);
  1432. void dma_async_device_unregister(struct dma_device *device);
  1433. int dma_async_device_channel_register(struct dma_device *device,
  1434. struct dma_chan *chan);
  1435. void dma_async_device_channel_unregister(struct dma_device *device,
  1436. struct dma_chan *chan);
  1437. void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
  1438. #define dma_request_channel(mask, x, y) \
  1439. __dma_request_channel(&(mask), x, y, NULL)
  1440. /* Deprecated, please use dma_request_chan() directly */
  1441. static inline struct dma_chan * __deprecated
  1442. dma_request_slave_channel(struct device *dev, const char *name)
  1443. {
  1444. struct dma_chan *ch = dma_request_chan(dev, name);
  1445. return IS_ERR(ch) ? NULL : ch;
  1446. }
  1447. static inline struct dma_chan
  1448. *dma_request_slave_channel_compat(const dma_cap_mask_t mask,
  1449. dma_filter_fn fn, void *fn_param,
  1450. struct device *dev, const char *name)
  1451. {
  1452. struct dma_chan *chan;
  1453. chan = dma_request_slave_channel(dev, name);
  1454. if (chan)
  1455. return chan;
  1456. if (!fn || !fn_param)
  1457. return NULL;
  1458. return __dma_request_channel(&mask, fn, fn_param, NULL);
  1459. }
  1460. static inline char *
  1461. dmaengine_get_direction_text(enum dma_transfer_direction dir)
  1462. {
  1463. switch (dir) {
  1464. case DMA_DEV_TO_MEM:
  1465. return "DEV_TO_MEM";
  1466. case DMA_MEM_TO_DEV:
  1467. return "MEM_TO_DEV";
  1468. case DMA_MEM_TO_MEM:
  1469. return "MEM_TO_MEM";
  1470. case DMA_DEV_TO_DEV:
  1471. return "DEV_TO_DEV";
  1472. default:
  1473. return "invalid";
  1474. }
  1475. }
  1476. #endif /* DMAENGINE_H */