cper.h 16 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * UEFI Common Platform Error Record
  4. *
  5. * Copyright (C) 2010, Intel Corp.
  6. * Author: Huang Ying <ying.huang@intel.com>
  7. */
  8. #ifndef LINUX_CPER_H
  9. #define LINUX_CPER_H
  10. #include <linux/uuid.h>
  11. #include <linux/trace_seq.h>
  12. /* CPER record signature and the size */
  13. #define CPER_SIG_RECORD "CPER"
  14. #define CPER_SIG_SIZE 4
  15. /* Used in signature_end field in struct cper_record_header */
  16. #define CPER_SIG_END 0xffffffff
  17. /*
  18. * CPER record header revision, used in revision field in struct
  19. * cper_record_header
  20. */
  21. #define CPER_RECORD_REV 0x0100
  22. /*
  23. * CPER record length contains the CPER fields which are relevant for further
  24. * handling of a memory error in userspace (we don't carry all the fields
  25. * defined in the UEFI spec because some of them don't make any sense.)
  26. * Currently, a length of 256 should be more than enough.
  27. */
  28. #define CPER_REC_LEN 256
  29. /*
  30. * Severity definition for error_severity in struct cper_record_header
  31. * and section_severity in struct cper_section_descriptor
  32. */
  33. enum {
  34. CPER_SEV_RECOVERABLE,
  35. CPER_SEV_FATAL,
  36. CPER_SEV_CORRECTED,
  37. CPER_SEV_INFORMATIONAL,
  38. };
  39. /*
  40. * Validation bits definition for validation_bits in struct
  41. * cper_record_header. If set, corresponding fields in struct
  42. * cper_record_header contain valid information.
  43. */
  44. #define CPER_VALID_PLATFORM_ID 0x0001
  45. #define CPER_VALID_TIMESTAMP 0x0002
  46. #define CPER_VALID_PARTITION_ID 0x0004
  47. /*
  48. * Notification type used to generate error record, used in
  49. * notification_type in struct cper_record_header. These UUIDs are defined
  50. * in the UEFI spec v2.7, sec N.2.1.
  51. */
  52. /* Corrected Machine Check */
  53. #define CPER_NOTIFY_CMC \
  54. GUID_INIT(0x2DCE8BB1, 0xBDD7, 0x450e, 0xB9, 0xAD, 0x9C, 0xF4, \
  55. 0xEB, 0xD4, 0xF8, 0x90)
  56. /* Corrected Platform Error */
  57. #define CPER_NOTIFY_CPE \
  58. GUID_INIT(0x4E292F96, 0xD843, 0x4a55, 0xA8, 0xC2, 0xD4, 0x81, \
  59. 0xF2, 0x7E, 0xBE, 0xEE)
  60. /* Machine Check Exception */
  61. #define CPER_NOTIFY_MCE \
  62. GUID_INIT(0xE8F56FFE, 0x919C, 0x4cc5, 0xBA, 0x88, 0x65, 0xAB, \
  63. 0xE1, 0x49, 0x13, 0xBB)
  64. /* PCI Express Error */
  65. #define CPER_NOTIFY_PCIE \
  66. GUID_INIT(0xCF93C01F, 0x1A16, 0x4dfc, 0xB8, 0xBC, 0x9C, 0x4D, \
  67. 0xAF, 0x67, 0xC1, 0x04)
  68. /* INIT Record (for IPF) */
  69. #define CPER_NOTIFY_INIT \
  70. GUID_INIT(0xCC5263E8, 0x9308, 0x454a, 0x89, 0xD0, 0x34, 0x0B, \
  71. 0xD3, 0x9B, 0xC9, 0x8E)
  72. /* Non-Maskable Interrupt */
  73. #define CPER_NOTIFY_NMI \
  74. GUID_INIT(0x5BAD89FF, 0xB7E6, 0x42c9, 0x81, 0x4A, 0xCF, 0x24, \
  75. 0x85, 0xD6, 0xE9, 0x8A)
  76. /* BOOT Error Record */
  77. #define CPER_NOTIFY_BOOT \
  78. GUID_INIT(0x3D61A466, 0xAB40, 0x409a, 0xA6, 0x98, 0xF3, 0x62, \
  79. 0xD4, 0x64, 0xB3, 0x8F)
  80. /* DMA Remapping Error */
  81. #define CPER_NOTIFY_DMAR \
  82. GUID_INIT(0x667DD791, 0xC6B3, 0x4c27, 0x8A, 0x6B, 0x0F, 0x8E, \
  83. 0x72, 0x2D, 0xEB, 0x41)
  84. /*
  85. * Flags bits definitions for flags in struct cper_record_header
  86. * If set, the error has been recovered
  87. */
  88. #define CPER_HW_ERROR_FLAGS_RECOVERED 0x1
  89. /* If set, the error is for previous boot */
  90. #define CPER_HW_ERROR_FLAGS_PREVERR 0x2
  91. /* If set, the error is injected for testing */
  92. #define CPER_HW_ERROR_FLAGS_SIMULATED 0x4
  93. /*
  94. * CPER section header revision, used in revision field in struct
  95. * cper_section_descriptor
  96. */
  97. #define CPER_SEC_REV 0x0100
  98. /*
  99. * Validation bits definition for validation_bits in struct
  100. * cper_section_descriptor. If set, corresponding fields in struct
  101. * cper_section_descriptor contain valid information.
  102. */
  103. #define CPER_SEC_VALID_FRU_ID 0x1
  104. #define CPER_SEC_VALID_FRU_TEXT 0x2
  105. /*
  106. * Flags bits definitions for flags in struct cper_section_descriptor
  107. *
  108. * If set, the section is associated with the error condition
  109. * directly, and should be focused on
  110. */
  111. #define CPER_SEC_PRIMARY 0x0001
  112. /*
  113. * If set, the error was not contained within the processor or memory
  114. * hierarchy and the error may have propagated to persistent storage
  115. * or network
  116. */
  117. #define CPER_SEC_CONTAINMENT_WARNING 0x0002
  118. /* If set, the component must be re-initialized or re-enabled prior to use */
  119. #define CPER_SEC_RESET 0x0004
  120. /* If set, Linux may choose to discontinue use of the resource */
  121. #define CPER_SEC_ERROR_THRESHOLD_EXCEEDED 0x0008
  122. /*
  123. * If set, resource could not be queried for error information due to
  124. * conflicts with other system software or resources. Some fields of
  125. * the section will be invalid
  126. */
  127. #define CPER_SEC_RESOURCE_NOT_ACCESSIBLE 0x0010
  128. /*
  129. * If set, action has been taken to ensure error containment (such as
  130. * poisoning data), but the error has not been fully corrected and the
  131. * data has not been consumed. Linux may choose to take further
  132. * corrective action before the data is consumed
  133. */
  134. #define CPER_SEC_LATENT_ERROR 0x0020
  135. /*
  136. * Section type definitions, used in section_type field in struct
  137. * cper_section_descriptor. These UUIDs are defined in the UEFI spec
  138. * v2.7, sec N.2.2.
  139. */
  140. /* Processor Generic */
  141. #define CPER_SEC_PROC_GENERIC \
  142. GUID_INIT(0x9876CCAD, 0x47B4, 0x4bdb, 0xB6, 0x5E, 0x16, 0xF1, \
  143. 0x93, 0xC4, 0xF3, 0xDB)
  144. /* Processor Specific: X86/X86_64 */
  145. #define CPER_SEC_PROC_IA \
  146. GUID_INIT(0xDC3EA0B0, 0xA144, 0x4797, 0xB9, 0x5B, 0x53, 0xFA, \
  147. 0x24, 0x2B, 0x6E, 0x1D)
  148. /* Processor Specific: IA64 */
  149. #define CPER_SEC_PROC_IPF \
  150. GUID_INIT(0xE429FAF1, 0x3CB7, 0x11D4, 0x0B, 0xCA, 0x07, 0x00, \
  151. 0x80, 0xC7, 0x3C, 0x88, 0x81)
  152. /* Processor Specific: ARM */
  153. #define CPER_SEC_PROC_ARM \
  154. GUID_INIT(0xE19E3D16, 0xBC11, 0x11E4, 0x9C, 0xAA, 0xC2, 0x05, \
  155. 0x1D, 0x5D, 0x46, 0xB0)
  156. /* Platform Memory */
  157. #define CPER_SEC_PLATFORM_MEM \
  158. GUID_INIT(0xA5BC1114, 0x6F64, 0x4EDE, 0xB8, 0x63, 0x3E, 0x83, \
  159. 0xED, 0x7C, 0x83, 0xB1)
  160. #define CPER_SEC_PCIE \
  161. GUID_INIT(0xD995E954, 0xBBC1, 0x430F, 0xAD, 0x91, 0xB4, 0x4D, \
  162. 0xCB, 0x3C, 0x6F, 0x35)
  163. /* Firmware Error Record Reference */
  164. #define CPER_SEC_FW_ERR_REC_REF \
  165. GUID_INIT(0x81212A96, 0x09ED, 0x4996, 0x94, 0x71, 0x8D, 0x72, \
  166. 0x9C, 0x8E, 0x69, 0xED)
  167. /* PCI/PCI-X Bus */
  168. #define CPER_SEC_PCI_X_BUS \
  169. GUID_INIT(0xC5753963, 0x3B84, 0x4095, 0xBF, 0x78, 0xED, 0xDA, \
  170. 0xD3, 0xF9, 0xC9, 0xDD)
  171. /* PCI Component/Device */
  172. #define CPER_SEC_PCI_DEV \
  173. GUID_INIT(0xEB5E4685, 0xCA66, 0x4769, 0xB6, 0xA2, 0x26, 0x06, \
  174. 0x8B, 0x00, 0x13, 0x26)
  175. #define CPER_SEC_DMAR_GENERIC \
  176. GUID_INIT(0x5B51FEF7, 0xC79D, 0x4434, 0x8F, 0x1B, 0xAA, 0x62, \
  177. 0xDE, 0x3E, 0x2C, 0x64)
  178. /* Intel VT for Directed I/O specific DMAr */
  179. #define CPER_SEC_DMAR_VT \
  180. GUID_INIT(0x71761D37, 0x32B2, 0x45cd, 0xA7, 0xD0, 0xB0, 0xFE, \
  181. 0xDD, 0x93, 0xE8, 0xCF)
  182. /* IOMMU specific DMAr */
  183. #define CPER_SEC_DMAR_IOMMU \
  184. GUID_INIT(0x036F84E1, 0x7F37, 0x428c, 0xA7, 0x9E, 0x57, 0x5F, \
  185. 0xDF, 0xAA, 0x84, 0xEC)
  186. #define CPER_PROC_VALID_TYPE 0x0001
  187. #define CPER_PROC_VALID_ISA 0x0002
  188. #define CPER_PROC_VALID_ERROR_TYPE 0x0004
  189. #define CPER_PROC_VALID_OPERATION 0x0008
  190. #define CPER_PROC_VALID_FLAGS 0x0010
  191. #define CPER_PROC_VALID_LEVEL 0x0020
  192. #define CPER_PROC_VALID_VERSION 0x0040
  193. #define CPER_PROC_VALID_BRAND_INFO 0x0080
  194. #define CPER_PROC_VALID_ID 0x0100
  195. #define CPER_PROC_VALID_TARGET_ADDRESS 0x0200
  196. #define CPER_PROC_VALID_REQUESTOR_ID 0x0400
  197. #define CPER_PROC_VALID_RESPONDER_ID 0x0800
  198. #define CPER_PROC_VALID_IP 0x1000
  199. #define CPER_MEM_VALID_ERROR_STATUS 0x0001
  200. #define CPER_MEM_VALID_PA 0x0002
  201. #define CPER_MEM_VALID_PA_MASK 0x0004
  202. #define CPER_MEM_VALID_NODE 0x0008
  203. #define CPER_MEM_VALID_CARD 0x0010
  204. #define CPER_MEM_VALID_MODULE 0x0020
  205. #define CPER_MEM_VALID_BANK 0x0040
  206. #define CPER_MEM_VALID_DEVICE 0x0080
  207. #define CPER_MEM_VALID_ROW 0x0100
  208. #define CPER_MEM_VALID_COLUMN 0x0200
  209. #define CPER_MEM_VALID_BIT_POSITION 0x0400
  210. #define CPER_MEM_VALID_REQUESTOR_ID 0x0800
  211. #define CPER_MEM_VALID_RESPONDER_ID 0x1000
  212. #define CPER_MEM_VALID_TARGET_ID 0x2000
  213. #define CPER_MEM_VALID_ERROR_TYPE 0x4000
  214. #define CPER_MEM_VALID_RANK_NUMBER 0x8000
  215. #define CPER_MEM_VALID_CARD_HANDLE 0x10000
  216. #define CPER_MEM_VALID_MODULE_HANDLE 0x20000
  217. #define CPER_MEM_VALID_ROW_EXT 0x40000
  218. #define CPER_MEM_VALID_BANK_GROUP 0x80000
  219. #define CPER_MEM_VALID_BANK_ADDRESS 0x100000
  220. #define CPER_MEM_VALID_CHIP_ID 0x200000
  221. #define CPER_MEM_EXT_ROW_MASK 0x3
  222. #define CPER_MEM_EXT_ROW_SHIFT 16
  223. #define CPER_MEM_BANK_ADDRESS_MASK 0xff
  224. #define CPER_MEM_BANK_GROUP_SHIFT 8
  225. #define CPER_MEM_CHIP_ID_SHIFT 5
  226. #define CPER_PCIE_VALID_PORT_TYPE 0x0001
  227. #define CPER_PCIE_VALID_VERSION 0x0002
  228. #define CPER_PCIE_VALID_COMMAND_STATUS 0x0004
  229. #define CPER_PCIE_VALID_DEVICE_ID 0x0008
  230. #define CPER_PCIE_VALID_SERIAL_NUMBER 0x0010
  231. #define CPER_PCIE_VALID_BRIDGE_CONTROL_STATUS 0x0020
  232. #define CPER_PCIE_VALID_CAPABILITY 0x0040
  233. #define CPER_PCIE_VALID_AER_INFO 0x0080
  234. #define CPER_PCIE_SLOT_SHIFT 3
  235. #define CPER_ARM_VALID_MPIDR BIT(0)
  236. #define CPER_ARM_VALID_AFFINITY_LEVEL BIT(1)
  237. #define CPER_ARM_VALID_RUNNING_STATE BIT(2)
  238. #define CPER_ARM_VALID_VENDOR_INFO BIT(3)
  239. #define CPER_ARM_INFO_VALID_MULTI_ERR BIT(0)
  240. #define CPER_ARM_INFO_VALID_FLAGS BIT(1)
  241. #define CPER_ARM_INFO_VALID_ERR_INFO BIT(2)
  242. #define CPER_ARM_INFO_VALID_VIRT_ADDR BIT(3)
  243. #define CPER_ARM_INFO_VALID_PHYSICAL_ADDR BIT(4)
  244. #define CPER_ARM_INFO_FLAGS_FIRST BIT(0)
  245. #define CPER_ARM_INFO_FLAGS_LAST BIT(1)
  246. #define CPER_ARM_INFO_FLAGS_PROPAGATED BIT(2)
  247. #define CPER_ARM_INFO_FLAGS_OVERFLOW BIT(3)
  248. #define CPER_ARM_CACHE_ERROR 0
  249. #define CPER_ARM_TLB_ERROR 1
  250. #define CPER_ARM_BUS_ERROR 2
  251. #define CPER_ARM_VENDOR_ERROR 3
  252. #define CPER_ARM_MAX_TYPE CPER_ARM_VENDOR_ERROR
  253. #define CPER_ARM_ERR_VALID_TRANSACTION_TYPE BIT(0)
  254. #define CPER_ARM_ERR_VALID_OPERATION_TYPE BIT(1)
  255. #define CPER_ARM_ERR_VALID_LEVEL BIT(2)
  256. #define CPER_ARM_ERR_VALID_PROC_CONTEXT_CORRUPT BIT(3)
  257. #define CPER_ARM_ERR_VALID_CORRECTED BIT(4)
  258. #define CPER_ARM_ERR_VALID_PRECISE_PC BIT(5)
  259. #define CPER_ARM_ERR_VALID_RESTARTABLE_PC BIT(6)
  260. #define CPER_ARM_ERR_VALID_PARTICIPATION_TYPE BIT(7)
  261. #define CPER_ARM_ERR_VALID_TIME_OUT BIT(8)
  262. #define CPER_ARM_ERR_VALID_ADDRESS_SPACE BIT(9)
  263. #define CPER_ARM_ERR_VALID_MEM_ATTRIBUTES BIT(10)
  264. #define CPER_ARM_ERR_VALID_ACCESS_MODE BIT(11)
  265. #define CPER_ARM_ERR_TRANSACTION_SHIFT 16
  266. #define CPER_ARM_ERR_TRANSACTION_MASK GENMASK(1,0)
  267. #define CPER_ARM_ERR_OPERATION_SHIFT 18
  268. #define CPER_ARM_ERR_OPERATION_MASK GENMASK(3,0)
  269. #define CPER_ARM_ERR_LEVEL_SHIFT 22
  270. #define CPER_ARM_ERR_LEVEL_MASK GENMASK(2,0)
  271. #define CPER_ARM_ERR_PC_CORRUPT_SHIFT 25
  272. #define CPER_ARM_ERR_PC_CORRUPT_MASK GENMASK(0,0)
  273. #define CPER_ARM_ERR_CORRECTED_SHIFT 26
  274. #define CPER_ARM_ERR_CORRECTED_MASK GENMASK(0,0)
  275. #define CPER_ARM_ERR_PRECISE_PC_SHIFT 27
  276. #define CPER_ARM_ERR_PRECISE_PC_MASK GENMASK(0,0)
  277. #define CPER_ARM_ERR_RESTARTABLE_PC_SHIFT 28
  278. #define CPER_ARM_ERR_RESTARTABLE_PC_MASK GENMASK(0,0)
  279. #define CPER_ARM_ERR_PARTICIPATION_TYPE_SHIFT 29
  280. #define CPER_ARM_ERR_PARTICIPATION_TYPE_MASK GENMASK(1,0)
  281. #define CPER_ARM_ERR_TIME_OUT_SHIFT 31
  282. #define CPER_ARM_ERR_TIME_OUT_MASK GENMASK(0,0)
  283. #define CPER_ARM_ERR_ADDRESS_SPACE_SHIFT 32
  284. #define CPER_ARM_ERR_ADDRESS_SPACE_MASK GENMASK(1,0)
  285. #define CPER_ARM_ERR_MEM_ATTRIBUTES_SHIFT 34
  286. #define CPER_ARM_ERR_MEM_ATTRIBUTES_MASK GENMASK(8,0)
  287. #define CPER_ARM_ERR_ACCESS_MODE_SHIFT 43
  288. #define CPER_ARM_ERR_ACCESS_MODE_MASK GENMASK(0,0)
  289. /*
  290. * All tables and structs must be byte-packed to match CPER
  291. * specification, since the tables are provided by the system BIOS
  292. */
  293. #pragma pack(1)
  294. /* Record Header, UEFI v2.7 sec N.2.1 */
  295. struct cper_record_header {
  296. char signature[CPER_SIG_SIZE]; /* must be CPER_SIG_RECORD */
  297. u16 revision; /* must be CPER_RECORD_REV */
  298. u32 signature_end; /* must be CPER_SIG_END */
  299. u16 section_count;
  300. u32 error_severity;
  301. u32 validation_bits;
  302. u32 record_length;
  303. u64 timestamp;
  304. guid_t platform_id;
  305. guid_t partition_id;
  306. guid_t creator_id;
  307. guid_t notification_type;
  308. u64 record_id;
  309. u32 flags;
  310. u64 persistence_information;
  311. u8 reserved[12]; /* must be zero */
  312. };
  313. /* Section Descriptor, UEFI v2.7 sec N.2.2 */
  314. struct cper_section_descriptor {
  315. u32 section_offset; /* Offset in bytes of the
  316. * section body from the base
  317. * of the record header */
  318. u32 section_length;
  319. u16 revision; /* must be CPER_RECORD_REV */
  320. u8 validation_bits;
  321. u8 reserved; /* must be zero */
  322. u32 flags;
  323. guid_t section_type;
  324. guid_t fru_id;
  325. u32 section_severity;
  326. u8 fru_text[20];
  327. };
  328. /* Generic Processor Error Section, UEFI v2.7 sec N.2.4.1 */
  329. struct cper_sec_proc_generic {
  330. u64 validation_bits;
  331. u8 proc_type;
  332. u8 proc_isa;
  333. u8 proc_error_type;
  334. u8 operation;
  335. u8 flags;
  336. u8 level;
  337. u16 reserved;
  338. u64 cpu_version;
  339. char cpu_brand[128];
  340. u64 proc_id;
  341. u64 target_addr;
  342. u64 requestor_id;
  343. u64 responder_id;
  344. u64 ip;
  345. };
  346. /* IA32/X64 Processor Error Section, UEFI v2.7 sec N.2.4.2 */
  347. struct cper_sec_proc_ia {
  348. u64 validation_bits;
  349. u64 lapic_id;
  350. u8 cpuid[48];
  351. };
  352. /* IA32/X64 Processor Error Information Structure, UEFI v2.7 sec N.2.4.2.1 */
  353. struct cper_ia_err_info {
  354. guid_t err_type;
  355. u64 validation_bits;
  356. u64 check_info;
  357. u64 target_id;
  358. u64 requestor_id;
  359. u64 responder_id;
  360. u64 ip;
  361. };
  362. /* IA32/X64 Processor Context Information Structure, UEFI v2.7 sec N.2.4.2.2 */
  363. struct cper_ia_proc_ctx {
  364. u16 reg_ctx_type;
  365. u16 reg_arr_size;
  366. u32 msr_addr;
  367. u64 mm_reg_addr;
  368. };
  369. /* ARM Processor Error Section, UEFI v2.7 sec N.2.4.4 */
  370. struct cper_sec_proc_arm {
  371. u32 validation_bits;
  372. u16 err_info_num; /* Number of Processor Error Info */
  373. u16 context_info_num; /* Number of Processor Context Info Records*/
  374. u32 section_length;
  375. u8 affinity_level;
  376. u8 reserved[3]; /* must be zero */
  377. u64 mpidr;
  378. u64 midr;
  379. u32 running_state; /* Bit 0 set - Processor running. PSCI = 0 */
  380. u32 psci_state;
  381. };
  382. /* ARM Processor Error Information Structure, UEFI v2.7 sec N.2.4.4.1 */
  383. struct cper_arm_err_info {
  384. u8 version;
  385. u8 length;
  386. u16 validation_bits;
  387. u8 type;
  388. u16 multiple_error;
  389. u8 flags;
  390. u64 error_info;
  391. u64 virt_fault_addr;
  392. u64 physical_fault_addr;
  393. };
  394. /* ARM Processor Context Information Structure, UEFI v2.7 sec N.2.4.4.2 */
  395. struct cper_arm_ctx_info {
  396. u16 version;
  397. u16 type;
  398. u32 size;
  399. };
  400. /* Old Memory Error Section, UEFI v2.1, v2.2 */
  401. struct cper_sec_mem_err_old {
  402. u64 validation_bits;
  403. u64 error_status;
  404. u64 physical_addr;
  405. u64 physical_addr_mask;
  406. u16 node;
  407. u16 card;
  408. u16 module;
  409. u16 bank;
  410. u16 device;
  411. u16 row;
  412. u16 column;
  413. u16 bit_pos;
  414. u64 requestor_id;
  415. u64 responder_id;
  416. u64 target_id;
  417. u8 error_type;
  418. };
  419. /* Memory Error Section (UEFI >= v2.3), UEFI v2.8 sec N.2.5 */
  420. struct cper_sec_mem_err {
  421. u64 validation_bits;
  422. u64 error_status;
  423. u64 physical_addr;
  424. u64 physical_addr_mask;
  425. u16 node;
  426. u16 card;
  427. u16 module;
  428. u16 bank;
  429. u16 device;
  430. u16 row;
  431. u16 column;
  432. u16 bit_pos;
  433. u64 requestor_id;
  434. u64 responder_id;
  435. u64 target_id;
  436. u8 error_type;
  437. u8 extended;
  438. u16 rank;
  439. u16 mem_array_handle; /* "card handle" in UEFI 2.4 */
  440. u16 mem_dev_handle; /* "module handle" in UEFI 2.4 */
  441. };
  442. struct cper_mem_err_compact {
  443. u64 validation_bits;
  444. u16 node;
  445. u16 card;
  446. u16 module;
  447. u16 bank;
  448. u16 device;
  449. u16 row;
  450. u16 column;
  451. u16 bit_pos;
  452. u64 requestor_id;
  453. u64 responder_id;
  454. u64 target_id;
  455. u16 rank;
  456. u16 mem_array_handle;
  457. u16 mem_dev_handle;
  458. u8 extended;
  459. };
  460. static inline u32 cper_get_mem_extension(u64 mem_valid, u8 mem_extended)
  461. {
  462. if (!(mem_valid & CPER_MEM_VALID_ROW_EXT))
  463. return 0;
  464. return (mem_extended & CPER_MEM_EXT_ROW_MASK) << CPER_MEM_EXT_ROW_SHIFT;
  465. }
  466. /* PCI Express Error Section, UEFI v2.7 sec N.2.7 */
  467. struct cper_sec_pcie {
  468. u64 validation_bits;
  469. u32 port_type;
  470. struct {
  471. u8 minor;
  472. u8 major;
  473. u8 reserved[2];
  474. } version;
  475. u16 command;
  476. u16 status;
  477. u32 reserved;
  478. struct {
  479. u16 vendor_id;
  480. u16 device_id;
  481. u8 class_code[3];
  482. u8 function;
  483. u8 device;
  484. u16 segment;
  485. u8 bus;
  486. u8 secondary_bus;
  487. u16 slot;
  488. u8 reserved;
  489. } device_id;
  490. struct {
  491. u32 lower;
  492. u32 upper;
  493. } serial_number;
  494. struct {
  495. u16 secondary_status;
  496. u16 control;
  497. } bridge;
  498. u8 capability[60];
  499. u8 aer_info[96];
  500. };
  501. /* Firmware Error Record Reference, UEFI v2.7 sec N.2.10 */
  502. struct cper_sec_fw_err_rec_ref {
  503. u8 record_type;
  504. u8 revision;
  505. u8 reserved[6];
  506. u64 record_identifier;
  507. guid_t record_identifier_guid;
  508. };
  509. /* Reset to default packing */
  510. #pragma pack()
  511. extern const char *const cper_proc_error_type_strs[4];
  512. u64 cper_next_record_id(void);
  513. const char *cper_severity_str(unsigned int);
  514. const char *cper_mem_err_type_str(unsigned int);
  515. void cper_print_bits(const char *prefix, unsigned int bits,
  516. const char * const strs[], unsigned int strs_size);
  517. void cper_mem_err_pack(const struct cper_sec_mem_err *,
  518. struct cper_mem_err_compact *);
  519. const char *cper_mem_err_unpack(struct trace_seq *,
  520. struct cper_mem_err_compact *);
  521. void cper_print_proc_arm(const char *pfx,
  522. const struct cper_sec_proc_arm *proc);
  523. void cper_print_proc_ia(const char *pfx,
  524. const struct cper_sec_proc_ia *proc);
  525. #endif