coresight.h 17 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2012, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _LINUX_CORESIGHT_H
  6. #define _LINUX_CORESIGHT_H
  7. #include <linux/device.h>
  8. #include <linux/io.h>
  9. #include <linux/perf_event.h>
  10. #include <linux/sched.h>
  11. /* Peripheral id registers (0xFD0-0xFEC) */
  12. #define CORESIGHT_PERIPHIDR4 0xfd0
  13. #define CORESIGHT_PERIPHIDR5 0xfd4
  14. #define CORESIGHT_PERIPHIDR6 0xfd8
  15. #define CORESIGHT_PERIPHIDR7 0xfdC
  16. #define CORESIGHT_PERIPHIDR0 0xfe0
  17. #define CORESIGHT_PERIPHIDR1 0xfe4
  18. #define CORESIGHT_PERIPHIDR2 0xfe8
  19. #define CORESIGHT_PERIPHIDR3 0xfeC
  20. /* Component id registers (0xFF0-0xFFC) */
  21. #define CORESIGHT_COMPIDR0 0xff0
  22. #define CORESIGHT_COMPIDR1 0xff4
  23. #define CORESIGHT_COMPIDR2 0xff8
  24. #define CORESIGHT_COMPIDR3 0xffC
  25. #define ETM_ARCH_V3_3 0x23
  26. #define ETM_ARCH_V3_5 0x25
  27. #define PFT_ARCH_V1_0 0x30
  28. #define PFT_ARCH_V1_1 0x31
  29. #define CORESIGHT_UNLOCK 0xc5acce55
  30. extern struct bus_type coresight_bustype;
  31. enum coresight_dev_type {
  32. CORESIGHT_DEV_TYPE_NONE,
  33. CORESIGHT_DEV_TYPE_SINK,
  34. CORESIGHT_DEV_TYPE_LINK,
  35. CORESIGHT_DEV_TYPE_LINKSINK,
  36. CORESIGHT_DEV_TYPE_SOURCE,
  37. CORESIGHT_DEV_TYPE_HELPER,
  38. CORESIGHT_DEV_TYPE_ECT,
  39. };
  40. enum coresight_dev_subtype_sink {
  41. CORESIGHT_DEV_SUBTYPE_SINK_NONE,
  42. CORESIGHT_DEV_SUBTYPE_SINK_PORT,
  43. CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
  44. CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
  45. CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM,
  46. };
  47. enum coresight_dev_subtype_link {
  48. CORESIGHT_DEV_SUBTYPE_LINK_NONE,
  49. CORESIGHT_DEV_SUBTYPE_LINK_MERG,
  50. CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
  51. CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
  52. };
  53. enum coresight_dev_subtype_source {
  54. CORESIGHT_DEV_SUBTYPE_SOURCE_NONE,
  55. CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
  56. CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
  57. CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
  58. };
  59. enum coresight_dev_subtype_helper {
  60. CORESIGHT_DEV_SUBTYPE_HELPER_NONE,
  61. CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
  62. };
  63. /* Embedded Cross Trigger (ECT) sub-types */
  64. enum coresight_dev_subtype_ect {
  65. CORESIGHT_DEV_SUBTYPE_ECT_NONE,
  66. CORESIGHT_DEV_SUBTYPE_ECT_CTI,
  67. };
  68. /**
  69. * union coresight_dev_subtype - further characterisation of a type
  70. * @sink_subtype: type of sink this component is, as defined
  71. * by @coresight_dev_subtype_sink.
  72. * @link_subtype: type of link this component is, as defined
  73. * by @coresight_dev_subtype_link.
  74. * @source_subtype: type of source this component is, as defined
  75. * by @coresight_dev_subtype_source.
  76. * @helper_subtype: type of helper this component is, as defined
  77. * by @coresight_dev_subtype_helper.
  78. * @ect_subtype: type of cross trigger this component is, as
  79. * defined by @coresight_dev_subtype_ect
  80. */
  81. union coresight_dev_subtype {
  82. /* We have some devices which acts as LINK and SINK */
  83. struct {
  84. enum coresight_dev_subtype_sink sink_subtype;
  85. enum coresight_dev_subtype_link link_subtype;
  86. };
  87. enum coresight_dev_subtype_source source_subtype;
  88. enum coresight_dev_subtype_helper helper_subtype;
  89. enum coresight_dev_subtype_ect ect_subtype;
  90. };
  91. /**
  92. * struct coresight_platform_data - data harvested from the firmware
  93. * specification.
  94. *
  95. * @nr_inport: Number of elements for the input connections.
  96. * @nr_outport: Number of elements for the output connections.
  97. * @conns: Sparse array of nr_outport connections from this component.
  98. */
  99. struct coresight_platform_data {
  100. int nr_inport;
  101. int nr_outport;
  102. struct coresight_connection *conns;
  103. };
  104. /**
  105. * struct csdev_access - Abstraction of a CoreSight device access.
  106. *
  107. * @io_mem : True if the device has memory mapped I/O
  108. * @base : When io_mem == true, base address of the component
  109. * @read : Read from the given "offset" of the given instance.
  110. * @write : Write "val" to the given "offset".
  111. */
  112. struct csdev_access {
  113. bool io_mem;
  114. union {
  115. void __iomem *base;
  116. struct {
  117. u64 (*read)(u32 offset, bool relaxed, bool _64bit);
  118. void (*write)(u64 val, u32 offset, bool relaxed,
  119. bool _64bit);
  120. };
  121. };
  122. };
  123. #define CSDEV_ACCESS_IOMEM(_addr) \
  124. ((struct csdev_access) { \
  125. .io_mem = true, \
  126. .base = (_addr), \
  127. })
  128. /**
  129. * struct coresight_desc - description of a component required from drivers
  130. * @type: as defined by @coresight_dev_type.
  131. * @subtype: as defined by @coresight_dev_subtype.
  132. * @ops: generic operations for this component, as defined
  133. * by @coresight_ops.
  134. * @pdata: platform data collected from DT.
  135. * @dev: The device entity associated to this component.
  136. * @groups: operations specific to this component. These will end up
  137. * in the component's sysfs sub-directory.
  138. * @name: name for the coresight device, also shown under sysfs.
  139. * @access: Describe access to the device
  140. */
  141. struct coresight_desc {
  142. enum coresight_dev_type type;
  143. union coresight_dev_subtype subtype;
  144. const struct coresight_ops *ops;
  145. struct coresight_platform_data *pdata;
  146. struct device *dev;
  147. const struct attribute_group **groups;
  148. const char *name;
  149. struct csdev_access access;
  150. };
  151. /**
  152. * struct coresight_connection - representation of a single connection
  153. * @outport: a connection's output port number.
  154. * @child_port: remote component's port number @output is connected to.
  155. * @chid_fwnode: remote component's fwnode handle.
  156. * @child_dev: a @coresight_device representation of the component
  157. connected to @outport.
  158. * @link: Representation of the connection as a sysfs link.
  159. */
  160. struct coresight_connection {
  161. int outport;
  162. int child_port;
  163. struct fwnode_handle *child_fwnode;
  164. struct coresight_device *child_dev;
  165. struct coresight_sysfs_link *link;
  166. };
  167. /**
  168. * struct coresight_sysfs_link - representation of a connection in sysfs.
  169. * @orig: Originating (master) coresight device for the link.
  170. * @orig_name: Name to use for the link orig->target.
  171. * @target: Target (slave) coresight device for the link.
  172. * @target_name: Name to use for the link target->orig.
  173. */
  174. struct coresight_sysfs_link {
  175. struct coresight_device *orig;
  176. const char *orig_name;
  177. struct coresight_device *target;
  178. const char *target_name;
  179. };
  180. /**
  181. * struct coresight_device - representation of a device as used by the framework
  182. * @pdata: Platform data with device connections associated to this device.
  183. * @type: as defined by @coresight_dev_type.
  184. * @subtype: as defined by @coresight_dev_subtype.
  185. * @ops: generic operations for this component, as defined
  186. * by @coresight_ops.
  187. * @access: Device i/o access abstraction for this device.
  188. * @dev: The device entity associated to this component.
  189. * @refcnt: keep track of what is in use.
  190. * @orphan: true if the component has connections that haven't been linked.
  191. * @enable: 'true' if component is currently part of an active path.
  192. * @activated: 'true' only if a _sink_ has been activated. A sink can be
  193. * activated but not yet enabled. Enabling for a _sink_
  194. * happens when a source has been selected and a path is enabled
  195. * from source to that sink.
  196. * @ea: Device attribute for sink representation under PMU directory.
  197. * @def_sink: cached reference to default sink found for this device.
  198. * @ect_dev: Associated cross trigger device. Not part of the trace data
  199. * path or connections.
  200. * @nr_links: number of sysfs links created to other components from this
  201. * device. These will appear in the "connections" group.
  202. * @has_conns_grp: Have added a "connections" group for sysfs links.
  203. */
  204. struct coresight_device {
  205. struct coresight_platform_data *pdata;
  206. enum coresight_dev_type type;
  207. union coresight_dev_subtype subtype;
  208. const struct coresight_ops *ops;
  209. struct csdev_access access;
  210. struct device dev;
  211. atomic_t *refcnt;
  212. bool orphan;
  213. bool enable; /* true only if configured as part of a path */
  214. /* sink specific fields */
  215. bool activated; /* true only if a sink is part of a path */
  216. struct dev_ext_attribute *ea;
  217. struct coresight_device *def_sink;
  218. /* cross trigger handling */
  219. struct coresight_device *ect_dev;
  220. /* sysfs links between components */
  221. int nr_links;
  222. bool has_conns_grp;
  223. bool ect_enabled; /* true only if associated ect device is enabled */
  224. };
  225. /*
  226. * coresight_dev_list - Mapping for devices to "name" index for device
  227. * names.
  228. *
  229. * @nr_idx: Number of entries already allocated.
  230. * @pfx: Prefix pattern for device name.
  231. * @fwnode_list: Array of fwnode_handles associated with each allocated
  232. * index, upto nr_idx entries.
  233. */
  234. struct coresight_dev_list {
  235. int nr_idx;
  236. const char *pfx;
  237. struct fwnode_handle **fwnode_list;
  238. };
  239. #define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \
  240. static struct coresight_dev_list (var) = { \
  241. .pfx = dev_pfx, \
  242. .nr_idx = 0, \
  243. .fwnode_list = NULL, \
  244. }
  245. #define to_coresight_device(d) container_of(d, struct coresight_device, dev)
  246. #define source_ops(csdev) csdev->ops->source_ops
  247. #define sink_ops(csdev) csdev->ops->sink_ops
  248. #define link_ops(csdev) csdev->ops->link_ops
  249. #define helper_ops(csdev) csdev->ops->helper_ops
  250. #define ect_ops(csdev) csdev->ops->ect_ops
  251. /**
  252. * struct coresight_ops_sink - basic operations for a sink
  253. * Operations available for sinks
  254. * @enable: enables the sink.
  255. * @disable: disables the sink.
  256. * @alloc_buffer: initialises perf's ring buffer for trace collection.
  257. * @free_buffer: release memory allocated in @get_config.
  258. * @update_buffer: update buffer pointers after a trace session.
  259. */
  260. struct coresight_ops_sink {
  261. int (*enable)(struct coresight_device *csdev, u32 mode, void *data);
  262. int (*disable)(struct coresight_device *csdev);
  263. void *(*alloc_buffer)(struct coresight_device *csdev,
  264. struct perf_event *event, void **pages,
  265. int nr_pages, bool overwrite);
  266. void (*free_buffer)(void *config);
  267. unsigned long (*update_buffer)(struct coresight_device *csdev,
  268. struct perf_output_handle *handle,
  269. void *sink_config);
  270. };
  271. /**
  272. * struct coresight_ops_link - basic operations for a link
  273. * Operations available for links.
  274. * @enable: enables flow between iport and oport.
  275. * @disable: disables flow between iport and oport.
  276. */
  277. struct coresight_ops_link {
  278. int (*enable)(struct coresight_device *csdev, int iport, int oport);
  279. void (*disable)(struct coresight_device *csdev, int iport, int oport);
  280. };
  281. /**
  282. * struct coresight_ops_source - basic operations for a source
  283. * Operations available for sources.
  284. * @cpu_id: returns the value of the CPU number this component
  285. * is associated to.
  286. * @trace_id: returns the value of the component's trace ID as known
  287. * to the HW.
  288. * @enable: enables tracing for a source.
  289. * @disable: disables tracing for a source.
  290. */
  291. struct coresight_ops_source {
  292. int (*cpu_id)(struct coresight_device *csdev);
  293. int (*trace_id)(struct coresight_device *csdev);
  294. int (*enable)(struct coresight_device *csdev,
  295. struct perf_event *event, u32 mode);
  296. void (*disable)(struct coresight_device *csdev,
  297. struct perf_event *event);
  298. };
  299. /**
  300. * struct coresight_ops_helper - Operations for a helper device.
  301. *
  302. * All operations could pass in a device specific data, which could
  303. * help the helper device to determine what to do.
  304. *
  305. * @enable : Enable the device
  306. * @disable : Disable the device
  307. */
  308. struct coresight_ops_helper {
  309. int (*enable)(struct coresight_device *csdev, void *data);
  310. int (*disable)(struct coresight_device *csdev, void *data);
  311. };
  312. /**
  313. * struct coresight_ops_ect - Ops for an embedded cross trigger device
  314. *
  315. * @enable : Enable the device
  316. * @disable : Disable the device
  317. */
  318. struct coresight_ops_ect {
  319. int (*enable)(struct coresight_device *csdev);
  320. int (*disable)(struct coresight_device *csdev);
  321. };
  322. struct coresight_ops {
  323. const struct coresight_ops_sink *sink_ops;
  324. const struct coresight_ops_link *link_ops;
  325. const struct coresight_ops_source *source_ops;
  326. const struct coresight_ops_helper *helper_ops;
  327. const struct coresight_ops_ect *ect_ops;
  328. };
  329. #if IS_ENABLED(CONFIG_CORESIGHT)
  330. static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa,
  331. u32 offset)
  332. {
  333. if (likely(csa->io_mem))
  334. return readl_relaxed(csa->base + offset);
  335. return csa->read(offset, true, false);
  336. }
  337. static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset)
  338. {
  339. if (likely(csa->io_mem))
  340. return readl(csa->base + offset);
  341. return csa->read(offset, false, false);
  342. }
  343. static inline void csdev_access_relaxed_write32(struct csdev_access *csa,
  344. u32 val, u32 offset)
  345. {
  346. if (likely(csa->io_mem))
  347. writel_relaxed(val, csa->base + offset);
  348. else
  349. csa->write(val, offset, true, false);
  350. }
  351. static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset)
  352. {
  353. if (likely(csa->io_mem))
  354. writel(val, csa->base + offset);
  355. else
  356. csa->write(val, offset, false, false);
  357. }
  358. #ifdef CONFIG_64BIT
  359. static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
  360. u32 offset)
  361. {
  362. if (likely(csa->io_mem))
  363. return readq_relaxed(csa->base + offset);
  364. return csa->read(offset, true, true);
  365. }
  366. static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
  367. {
  368. if (likely(csa->io_mem))
  369. return readq(csa->base + offset);
  370. return csa->read(offset, false, true);
  371. }
  372. static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
  373. u64 val, u32 offset)
  374. {
  375. if (likely(csa->io_mem))
  376. writeq_relaxed(val, csa->base + offset);
  377. else
  378. csa->write(val, offset, true, true);
  379. }
  380. static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
  381. {
  382. if (likely(csa->io_mem))
  383. writeq(val, csa->base + offset);
  384. else
  385. csa->write(val, offset, false, true);
  386. }
  387. #else /* !CONFIG_64BIT */
  388. static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
  389. u32 offset)
  390. {
  391. WARN_ON(1);
  392. return 0;
  393. }
  394. static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
  395. {
  396. WARN_ON(1);
  397. return 0;
  398. }
  399. static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
  400. u64 val, u32 offset)
  401. {
  402. WARN_ON(1);
  403. }
  404. static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
  405. {
  406. WARN_ON(1);
  407. }
  408. #endif /* CONFIG_64BIT */
  409. static inline bool coresight_is_percpu_source(struct coresight_device *csdev)
  410. {
  411. return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) &&
  412. (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC);
  413. }
  414. static inline bool coresight_is_percpu_sink(struct coresight_device *csdev)
  415. {
  416. return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) &&
  417. (csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM);
  418. }
  419. extern struct coresight_device *
  420. coresight_register(struct coresight_desc *desc);
  421. extern void coresight_unregister(struct coresight_device *csdev);
  422. extern int coresight_enable(struct coresight_device *csdev);
  423. extern void coresight_disable(struct coresight_device *csdev);
  424. extern int coresight_timeout(struct csdev_access *csa, u32 offset,
  425. int position, int value);
  426. extern int coresight_claim_device(struct coresight_device *csdev);
  427. extern int coresight_claim_device_unlocked(struct coresight_device *csdev);
  428. extern void coresight_disclaim_device(struct coresight_device *csdev);
  429. extern void coresight_disclaim_device_unlocked(struct coresight_device *csdev);
  430. extern char *coresight_alloc_device_name(struct coresight_dev_list *devs,
  431. struct device *dev);
  432. extern bool coresight_loses_context_with_cpu(struct device *dev);
  433. u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset);
  434. u32 coresight_read32(struct coresight_device *csdev, u32 offset);
  435. void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset);
  436. void coresight_relaxed_write32(struct coresight_device *csdev,
  437. u32 val, u32 offset);
  438. u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset);
  439. u64 coresight_read64(struct coresight_device *csdev, u32 offset);
  440. void coresight_relaxed_write64(struct coresight_device *csdev,
  441. u64 val, u32 offset);
  442. void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset);
  443. #else
  444. static inline struct coresight_device *
  445. coresight_register(struct coresight_desc *desc) { return NULL; }
  446. static inline void coresight_unregister(struct coresight_device *csdev) {}
  447. static inline int
  448. coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
  449. static inline void coresight_disable(struct coresight_device *csdev) {}
  450. static inline int coresight_timeout(struct csdev_access *csa, u32 offset,
  451. int position, int value)
  452. {
  453. return 1;
  454. }
  455. static inline int coresight_claim_device_unlocked(struct coresight_device *csdev)
  456. {
  457. return -EINVAL;
  458. }
  459. static inline int coresight_claim_device(struct coresight_device *csdev)
  460. {
  461. return -EINVAL;
  462. }
  463. static inline void coresight_disclaim_device(struct coresight_device *csdev) {}
  464. static inline void coresight_disclaim_device_unlocked(struct coresight_device *csdev) {}
  465. static inline bool coresight_loses_context_with_cpu(struct device *dev)
  466. {
  467. return false;
  468. }
  469. static inline u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset)
  470. {
  471. WARN_ON_ONCE(1);
  472. return 0;
  473. }
  474. static inline u32 coresight_read32(struct coresight_device *csdev, u32 offset)
  475. {
  476. WARN_ON_ONCE(1);
  477. return 0;
  478. }
  479. static inline void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset)
  480. {
  481. }
  482. static inline void coresight_relaxed_write32(struct coresight_device *csdev,
  483. u32 val, u32 offset)
  484. {
  485. }
  486. static inline u64 coresight_relaxed_read64(struct coresight_device *csdev,
  487. u32 offset)
  488. {
  489. WARN_ON_ONCE(1);
  490. return 0;
  491. }
  492. static inline u64 coresight_read64(struct coresight_device *csdev, u32 offset)
  493. {
  494. WARN_ON_ONCE(1);
  495. return 0;
  496. }
  497. static inline void coresight_relaxed_write64(struct coresight_device *csdev,
  498. u64 val, u32 offset)
  499. {
  500. }
  501. static inline void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset)
  502. {
  503. }
  504. #endif /* IS_ENABLED(CONFIG_CORESIGHT) */
  505. extern int coresight_get_cpu(struct device *dev);
  506. struct coresight_platform_data *coresight_get_platform_data(struct device *dev);
  507. #endif /* _LINUX_COREISGHT_H */