coresight-pmu.h 1.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright(C) 2015 Linaro Limited. All rights reserved.
  4. * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
  5. */
  6. #ifndef _LINUX_CORESIGHT_PMU_H
  7. #define _LINUX_CORESIGHT_PMU_H
  8. #define CORESIGHT_ETM_PMU_NAME "cs_etm"
  9. #define CORESIGHT_ETM_PMU_SEED 0x10
  10. /*
  11. * Below are the definition of bit offsets for perf option, and works as
  12. * arbitrary values for all ETM versions.
  13. *
  14. * Most of them are orignally from ETMv3.5/PTM's ETMCR config, therefore,
  15. * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and
  16. * directly use below macros as config bits.
  17. */
  18. #define ETM_OPT_CYCACC 12
  19. #define ETM_OPT_CTXTID 14
  20. #define ETM_OPT_CTXTID2 15
  21. #define ETM_OPT_TS 28
  22. #define ETM_OPT_RETSTK 29
  23. /* ETMv4 CONFIGR programming bits for the ETM OPTs */
  24. #define ETM4_CFG_BIT_CYCACC 4
  25. #define ETM4_CFG_BIT_CTXTID 6
  26. #define ETM4_CFG_BIT_VMID 7
  27. #define ETM4_CFG_BIT_TS 11
  28. #define ETM4_CFG_BIT_RETSTK 12
  29. #define ETM4_CFG_BIT_VMID_OPT 15
  30. static inline int coresight_get_trace_id(int cpu)
  31. {
  32. /*
  33. * A trace ID of value 0 is invalid, so let's start at some
  34. * random value that fits in 7 bits and go from there. Since
  35. * the common convention is to have data trace IDs be I(N) + 1,
  36. * set instruction trace IDs as a function of the CPU number.
  37. */
  38. return (CORESIGHT_ETM_PMU_SEED + (cpu * 2));
  39. }
  40. #endif