clk-provider.h 53 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
  4. * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
  5. */
  6. #ifndef __LINUX_CLK_PROVIDER_H
  7. #define __LINUX_CLK_PROVIDER_H
  8. #include <linux/of.h>
  9. #include <linux/of_clk.h>
  10. /*
  11. * flags used across common struct clk. these flags should only affect the
  12. * top-level framework. custom flags for dealing with hardware specifics
  13. * belong in struct clk_foo
  14. *
  15. * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
  16. */
  17. #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
  18. #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
  19. #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
  20. #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
  21. /* unused */
  22. /* unused */
  23. #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
  24. #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
  25. #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
  26. #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
  27. #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
  28. #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
  29. /* parents need enable during gate/ungate, set rate and re-parent */
  30. #define CLK_OPS_PARENT_ENABLE BIT(12)
  31. /* duty cycle call may be forwarded to the parent clock */
  32. #define CLK_DUTY_CYCLE_PARENT BIT(13)
  33. #define CLK_DONT_HOLD_STATE BIT(14) /* Don't hold state */
  34. struct clk;
  35. struct clk_hw;
  36. struct clk_core;
  37. struct dentry;
  38. /**
  39. * struct clk_rate_request - Structure encoding the clk constraints that
  40. * a clock user might require.
  41. *
  42. * @rate: Requested clock rate. This field will be adjusted by
  43. * clock drivers according to hardware capabilities.
  44. * @min_rate: Minimum rate imposed by clk users.
  45. * @max_rate: Maximum rate imposed by clk users.
  46. * @best_parent_rate: The best parent rate a parent can provide to fulfill the
  47. * requested constraints.
  48. * @best_parent_hw: The most appropriate parent clock that fulfills the
  49. * requested constraints.
  50. *
  51. */
  52. struct clk_rate_request {
  53. unsigned long rate;
  54. unsigned long min_rate;
  55. unsigned long max_rate;
  56. unsigned long best_parent_rate;
  57. struct clk_hw *best_parent_hw;
  58. };
  59. /**
  60. * struct clk_duty - Struture encoding the duty cycle ratio of a clock
  61. *
  62. * @num: Numerator of the duty cycle ratio
  63. * @den: Denominator of the duty cycle ratio
  64. */
  65. struct clk_duty {
  66. unsigned int num;
  67. unsigned int den;
  68. };
  69. /**
  70. * struct clk_ops - Callback operations for hardware clocks; these are to
  71. * be provided by the clock implementation, and will be called by drivers
  72. * through the clk_* api.
  73. *
  74. * @prepare: Prepare the clock for enabling. This must not return until
  75. * the clock is fully prepared, and it's safe to call clk_enable.
  76. * This callback is intended to allow clock implementations to
  77. * do any initialisation that may sleep. Called with
  78. * prepare_lock held.
  79. *
  80. * @unprepare: Release the clock from its prepared state. This will typically
  81. * undo any work done in the @prepare callback. Called with
  82. * prepare_lock held.
  83. *
  84. * @is_prepared: Queries the hardware to determine if the clock is prepared.
  85. * This function is allowed to sleep. Optional, if this op is not
  86. * set then the prepare count will be used.
  87. *
  88. * @unprepare_unused: Unprepare the clock atomically. Only called from
  89. * clk_disable_unused for prepare clocks with special needs.
  90. * Called with prepare mutex held. This function may sleep.
  91. *
  92. * @enable: Enable the clock atomically. This must not return until the
  93. * clock is generating a valid clock signal, usable by consumer
  94. * devices. Called with enable_lock held. This function must not
  95. * sleep.
  96. *
  97. * @disable: Disable the clock atomically. Called with enable_lock held.
  98. * This function must not sleep.
  99. *
  100. * @is_enabled: Queries the hardware to determine if the clock is enabled.
  101. * This function must not sleep. Optional, if this op is not
  102. * set then the enable count will be used.
  103. *
  104. * @disable_unused: Disable the clock atomically. Only called from
  105. * clk_disable_unused for gate clocks with special needs.
  106. * Called with enable_lock held. This function must not
  107. * sleep.
  108. *
  109. * @save_context: Save the context of the clock in prepration for poweroff.
  110. *
  111. * @restore_context: Restore the context of the clock after a restoration
  112. * of power.
  113. *
  114. * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
  115. * parent rate is an input parameter. It is up to the caller to
  116. * ensure that the prepare_mutex is held across this call.
  117. * Returns the calculated rate. Optional, but recommended - if
  118. * this op is not set then clock rate will be initialized to 0.
  119. *
  120. * @round_rate: Given a target rate as input, returns the closest rate actually
  121. * supported by the clock. The parent rate is an input/output
  122. * parameter.
  123. *
  124. * @determine_rate: Given a target rate as input, returns the closest rate
  125. * actually supported by the clock, and optionally the parent clock
  126. * that should be used to provide the clock rate.
  127. *
  128. * @set_parent: Change the input source of this clock; for clocks with multiple
  129. * possible parents specify a new parent by passing in the index
  130. * as a u8 corresponding to the parent in either the .parent_names
  131. * or .parents arrays. This function in affect translates an
  132. * array index into the value programmed into the hardware.
  133. * Returns 0 on success, -EERROR otherwise.
  134. *
  135. * @get_parent: Queries the hardware to determine the parent of a clock. The
  136. * return value is a u8 which specifies the index corresponding to
  137. * the parent clock. This index can be applied to either the
  138. * .parent_names or .parents arrays. In short, this function
  139. * translates the parent value read from hardware into an array
  140. * index. Currently only called when the clock is initialized by
  141. * __clk_init. This callback is mandatory for clocks with
  142. * multiple parents. It is optional (and unnecessary) for clocks
  143. * with 0 or 1 parents.
  144. *
  145. * @set_rate: Change the rate of this clock. The requested rate is specified
  146. * by the second argument, which should typically be the return
  147. * of .round_rate call. The third argument gives the parent rate
  148. * which is likely helpful for most .set_rate implementation.
  149. * Returns 0 on success, -EERROR otherwise.
  150. *
  151. * @set_rate_and_parent: Change the rate and the parent of this clock. The
  152. * requested rate is specified by the second argument, which
  153. * should typically be the return of .round_rate call. The
  154. * third argument gives the parent rate which is likely helpful
  155. * for most .set_rate_and_parent implementation. The fourth
  156. * argument gives the parent index. This callback is optional (and
  157. * unnecessary) for clocks with 0 or 1 parents as well as
  158. * for clocks that can tolerate switching the rate and the parent
  159. * separately via calls to .set_parent and .set_rate.
  160. * Returns 0 on success, -EERROR otherwise.
  161. *
  162. * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
  163. * is expressed in ppb (parts per billion). The parent accuracy is
  164. * an input parameter.
  165. * Returns the calculated accuracy. Optional - if this op is not
  166. * set then clock accuracy will be initialized to parent accuracy
  167. * or 0 (perfect clock) if clock has no parent.
  168. *
  169. * @get_phase: Queries the hardware to get the current phase of a clock.
  170. * Returned values are 0-359 degrees on success, negative
  171. * error codes on failure.
  172. *
  173. * @set_phase: Shift the phase this clock signal in degrees specified
  174. * by the second argument. Valid values for degrees are
  175. * 0-359. Return 0 on success, otherwise -EERROR.
  176. *
  177. * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
  178. * of a clock. Returned values denominator cannot be 0 and must be
  179. * superior or equal to the numerator.
  180. *
  181. * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
  182. * the numerator (2nd argurment) and denominator (3rd argument).
  183. * Argument must be a valid ratio (denominator > 0
  184. * and >= numerator) Return 0 on success, otherwise -EERROR.
  185. *
  186. * @init: Perform platform-specific initialization magic.
  187. * This is not used by any of the basic clock types.
  188. * This callback exist for HW which needs to perform some
  189. * initialisation magic for CCF to get an accurate view of the
  190. * clock. It may also be used dynamic resource allocation is
  191. * required. It shall not used to deal with clock parameters,
  192. * such as rate or parents.
  193. * Returns 0 on success, -EERROR otherwise.
  194. *
  195. * @terminate: Free any resource allocated by init.
  196. *
  197. * @debug_init: Set up type-specific debugfs entries for this clock. This
  198. * is called once, after the debugfs directory entry for this
  199. * clock has been created. The dentry pointer representing that
  200. * directory is provided as an argument. Called with
  201. * prepare_lock held. Returns 0 on success, -EERROR otherwise.
  202. *
  203. * @pre_rate_change: Optional callback for a clock to fulfill its rate
  204. * change requirements before any rate change has occurred in
  205. * its clock tree. Returns 0 on success, -EERROR otherwise.
  206. *
  207. * @post_rate_change: Optional callback for a clock to clean up any
  208. * requirements that were needed while the clock and its tree
  209. * was changing states. Returns 0 on success, -EERROR otherwise.
  210. *
  211. * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
  212. * implementations to split any work between atomic (enable) and sleepable
  213. * (prepare) contexts. If enabling a clock requires code that might sleep,
  214. * this must be done in clk_prepare. Clock enable code that will never be
  215. * called in a sleepable context may be implemented in clk_enable.
  216. *
  217. * Typically, drivers will call clk_prepare when a clock may be needed later
  218. * (eg. when a device is opened), and clk_enable when the clock is actually
  219. * required (eg. from an interrupt). Note that clk_prepare MUST have been
  220. * called before clk_enable.
  221. */
  222. struct clk_ops {
  223. int (*prepare)(struct clk_hw *hw);
  224. void (*unprepare)(struct clk_hw *hw);
  225. int (*is_prepared)(struct clk_hw *hw);
  226. void (*unprepare_unused)(struct clk_hw *hw);
  227. int (*enable)(struct clk_hw *hw);
  228. void (*disable)(struct clk_hw *hw);
  229. int (*is_enabled)(struct clk_hw *hw);
  230. void (*disable_unused)(struct clk_hw *hw);
  231. int (*save_context)(struct clk_hw *hw);
  232. void (*restore_context)(struct clk_hw *hw);
  233. unsigned long (*recalc_rate)(struct clk_hw *hw,
  234. unsigned long parent_rate);
  235. long (*round_rate)(struct clk_hw *hw, unsigned long rate,
  236. unsigned long *parent_rate);
  237. int (*determine_rate)(struct clk_hw *hw,
  238. struct clk_rate_request *req);
  239. int (*set_parent)(struct clk_hw *hw, u8 index);
  240. u8 (*get_parent)(struct clk_hw *hw);
  241. int (*set_rate)(struct clk_hw *hw, unsigned long rate,
  242. unsigned long parent_rate);
  243. int (*set_rate_and_parent)(struct clk_hw *hw,
  244. unsigned long rate,
  245. unsigned long parent_rate, u8 index);
  246. unsigned long (*recalc_accuracy)(struct clk_hw *hw,
  247. unsigned long parent_accuracy);
  248. int (*get_phase)(struct clk_hw *hw);
  249. int (*set_phase)(struct clk_hw *hw, int degrees);
  250. int (*get_duty_cycle)(struct clk_hw *hw,
  251. struct clk_duty *duty);
  252. int (*set_duty_cycle)(struct clk_hw *hw,
  253. struct clk_duty *duty);
  254. int (*init)(struct clk_hw *hw);
  255. void (*terminate)(struct clk_hw *hw);
  256. void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
  257. int (*pre_rate_change)(struct clk_hw *hw,
  258. unsigned long rate,
  259. unsigned long new_rate);
  260. int (*post_rate_change)(struct clk_hw *hw,
  261. unsigned long old_rate,
  262. unsigned long rate);
  263. };
  264. /**
  265. * struct clk_parent_data - clk parent information
  266. * @hw: parent clk_hw pointer (used for clk providers with internal clks)
  267. * @fw_name: parent name local to provider registering clk
  268. * @name: globally unique parent name (used as a fallback)
  269. * @index: parent index local to provider registering clk (if @fw_name absent)
  270. */
  271. struct clk_parent_data {
  272. const struct clk_hw *hw;
  273. const char *fw_name;
  274. const char *name;
  275. int index;
  276. };
  277. /**
  278. * struct clk_init_data - holds init data that's common to all clocks and is
  279. * shared between the clock provider and the common clock framework.
  280. *
  281. * @name: clock name
  282. * @ops: operations this clock supports
  283. * @parent_names: array of string names for all possible parents
  284. * @parent_data: array of parent data for all possible parents (when some
  285. * parents are external to the clk controller)
  286. * @parent_hws: array of pointers to all possible parents (when all parents
  287. * are internal to the clk controller)
  288. * @num_parents: number of possible parents
  289. * @flags: framework-level hints and quirks
  290. */
  291. struct clk_init_data {
  292. const char *name;
  293. const struct clk_ops *ops;
  294. /* Only one of the following three should be assigned */
  295. const char * const *parent_names;
  296. const struct clk_parent_data *parent_data;
  297. const struct clk_hw **parent_hws;
  298. u8 num_parents;
  299. unsigned long flags;
  300. };
  301. /**
  302. * struct clk_hw - handle for traversing from a struct clk to its corresponding
  303. * hardware-specific structure. struct clk_hw should be declared within struct
  304. * clk_foo and then referenced by the struct clk instance that uses struct
  305. * clk_foo's clk_ops
  306. *
  307. * @core: pointer to the struct clk_core instance that points back to this
  308. * struct clk_hw instance
  309. *
  310. * @clk: pointer to the per-user struct clk instance that can be used to call
  311. * into the clk API
  312. *
  313. * @init: pointer to struct clk_init_data that contains the init data shared
  314. * with the common clock framework. This pointer will be set to NULL once
  315. * a clk_register() variant is called on this clk_hw pointer.
  316. */
  317. struct clk_hw {
  318. struct clk_core *core;
  319. struct clk *clk;
  320. const struct clk_init_data *init;
  321. };
  322. /*
  323. * DOC: Basic clock implementations common to many platforms
  324. *
  325. * Each basic clock hardware type is comprised of a structure describing the
  326. * clock hardware, implementations of the relevant callbacks in struct clk_ops,
  327. * unique flags for that hardware type, a registration function and an
  328. * alternative macro for static initialization
  329. */
  330. /**
  331. * struct clk_fixed_rate - fixed-rate clock
  332. * @hw: handle between common and hardware-specific interfaces
  333. * @fixed_rate: constant frequency of clock
  334. * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)
  335. * @flags: hardware specific flags
  336. *
  337. * Flags:
  338. * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
  339. * instead of what's set in @fixed_accuracy.
  340. */
  341. struct clk_fixed_rate {
  342. struct clk_hw hw;
  343. unsigned long fixed_rate;
  344. unsigned long fixed_accuracy;
  345. unsigned long flags;
  346. };
  347. #define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)
  348. extern const struct clk_ops clk_fixed_rate_ops;
  349. struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
  350. struct device_node *np, const char *name,
  351. const char *parent_name, const struct clk_hw *parent_hw,
  352. const struct clk_parent_data *parent_data, unsigned long flags,
  353. unsigned long fixed_rate, unsigned long fixed_accuracy,
  354. unsigned long clk_fixed_flags);
  355. struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
  356. const char *parent_name, unsigned long flags,
  357. unsigned long fixed_rate);
  358. /**
  359. * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
  360. * framework
  361. * @dev: device that is registering this clock
  362. * @name: name of this clock
  363. * @parent_name: name of clock's parent
  364. * @flags: framework-specific flags
  365. * @fixed_rate: non-adjustable clock rate
  366. */
  367. #define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
  368. __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
  369. NULL, (flags), (fixed_rate), 0, 0)
  370. /**
  371. * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
  372. * the clock framework
  373. * @dev: device that is registering this clock
  374. * @name: name of this clock
  375. * @parent_hw: pointer to parent clk
  376. * @flags: framework-specific flags
  377. * @fixed_rate: non-adjustable clock rate
  378. */
  379. #define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \
  380. fixed_rate) \
  381. __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
  382. NULL, (flags), (fixed_rate), 0, 0)
  383. /**
  384. * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
  385. * the clock framework
  386. * @dev: device that is registering this clock
  387. * @name: name of this clock
  388. * @parent_data: parent clk data
  389. * @flags: framework-specific flags
  390. * @fixed_rate: non-adjustable clock rate
  391. */
  392. #define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags, \
  393. fixed_rate) \
  394. __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
  395. (parent_data), (flags), (fixed_rate), 0, \
  396. 0)
  397. /**
  398. * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
  399. * the clock framework
  400. * @dev: device that is registering this clock
  401. * @name: name of this clock
  402. * @parent_name: name of clock's parent
  403. * @flags: framework-specific flags
  404. * @fixed_rate: non-adjustable clock rate
  405. * @fixed_accuracy: non-adjustable clock accuracy
  406. */
  407. #define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \
  408. flags, fixed_rate, \
  409. fixed_accuracy) \
  410. __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \
  411. NULL, NULL, (flags), (fixed_rate), \
  412. (fixed_accuracy), 0)
  413. /**
  414. * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
  415. * clock with the clock framework
  416. * @dev: device that is registering this clock
  417. * @name: name of this clock
  418. * @parent_hw: pointer to parent clk
  419. * @flags: framework-specific flags
  420. * @fixed_rate: non-adjustable clock rate
  421. * @fixed_accuracy: non-adjustable clock accuracy
  422. */
  423. #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \
  424. parent_hw, flags, fixed_rate, fixed_accuracy) \
  425. __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw) \
  426. NULL, NULL, (flags), (fixed_rate), \
  427. (fixed_accuracy), 0)
  428. /**
  429. * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
  430. * clock with the clock framework
  431. * @dev: device that is registering this clock
  432. * @name: name of this clock
  433. * @parent_name: name of clock's parent
  434. * @flags: framework-specific flags
  435. * @fixed_rate: non-adjustable clock rate
  436. * @fixed_accuracy: non-adjustable clock accuracy
  437. */
  438. #define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \
  439. parent_data, flags, fixed_rate, fixed_accuracy) \
  440. __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
  441. (parent_data), NULL, (flags), \
  442. (fixed_rate), (fixed_accuracy), 0)
  443. void clk_unregister_fixed_rate(struct clk *clk);
  444. void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
  445. void of_fixed_clk_setup(struct device_node *np);
  446. /**
  447. * struct clk_gate - gating clock
  448. *
  449. * @hw: handle between common and hardware-specific interfaces
  450. * @reg: register controlling gate
  451. * @bit_idx: single bit controlling gate
  452. * @flags: hardware-specific flags
  453. * @lock: register lock
  454. *
  455. * Clock which can gate its output. Implements .enable & .disable
  456. *
  457. * Flags:
  458. * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
  459. * enable the clock. Setting this flag does the opposite: setting the bit
  460. * disable the clock and clearing it enables the clock
  461. * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
  462. * of this register, and mask of gate bits are in higher 16-bit of this
  463. * register. While setting the gate bits, higher 16-bit should also be
  464. * updated to indicate changing gate bits.
  465. * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
  466. * the gate register. Setting this flag makes the register accesses big
  467. * endian.
  468. */
  469. struct clk_gate {
  470. struct clk_hw hw;
  471. void __iomem *reg;
  472. u8 bit_idx;
  473. u8 flags;
  474. spinlock_t *lock;
  475. };
  476. #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
  477. #define CLK_GATE_SET_TO_DISABLE BIT(0)
  478. #define CLK_GATE_HIWORD_MASK BIT(1)
  479. #define CLK_GATE_BIG_ENDIAN BIT(2)
  480. extern const struct clk_ops clk_gate_ops;
  481. struct clk_hw *__clk_hw_register_gate(struct device *dev,
  482. struct device_node *np, const char *name,
  483. const char *parent_name, const struct clk_hw *parent_hw,
  484. const struct clk_parent_data *parent_data,
  485. unsigned long flags,
  486. void __iomem *reg, u8 bit_idx,
  487. u8 clk_gate_flags, spinlock_t *lock);
  488. struct clk *clk_register_gate(struct device *dev, const char *name,
  489. const char *parent_name, unsigned long flags,
  490. void __iomem *reg, u8 bit_idx,
  491. u8 clk_gate_flags, spinlock_t *lock);
  492. /**
  493. * clk_hw_register_gate - register a gate clock with the clock framework
  494. * @dev: device that is registering this clock
  495. * @name: name of this clock
  496. * @parent_name: name of this clock's parent
  497. * @flags: framework-specific flags for this clock
  498. * @reg: register address to control gating of this clock
  499. * @bit_idx: which bit in the register controls gating of this clock
  500. * @clk_gate_flags: gate-specific flags for this clock
  501. * @lock: shared register lock for this clock
  502. */
  503. #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \
  504. clk_gate_flags, lock) \
  505. __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
  506. NULL, (flags), (reg), (bit_idx), \
  507. (clk_gate_flags), (lock))
  508. /**
  509. * clk_hw_register_gate_parent_hw - register a gate clock with the clock
  510. * framework
  511. * @dev: device that is registering this clock
  512. * @name: name of this clock
  513. * @parent_hw: pointer to parent clk
  514. * @flags: framework-specific flags for this clock
  515. * @reg: register address to control gating of this clock
  516. * @bit_idx: which bit in the register controls gating of this clock
  517. * @clk_gate_flags: gate-specific flags for this clock
  518. * @lock: shared register lock for this clock
  519. */
  520. #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \
  521. bit_idx, clk_gate_flags, lock) \
  522. __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
  523. NULL, (flags), (reg), (bit_idx), \
  524. (clk_gate_flags), (lock))
  525. /**
  526. * clk_hw_register_gate_parent_data - register a gate clock with the clock
  527. * framework
  528. * @dev: device that is registering this clock
  529. * @name: name of this clock
  530. * @parent_data: parent clk data
  531. * @flags: framework-specific flags for this clock
  532. * @reg: register address to control gating of this clock
  533. * @bit_idx: which bit in the register controls gating of this clock
  534. * @clk_gate_flags: gate-specific flags for this clock
  535. * @lock: shared register lock for this clock
  536. */
  537. #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \
  538. bit_idx, clk_gate_flags, lock) \
  539. __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
  540. (flags), (reg), (bit_idx), \
  541. (clk_gate_flags), (lock))
  542. void clk_unregister_gate(struct clk *clk);
  543. void clk_hw_unregister_gate(struct clk_hw *hw);
  544. int clk_gate_is_enabled(struct clk_hw *hw);
  545. struct clk_div_table {
  546. unsigned int val;
  547. unsigned int div;
  548. };
  549. /**
  550. * struct clk_divider - adjustable divider clock
  551. *
  552. * @hw: handle between common and hardware-specific interfaces
  553. * @reg: register containing the divider
  554. * @shift: shift to the divider bit field
  555. * @width: width of the divider bit field
  556. * @table: array of value/divider pairs, last entry should have div = 0
  557. * @lock: register lock
  558. *
  559. * Clock with an adjustable divider affecting its output frequency. Implements
  560. * .recalc_rate, .set_rate and .round_rate
  561. *
  562. * Flags:
  563. * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
  564. * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
  565. * the raw value read from the register, with the value of zero considered
  566. * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
  567. * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
  568. * the hardware register
  569. * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
  570. * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
  571. * Some hardware implementations gracefully handle this case and allow a
  572. * zero divisor by not modifying their input clock
  573. * (divide by one / bypass).
  574. * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
  575. * of this register, and mask of divider bits are in higher 16-bit of this
  576. * register. While setting the divider bits, higher 16-bit should also be
  577. * updated to indicate changing divider bits.
  578. * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
  579. * to the closest integer instead of the up one.
  580. * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
  581. * not be changed by the clock framework.
  582. * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
  583. * except when the value read from the register is zero, the divisor is
  584. * 2^width of the field.
  585. * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
  586. * for the divider register. Setting this flag makes the register accesses
  587. * big endian.
  588. */
  589. struct clk_divider {
  590. struct clk_hw hw;
  591. void __iomem *reg;
  592. u8 shift;
  593. u8 width;
  594. u8 flags;
  595. const struct clk_div_table *table;
  596. spinlock_t *lock;
  597. };
  598. #define clk_div_mask(width) ((1 << (width)) - 1)
  599. #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
  600. #define CLK_DIVIDER_ONE_BASED BIT(0)
  601. #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
  602. #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
  603. #define CLK_DIVIDER_HIWORD_MASK BIT(3)
  604. #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
  605. #define CLK_DIVIDER_READ_ONLY BIT(5)
  606. #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
  607. #define CLK_DIVIDER_BIG_ENDIAN BIT(7)
  608. extern const struct clk_ops clk_divider_ops;
  609. extern const struct clk_ops clk_divider_ro_ops;
  610. unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
  611. unsigned int val, const struct clk_div_table *table,
  612. unsigned long flags, unsigned long width);
  613. long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
  614. unsigned long rate, unsigned long *prate,
  615. const struct clk_div_table *table,
  616. u8 width, unsigned long flags);
  617. long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
  618. unsigned long rate, unsigned long *prate,
  619. const struct clk_div_table *table, u8 width,
  620. unsigned long flags, unsigned int val);
  621. int divider_get_val(unsigned long rate, unsigned long parent_rate,
  622. const struct clk_div_table *table, u8 width,
  623. unsigned long flags);
  624. struct clk_hw *__clk_hw_register_divider(struct device *dev,
  625. struct device_node *np, const char *name,
  626. const char *parent_name, const struct clk_hw *parent_hw,
  627. const struct clk_parent_data *parent_data, unsigned long flags,
  628. void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
  629. const struct clk_div_table *table, spinlock_t *lock);
  630. struct clk *clk_register_divider_table(struct device *dev, const char *name,
  631. const char *parent_name, unsigned long flags,
  632. void __iomem *reg, u8 shift, u8 width,
  633. u8 clk_divider_flags, const struct clk_div_table *table,
  634. spinlock_t *lock);
  635. /**
  636. * clk_register_divider - register a divider clock with the clock framework
  637. * @dev: device registering this clock
  638. * @name: name of this clock
  639. * @parent_name: name of clock's parent
  640. * @flags: framework-specific flags
  641. * @reg: register address to adjust divider
  642. * @shift: number of bits to shift the bitfield
  643. * @width: width of the bitfield
  644. * @clk_divider_flags: divider-specific flags for this clock
  645. * @lock: shared register lock for this clock
  646. */
  647. #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \
  648. clk_divider_flags, lock) \
  649. clk_register_divider_table((dev), (name), (parent_name), (flags), \
  650. (reg), (shift), (width), \
  651. (clk_divider_flags), NULL, (lock))
  652. /**
  653. * clk_hw_register_divider - register a divider clock with the clock framework
  654. * @dev: device registering this clock
  655. * @name: name of this clock
  656. * @parent_name: name of clock's parent
  657. * @flags: framework-specific flags
  658. * @reg: register address to adjust divider
  659. * @shift: number of bits to shift the bitfield
  660. * @width: width of the bitfield
  661. * @clk_divider_flags: divider-specific flags for this clock
  662. * @lock: shared register lock for this clock
  663. */
  664. #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
  665. width, clk_divider_flags, lock) \
  666. __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
  667. NULL, (flags), (reg), (shift), (width), \
  668. (clk_divider_flags), NULL, (lock))
  669. /**
  670. * clk_hw_register_divider_parent_hw - register a divider clock with the clock
  671. * framework
  672. * @dev: device registering this clock
  673. * @name: name of this clock
  674. * @parent_hw: pointer to parent clk
  675. * @flags: framework-specific flags
  676. * @reg: register address to adjust divider
  677. * @shift: number of bits to shift the bitfield
  678. * @width: width of the bitfield
  679. * @clk_divider_flags: divider-specific flags for this clock
  680. * @lock: shared register lock for this clock
  681. */
  682. #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \
  683. shift, width, clk_divider_flags, \
  684. lock) \
  685. __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
  686. NULL, (flags), (reg), (shift), (width), \
  687. (clk_divider_flags), NULL, (lock))
  688. /**
  689. * clk_hw_register_divider_parent_data - register a divider clock with the clock
  690. * framework
  691. * @dev: device registering this clock
  692. * @name: name of this clock
  693. * @parent_data: parent clk data
  694. * @flags: framework-specific flags
  695. * @reg: register address to adjust divider
  696. * @shift: number of bits to shift the bitfield
  697. * @width: width of the bitfield
  698. * @clk_divider_flags: divider-specific flags for this clock
  699. * @lock: shared register lock for this clock
  700. */
  701. #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \
  702. reg, shift, width, \
  703. clk_divider_flags, lock) \
  704. __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
  705. (parent_data), (flags), (reg), (shift), \
  706. (width), (clk_divider_flags), NULL, (lock))
  707. /**
  708. * clk_hw_register_divider_table - register a table based divider clock with
  709. * the clock framework
  710. * @dev: device registering this clock
  711. * @name: name of this clock
  712. * @parent_name: name of clock's parent
  713. * @flags: framework-specific flags
  714. * @reg: register address to adjust divider
  715. * @shift: number of bits to shift the bitfield
  716. * @width: width of the bitfield
  717. * @clk_divider_flags: divider-specific flags for this clock
  718. * @table: array of divider/value pairs ending with a div set to 0
  719. * @lock: shared register lock for this clock
  720. */
  721. #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \
  722. shift, width, clk_divider_flags, table, \
  723. lock) \
  724. __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
  725. NULL, (flags), (reg), (shift), (width), \
  726. (clk_divider_flags), (table), (lock))
  727. /**
  728. * clk_hw_register_divider_table_parent_hw - register a table based divider
  729. * clock with the clock framework
  730. * @dev: device registering this clock
  731. * @name: name of this clock
  732. * @parent_hw: pointer to parent clk
  733. * @flags: framework-specific flags
  734. * @reg: register address to adjust divider
  735. * @shift: number of bits to shift the bitfield
  736. * @width: width of the bitfield
  737. * @clk_divider_flags: divider-specific flags for this clock
  738. * @table: array of divider/value pairs ending with a div set to 0
  739. * @lock: shared register lock for this clock
  740. */
  741. #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \
  742. reg, shift, width, \
  743. clk_divider_flags, table, \
  744. lock) \
  745. __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
  746. NULL, (flags), (reg), (shift), (width), \
  747. (clk_divider_flags), (table), (lock))
  748. /**
  749. * clk_hw_register_divider_table_parent_data - register a table based divider
  750. * clock with the clock framework
  751. * @dev: device registering this clock
  752. * @name: name of this clock
  753. * @parent_data: parent clk data
  754. * @flags: framework-specific flags
  755. * @reg: register address to adjust divider
  756. * @shift: number of bits to shift the bitfield
  757. * @width: width of the bitfield
  758. * @clk_divider_flags: divider-specific flags for this clock
  759. * @table: array of divider/value pairs ending with a div set to 0
  760. * @lock: shared register lock for this clock
  761. */
  762. #define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \
  763. flags, reg, shift, width, \
  764. clk_divider_flags, table, \
  765. lock) \
  766. __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
  767. (parent_data), (flags), (reg), (shift), \
  768. (width), (clk_divider_flags), (table), \
  769. (lock))
  770. void clk_unregister_divider(struct clk *clk);
  771. void clk_hw_unregister_divider(struct clk_hw *hw);
  772. /**
  773. * struct clk_mux - multiplexer clock
  774. *
  775. * @hw: handle between common and hardware-specific interfaces
  776. * @reg: register controlling multiplexer
  777. * @table: array of register values corresponding to the parent index
  778. * @shift: shift to multiplexer bit field
  779. * @mask: mask of mutliplexer bit field
  780. * @flags: hardware-specific flags
  781. * @lock: register lock
  782. *
  783. * Clock with multiple selectable parents. Implements .get_parent, .set_parent
  784. * and .recalc_rate
  785. *
  786. * Flags:
  787. * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
  788. * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
  789. * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
  790. * register, and mask of mux bits are in higher 16-bit of this register.
  791. * While setting the mux bits, higher 16-bit should also be updated to
  792. * indicate changing mux bits.
  793. * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
  794. * .get_parent clk_op.
  795. * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
  796. * frequency.
  797. * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
  798. * the mux register. Setting this flag makes the register accesses big
  799. * endian.
  800. */
  801. struct clk_mux {
  802. struct clk_hw hw;
  803. void __iomem *reg;
  804. u32 *table;
  805. u32 mask;
  806. u8 shift;
  807. u8 flags;
  808. spinlock_t *lock;
  809. };
  810. #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
  811. #define CLK_MUX_INDEX_ONE BIT(0)
  812. #define CLK_MUX_INDEX_BIT BIT(1)
  813. #define CLK_MUX_HIWORD_MASK BIT(2)
  814. #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
  815. #define CLK_MUX_ROUND_CLOSEST BIT(4)
  816. #define CLK_MUX_BIG_ENDIAN BIT(5)
  817. extern const struct clk_ops clk_mux_ops;
  818. extern const struct clk_ops clk_mux_ro_ops;
  819. struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
  820. const char *name, u8 num_parents,
  821. const char * const *parent_names,
  822. const struct clk_hw **parent_hws,
  823. const struct clk_parent_data *parent_data,
  824. unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
  825. u8 clk_mux_flags, u32 *table, spinlock_t *lock);
  826. struct clk *clk_register_mux_table(struct device *dev, const char *name,
  827. const char * const *parent_names, u8 num_parents,
  828. unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
  829. u8 clk_mux_flags, u32 *table, spinlock_t *lock);
  830. #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \
  831. shift, width, clk_mux_flags, lock) \
  832. clk_register_mux_table((dev), (name), (parent_names), (num_parents), \
  833. (flags), (reg), (shift), BIT((width)) - 1, \
  834. (clk_mux_flags), NULL, (lock))
  835. #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \
  836. flags, reg, shift, mask, clk_mux_flags, \
  837. table, lock) \
  838. __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
  839. (parent_names), NULL, NULL, (flags), (reg), \
  840. (shift), (mask), (clk_mux_flags), (table), \
  841. (lock))
  842. #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
  843. shift, width, clk_mux_flags, lock) \
  844. __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
  845. (parent_names), NULL, NULL, (flags), (reg), \
  846. (shift), BIT((width)) - 1, (clk_mux_flags), \
  847. NULL, (lock))
  848. #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \
  849. reg, shift, width, clk_mux_flags, lock) \
  850. __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
  851. (parent_hws), NULL, (flags), (reg), (shift), \
  852. BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
  853. #define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \
  854. flags, reg, shift, width, \
  855. clk_mux_flags, lock) \
  856. __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
  857. (parent_data), (flags), (reg), (shift), \
  858. BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
  859. int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
  860. unsigned int val);
  861. unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
  862. void clk_unregister_mux(struct clk *clk);
  863. void clk_hw_unregister_mux(struct clk_hw *hw);
  864. void of_fixed_factor_clk_setup(struct device_node *node);
  865. /**
  866. * struct clk_fixed_factor - fixed multiplier and divider clock
  867. *
  868. * @hw: handle between common and hardware-specific interfaces
  869. * @mult: multiplier
  870. * @div: divider
  871. *
  872. * Clock with a fixed multiplier and divider. The output frequency is the
  873. * parent clock rate divided by div and multiplied by mult.
  874. * Implements .recalc_rate, .set_rate and .round_rate
  875. */
  876. struct clk_fixed_factor {
  877. struct clk_hw hw;
  878. unsigned int mult;
  879. unsigned int div;
  880. };
  881. #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
  882. extern const struct clk_ops clk_fixed_factor_ops;
  883. struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
  884. const char *parent_name, unsigned long flags,
  885. unsigned int mult, unsigned int div);
  886. void clk_unregister_fixed_factor(struct clk *clk);
  887. struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
  888. const char *name, const char *parent_name, unsigned long flags,
  889. unsigned int mult, unsigned int div);
  890. void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
  891. /**
  892. * struct clk_fractional_divider - adjustable fractional divider clock
  893. *
  894. * @hw: handle between common and hardware-specific interfaces
  895. * @reg: register containing the divider
  896. * @mshift: shift to the numerator bit field
  897. * @mwidth: width of the numerator bit field
  898. * @nshift: shift to the denominator bit field
  899. * @nwidth: width of the denominator bit field
  900. * @lock: register lock
  901. *
  902. * Clock with adjustable fractional divider affecting its output frequency.
  903. *
  904. * Flags:
  905. * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
  906. * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
  907. * is set then the numerator and denominator are both the value read
  908. * plus one.
  909. * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
  910. * used for the divider register. Setting this flag makes the register
  911. * accesses big endian.
  912. */
  913. struct clk_fractional_divider {
  914. struct clk_hw hw;
  915. void __iomem *reg;
  916. u8 mshift;
  917. u8 mwidth;
  918. u32 mmask;
  919. u8 nshift;
  920. u8 nwidth;
  921. u32 nmask;
  922. u8 flags;
  923. void (*approximation)(struct clk_hw *hw,
  924. unsigned long rate, unsigned long *parent_rate,
  925. unsigned long *m, unsigned long *n);
  926. spinlock_t *lock;
  927. };
  928. #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
  929. #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
  930. #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
  931. extern const struct clk_ops clk_fractional_divider_ops;
  932. struct clk *clk_register_fractional_divider(struct device *dev,
  933. const char *name, const char *parent_name, unsigned long flags,
  934. void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
  935. u8 clk_divider_flags, spinlock_t *lock);
  936. struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
  937. const char *name, const char *parent_name, unsigned long flags,
  938. void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
  939. u8 clk_divider_flags, spinlock_t *lock);
  940. void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
  941. /**
  942. * struct clk_multiplier - adjustable multiplier clock
  943. *
  944. * @hw: handle between common and hardware-specific interfaces
  945. * @reg: register containing the multiplier
  946. * @shift: shift to the multiplier bit field
  947. * @width: width of the multiplier bit field
  948. * @lock: register lock
  949. *
  950. * Clock with an adjustable multiplier affecting its output frequency.
  951. * Implements .recalc_rate, .set_rate and .round_rate
  952. *
  953. * Flags:
  954. * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
  955. * from the register, with 0 being a valid value effectively
  956. * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
  957. * set, then a null multiplier will be considered as a bypass,
  958. * leaving the parent rate unmodified.
  959. * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
  960. * rounded to the closest integer instead of the down one.
  961. * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
  962. * used for the multiplier register. Setting this flag makes the register
  963. * accesses big endian.
  964. */
  965. struct clk_multiplier {
  966. struct clk_hw hw;
  967. void __iomem *reg;
  968. u8 shift;
  969. u8 width;
  970. u8 flags;
  971. spinlock_t *lock;
  972. };
  973. #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
  974. #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
  975. #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
  976. #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
  977. extern const struct clk_ops clk_multiplier_ops;
  978. /***
  979. * struct clk_composite - aggregate clock of mux, divider and gate clocks
  980. *
  981. * @hw: handle between common and hardware-specific interfaces
  982. * @mux_hw: handle between composite and hardware-specific mux clock
  983. * @rate_hw: handle between composite and hardware-specific rate clock
  984. * @gate_hw: handle between composite and hardware-specific gate clock
  985. * @mux_ops: clock ops for mux
  986. * @rate_ops: clock ops for rate
  987. * @gate_ops: clock ops for gate
  988. */
  989. struct clk_composite {
  990. struct clk_hw hw;
  991. struct clk_ops ops;
  992. struct clk_hw *mux_hw;
  993. struct clk_hw *rate_hw;
  994. struct clk_hw *gate_hw;
  995. const struct clk_ops *mux_ops;
  996. const struct clk_ops *rate_ops;
  997. const struct clk_ops *gate_ops;
  998. };
  999. #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
  1000. struct clk *clk_register_composite(struct device *dev, const char *name,
  1001. const char * const *parent_names, int num_parents,
  1002. struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
  1003. struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
  1004. struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
  1005. unsigned long flags);
  1006. struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
  1007. const struct clk_parent_data *parent_data, int num_parents,
  1008. struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
  1009. struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
  1010. struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
  1011. unsigned long flags);
  1012. void clk_unregister_composite(struct clk *clk);
  1013. struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
  1014. const char * const *parent_names, int num_parents,
  1015. struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
  1016. struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
  1017. struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
  1018. unsigned long flags);
  1019. struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
  1020. const char *name,
  1021. const struct clk_parent_data *parent_data, int num_parents,
  1022. struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
  1023. struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
  1024. struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
  1025. unsigned long flags);
  1026. void clk_hw_unregister_composite(struct clk_hw *hw);
  1027. struct clk *clk_register(struct device *dev, struct clk_hw *hw);
  1028. struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
  1029. int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
  1030. int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
  1031. int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
  1032. void clk_unregister(struct clk *clk);
  1033. void devm_clk_unregister(struct device *dev, struct clk *clk);
  1034. void clk_hw_unregister(struct clk_hw *hw);
  1035. void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);
  1036. void clk_sync_state(struct device *dev);
  1037. /* helper functions */
  1038. const char *__clk_get_name(const struct clk *clk);
  1039. const char *clk_hw_get_name(const struct clk_hw *hw);
  1040. #ifdef CONFIG_COMMON_CLK
  1041. struct clk_hw *__clk_get_hw(struct clk *clk);
  1042. #else
  1043. static inline struct clk_hw *__clk_get_hw(struct clk *clk)
  1044. {
  1045. return (struct clk_hw *)clk;
  1046. }
  1047. #endif
  1048. struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id);
  1049. struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,
  1050. const char *con_id);
  1051. unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
  1052. struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
  1053. struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
  1054. unsigned int index);
  1055. int clk_hw_get_parent_index(struct clk_hw *hw);
  1056. int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
  1057. unsigned int __clk_get_enable_count(struct clk *clk);
  1058. unsigned long clk_hw_get_rate(const struct clk_hw *hw);
  1059. unsigned long clk_hw_get_flags(const struct clk_hw *hw);
  1060. #define clk_hw_can_set_rate_parent(hw) \
  1061. (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
  1062. bool clk_hw_is_prepared(const struct clk_hw *hw);
  1063. bool clk_hw_rate_is_protected(const struct clk_hw *hw);
  1064. bool clk_hw_is_enabled(const struct clk_hw *hw);
  1065. bool __clk_is_enabled(struct clk *clk);
  1066. struct clk *__clk_lookup(const char *name);
  1067. int __clk_mux_determine_rate(struct clk_hw *hw,
  1068. struct clk_rate_request *req);
  1069. int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
  1070. int __clk_mux_determine_rate_closest(struct clk_hw *hw,
  1071. struct clk_rate_request *req);
  1072. int clk_mux_determine_rate_flags(struct clk_hw *hw,
  1073. struct clk_rate_request *req,
  1074. unsigned long flags);
  1075. void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
  1076. void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
  1077. unsigned long max_rate);
  1078. static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
  1079. {
  1080. dst->clk = src->clk;
  1081. dst->core = src->core;
  1082. }
  1083. static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
  1084. unsigned long *prate,
  1085. const struct clk_div_table *table,
  1086. u8 width, unsigned long flags)
  1087. {
  1088. return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
  1089. rate, prate, table, width, flags);
  1090. }
  1091. static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
  1092. unsigned long *prate,
  1093. const struct clk_div_table *table,
  1094. u8 width, unsigned long flags,
  1095. unsigned int val)
  1096. {
  1097. return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
  1098. rate, prate, table, width, flags,
  1099. val);
  1100. }
  1101. /*
  1102. * FIXME clock api without lock protection
  1103. */
  1104. unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
  1105. struct clk_onecell_data {
  1106. struct clk **clks;
  1107. unsigned int clk_num;
  1108. };
  1109. struct clk_hw_onecell_data {
  1110. unsigned int num;
  1111. struct clk_hw *hws[];
  1112. };
  1113. #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
  1114. /*
  1115. * Use this macro when you have a driver that requires two initialization
  1116. * routines, one at of_clk_init(), and one at platform device probe
  1117. */
  1118. #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
  1119. static void __init name##_of_clk_init_driver(struct device_node *np) \
  1120. { \
  1121. of_node_clear_flag(np, OF_POPULATED); \
  1122. fn(np); \
  1123. } \
  1124. OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
  1125. #define CLK_HW_INIT(_name, _parent, _ops, _flags) \
  1126. (&(struct clk_init_data) { \
  1127. .flags = _flags, \
  1128. .name = _name, \
  1129. .parent_names = (const char *[]) { _parent }, \
  1130. .num_parents = 1, \
  1131. .ops = _ops, \
  1132. })
  1133. #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \
  1134. (&(struct clk_init_data) { \
  1135. .flags = _flags, \
  1136. .name = _name, \
  1137. .parent_hws = (const struct clk_hw*[]) { _parent }, \
  1138. .num_parents = 1, \
  1139. .ops = _ops, \
  1140. })
  1141. /*
  1142. * This macro is intended for drivers to be able to share the otherwise
  1143. * individual struct clk_hw[] compound literals created by the compiler
  1144. * when using CLK_HW_INIT_HW. It does NOT support multiple parents.
  1145. */
  1146. #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \
  1147. (&(struct clk_init_data) { \
  1148. .flags = _flags, \
  1149. .name = _name, \
  1150. .parent_hws = _parent, \
  1151. .num_parents = 1, \
  1152. .ops = _ops, \
  1153. })
  1154. #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \
  1155. (&(struct clk_init_data) { \
  1156. .flags = _flags, \
  1157. .name = _name, \
  1158. .parent_data = (const struct clk_parent_data[]) { \
  1159. { .fw_name = _parent }, \
  1160. }, \
  1161. .num_parents = 1, \
  1162. .ops = _ops, \
  1163. })
  1164. #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
  1165. (&(struct clk_init_data) { \
  1166. .flags = _flags, \
  1167. .name = _name, \
  1168. .parent_names = _parents, \
  1169. .num_parents = ARRAY_SIZE(_parents), \
  1170. .ops = _ops, \
  1171. })
  1172. #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \
  1173. (&(struct clk_init_data) { \
  1174. .flags = _flags, \
  1175. .name = _name, \
  1176. .parent_hws = _parents, \
  1177. .num_parents = ARRAY_SIZE(_parents), \
  1178. .ops = _ops, \
  1179. })
  1180. #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \
  1181. (&(struct clk_init_data) { \
  1182. .flags = _flags, \
  1183. .name = _name, \
  1184. .parent_data = _parents, \
  1185. .num_parents = ARRAY_SIZE(_parents), \
  1186. .ops = _ops, \
  1187. })
  1188. #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
  1189. (&(struct clk_init_data) { \
  1190. .flags = _flags, \
  1191. .name = _name, \
  1192. .parent_names = NULL, \
  1193. .num_parents = 0, \
  1194. .ops = _ops, \
  1195. })
  1196. #define CLK_FIXED_FACTOR(_struct, _name, _parent, \
  1197. _div, _mult, _flags) \
  1198. struct clk_fixed_factor _struct = { \
  1199. .div = _div, \
  1200. .mult = _mult, \
  1201. .hw.init = CLK_HW_INIT(_name, \
  1202. _parent, \
  1203. &clk_fixed_factor_ops, \
  1204. _flags), \
  1205. }
  1206. #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \
  1207. _div, _mult, _flags) \
  1208. struct clk_fixed_factor _struct = { \
  1209. .div = _div, \
  1210. .mult = _mult, \
  1211. .hw.init = CLK_HW_INIT_HW(_name, \
  1212. _parent, \
  1213. &clk_fixed_factor_ops, \
  1214. _flags), \
  1215. }
  1216. /*
  1217. * This macro allows the driver to reuse the _parent array for multiple
  1218. * fixed factor clk declarations.
  1219. */
  1220. #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \
  1221. _div, _mult, _flags) \
  1222. struct clk_fixed_factor _struct = { \
  1223. .div = _div, \
  1224. .mult = _mult, \
  1225. .hw.init = CLK_HW_INIT_HWS(_name, \
  1226. _parent, \
  1227. &clk_fixed_factor_ops, \
  1228. _flags), \
  1229. }
  1230. #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \
  1231. _div, _mult, _flags) \
  1232. struct clk_fixed_factor _struct = { \
  1233. .div = _div, \
  1234. .mult = _mult, \
  1235. .hw.init = CLK_HW_INIT_FW_NAME(_name, \
  1236. _parent, \
  1237. &clk_fixed_factor_ops, \
  1238. _flags), \
  1239. }
  1240. #ifdef CONFIG_OF
  1241. int of_clk_add_provider(struct device_node *np,
  1242. struct clk *(*clk_src_get)(struct of_phandle_args *args,
  1243. void *data),
  1244. void *data);
  1245. int of_clk_add_hw_provider(struct device_node *np,
  1246. struct clk_hw *(*get)(struct of_phandle_args *clkspec,
  1247. void *data),
  1248. void *data);
  1249. int devm_of_clk_add_hw_provider(struct device *dev,
  1250. struct clk_hw *(*get)(struct of_phandle_args *clkspec,
  1251. void *data),
  1252. void *data);
  1253. void of_clk_del_provider(struct device_node *np);
  1254. void devm_of_clk_del_provider(struct device *dev);
  1255. struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
  1256. void *data);
  1257. struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
  1258. void *data);
  1259. struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
  1260. struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
  1261. void *data);
  1262. int of_clk_parent_fill(struct device_node *np, const char **parents,
  1263. unsigned int size);
  1264. int of_clk_detect_critical(struct device_node *np, int index,
  1265. unsigned long *flags);
  1266. #else /* !CONFIG_OF */
  1267. static inline int of_clk_add_provider(struct device_node *np,
  1268. struct clk *(*clk_src_get)(struct of_phandle_args *args,
  1269. void *data),
  1270. void *data)
  1271. {
  1272. return 0;
  1273. }
  1274. static inline int of_clk_add_hw_provider(struct device_node *np,
  1275. struct clk_hw *(*get)(struct of_phandle_args *clkspec,
  1276. void *data),
  1277. void *data)
  1278. {
  1279. return 0;
  1280. }
  1281. static inline int devm_of_clk_add_hw_provider(struct device *dev,
  1282. struct clk_hw *(*get)(struct of_phandle_args *clkspec,
  1283. void *data),
  1284. void *data)
  1285. {
  1286. return 0;
  1287. }
  1288. static inline void of_clk_del_provider(struct device_node *np) {}
  1289. static inline void devm_of_clk_del_provider(struct device *dev) {}
  1290. static inline struct clk *of_clk_src_simple_get(
  1291. struct of_phandle_args *clkspec, void *data)
  1292. {
  1293. return ERR_PTR(-ENOENT);
  1294. }
  1295. static inline struct clk_hw *
  1296. of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
  1297. {
  1298. return ERR_PTR(-ENOENT);
  1299. }
  1300. static inline struct clk *of_clk_src_onecell_get(
  1301. struct of_phandle_args *clkspec, void *data)
  1302. {
  1303. return ERR_PTR(-ENOENT);
  1304. }
  1305. static inline struct clk_hw *
  1306. of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
  1307. {
  1308. return ERR_PTR(-ENOENT);
  1309. }
  1310. static inline int of_clk_parent_fill(struct device_node *np,
  1311. const char **parents, unsigned int size)
  1312. {
  1313. return 0;
  1314. }
  1315. static inline int of_clk_detect_critical(struct device_node *np, int index,
  1316. unsigned long *flags)
  1317. {
  1318. return 0;
  1319. }
  1320. #endif /* CONFIG_OF */
  1321. void clk_gate_restore_context(struct clk_hw *hw);
  1322. #endif /* CLK_PROVIDER_H */