brcmphy.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef _LINUX_BRCMPHY_H
  3. #define _LINUX_BRCMPHY_H
  4. #include <linux/phy.h>
  5. /* All Broadcom Ethernet switches have a pseudo-PHY at address 30 which is used
  6. * to configure the switch internal registers via MDIO accesses.
  7. */
  8. #define BRCM_PSEUDO_PHY_ADDR 30
  9. #define PHY_ID_BCM50610 0x0143bd60
  10. #define PHY_ID_BCM50610M 0x0143bd70
  11. #define PHY_ID_BCM5241 0x0143bc30
  12. #define PHY_ID_BCMAC131 0x0143bc70
  13. #define PHY_ID_BCM5481 0x0143bca0
  14. #define PHY_ID_BCM5395 0x0143bcf0
  15. #define PHY_ID_BCM53125 0x03625f20
  16. #define PHY_ID_BCM54810 0x03625d00
  17. #define PHY_ID_BCM54811 0x03625cc0
  18. #define PHY_ID_BCM5482 0x0143bcb0
  19. #define PHY_ID_BCM5411 0x00206070
  20. #define PHY_ID_BCM5421 0x002060e0
  21. #define PHY_ID_BCM54210E 0x600d84a0
  22. #define PHY_ID_BCM5464 0x002060b0
  23. #define PHY_ID_BCM5461 0x002060c0
  24. #define PHY_ID_BCM54612E 0x03625e60
  25. #define PHY_ID_BCM54616S 0x03625d10
  26. #define PHY_ID_BCM54140 0xae025009
  27. #define PHY_ID_BCM57780 0x03625d90
  28. #define PHY_ID_BCM89610 0x03625cd0
  29. #define PHY_ID_BCM72113 0x35905310
  30. #define PHY_ID_BCM7250 0xae025280
  31. #define PHY_ID_BCM7255 0xae025120
  32. #define PHY_ID_BCM7260 0xae025190
  33. #define PHY_ID_BCM7268 0xae025090
  34. #define PHY_ID_BCM7271 0xae0253b0
  35. #define PHY_ID_BCM7278 0xae0251a0
  36. #define PHY_ID_BCM7364 0xae025260
  37. #define PHY_ID_BCM7366 0x600d8490
  38. #define PHY_ID_BCM7346 0x600d8650
  39. #define PHY_ID_BCM7362 0x600d84b0
  40. #define PHY_ID_BCM7425 0x600d86b0
  41. #define PHY_ID_BCM7429 0x600d8730
  42. #define PHY_ID_BCM7435 0x600d8750
  43. #define PHY_ID_BCM74371 0xae0252e0
  44. #define PHY_ID_BCM7439 0x600d8480
  45. #define PHY_ID_BCM7439_2 0xae025080
  46. #define PHY_ID_BCM7445 0x600d8510
  47. #define PHY_ID_BCM_CYGNUS 0xae025200
  48. #define PHY_ID_BCM_OMEGA 0xae025100
  49. #define PHY_BCM_OUI_MASK 0xfffffc00
  50. #define PHY_BCM_OUI_1 0x00206000
  51. #define PHY_BCM_OUI_2 0x0143bc00
  52. #define PHY_BCM_OUI_3 0x03625c00
  53. #define PHY_BCM_OUI_4 0x600d8400
  54. #define PHY_BCM_OUI_5 0x03625e00
  55. #define PHY_BCM_OUI_6 0xae025000
  56. #define PHY_BCM_FLAGS_MODE_COPPER 0x00000001
  57. #define PHY_BCM_FLAGS_MODE_1000BX 0x00000002
  58. #define PHY_BCM_FLAGS_INTF_SGMII 0x00000010
  59. #define PHY_BCM_FLAGS_INTF_XAUI 0x00000020
  60. #define PHY_BRCM_WIRESPEED_ENABLE 0x00000100
  61. #define PHY_BRCM_AUTO_PWRDWN_ENABLE 0x00000200
  62. #define PHY_BRCM_RX_REFCLK_UNUSED 0x00000400
  63. #define PHY_BRCM_STD_IBND_DISABLE 0x00000800
  64. #define PHY_BRCM_EXT_IBND_RX_ENABLE 0x00001000
  65. #define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000
  66. #define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000
  67. #define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000
  68. #define PHY_BRCM_EN_MASTER_MODE 0x00010000
  69. /* Broadcom BCM7xxx specific workarounds */
  70. #define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff)
  71. #define PHY_BRCM_7XXX_PATCH(x) ((x) & 0xff)
  72. #define PHY_BCM_FLAGS_VALID 0x80000000
  73. /* Broadcom BCM54XX register definitions, common to most Broadcom PHYs */
  74. #define MII_BCM54XX_ECR 0x10 /* BCM54xx extended control register */
  75. #define MII_BCM54XX_ECR_IM 0x1000 /* Interrupt mask */
  76. #define MII_BCM54XX_ECR_IF 0x0800 /* Interrupt force */
  77. #define MII_BCM54XX_ECR_FIFOE 0x0001 /* FIFO elasticity */
  78. #define MII_BCM54XX_ESR 0x11 /* BCM54xx extended status register */
  79. #define MII_BCM54XX_ESR_IS 0x1000 /* Interrupt status */
  80. #define MII_BCM54XX_EXP_DATA 0x15 /* Expansion register data */
  81. #define MII_BCM54XX_EXP_SEL 0x17 /* Expansion register select */
  82. #define MII_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */
  83. #define MII_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */
  84. #define MII_BCM54XX_EXP_SEL_ETC 0x0d00 /* Expansion register spare + 2k mem */
  85. #define MII_BCM54XX_AUX_CTL 0x18 /* Auxiliary control register */
  86. #define MII_BCM54XX_ISR 0x1a /* BCM54xx interrupt status register */
  87. #define MII_BCM54XX_IMR 0x1b /* BCM54xx interrupt mask register */
  88. #define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC error */
  89. #define MII_BCM54XX_INT_LINK 0x0002 /* Link status changed */
  90. #define MII_BCM54XX_INT_SPEED 0x0004 /* Link speed change */
  91. #define MII_BCM54XX_INT_DUPLEX 0x0008 /* Duplex mode changed */
  92. #define MII_BCM54XX_INT_LRS 0x0010 /* Local receiver status changed */
  93. #define MII_BCM54XX_INT_RRS 0x0020 /* Remote receiver status changed */
  94. #define MII_BCM54XX_INT_SSERR 0x0040 /* Scrambler synchronization error */
  95. #define MII_BCM54XX_INT_UHCD 0x0080 /* Unsupported HCD negotiated */
  96. #define MII_BCM54XX_INT_NHCD 0x0100 /* No HCD */
  97. #define MII_BCM54XX_INT_NHCDL 0x0200 /* No HCD link */
  98. #define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */
  99. #define MII_BCM54XX_INT_LC 0x0800 /* All counters below 128 */
  100. #define MII_BCM54XX_INT_HC 0x1000 /* Counter above 32768 */
  101. #define MII_BCM54XX_INT_MDIX 0x2000 /* MDIX status change */
  102. #define MII_BCM54XX_INT_PSERR 0x4000 /* Pair swap error */
  103. #define MII_BCM54XX_SHD 0x1c /* 0x1c shadow registers */
  104. #define MII_BCM54XX_SHD_WRITE 0x8000
  105. #define MII_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10)
  106. #define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
  107. #define MII_BCM54XX_RDB_ADDR 0x1e
  108. #define MII_BCM54XX_RDB_DATA 0x1f
  109. /* legacy access control via rdb/expansion register */
  110. #define BCM54XX_RDB_REG0087 0x0087
  111. #define BCM54XX_EXP_REG7E (MII_BCM54XX_EXP_SEL_ER + 0x7E)
  112. #define BCM54XX_ACCESS_MODE_LEGACY_EN BIT(15)
  113. /*
  114. * AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18)
  115. */
  116. #define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x00
  117. #define MII_BCM54XX_AUXCTL_ACTL_TX_6DB 0x0400
  118. #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800
  119. #define MII_BCM54XX_AUXCTL_ACTL_EXT_PKT_LEN 0x4000
  120. #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x07
  121. #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN 0x0010
  122. #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN 0x0080
  123. #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN 0x0100
  124. #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
  125. #define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
  126. #define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
  127. #define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007
  128. /*
  129. * Broadcom LED source encodings. These are used in BCM5461, BCM5481,
  130. * BCM5482, and possibly some others.
  131. */
  132. #define BCM_LED_SRC_LINKSPD1 0x0
  133. #define BCM_LED_SRC_LINKSPD2 0x1
  134. #define BCM_LED_SRC_XMITLED 0x2
  135. #define BCM_LED_SRC_ACTIVITYLED 0x3
  136. #define BCM_LED_SRC_FDXLED 0x4
  137. #define BCM_LED_SRC_SLAVE 0x5
  138. #define BCM_LED_SRC_INTR 0x6
  139. #define BCM_LED_SRC_QUALITY 0x7
  140. #define BCM_LED_SRC_RCVLED 0x8
  141. #define BCM_LED_SRC_WIRESPEED 0x9
  142. #define BCM_LED_SRC_MULTICOLOR1 0xa
  143. #define BCM_LED_SRC_OPENSHORT 0xb
  144. #define BCM_LED_SRC_OFF 0xe /* Tied high */
  145. #define BCM_LED_SRC_ON 0xf /* Tied low */
  146. /*
  147. * Broadcom Multicolor LED configurations (expansion register 4)
  148. */
  149. #define BCM_EXP_MULTICOLOR (MII_BCM54XX_EXP_SEL_ER + 0x04)
  150. #define BCM_LED_MULTICOLOR_IN_PHASE BIT(8)
  151. #define BCM_LED_MULTICOLOR_LINK_ACT 0x0
  152. #define BCM_LED_MULTICOLOR_SPEED 0x1
  153. #define BCM_LED_MULTICOLOR_ACT_FLASH 0x2
  154. #define BCM_LED_MULTICOLOR_FDX 0x3
  155. #define BCM_LED_MULTICOLOR_OFF 0x4
  156. #define BCM_LED_MULTICOLOR_ON 0x5
  157. #define BCM_LED_MULTICOLOR_ALT 0x6
  158. #define BCM_LED_MULTICOLOR_FLASH 0x7
  159. #define BCM_LED_MULTICOLOR_LINK 0x8
  160. #define BCM_LED_MULTICOLOR_ACT 0x9
  161. #define BCM_LED_MULTICOLOR_PROGRAM 0xa
  162. /*
  163. * BCM5482: Shadow registers
  164. * Shadow values go into bits [14:10] of register 0x1c to select a shadow
  165. * register to access.
  166. */
  167. /* 00100: Reserved control register 2 */
  168. #define BCM54XX_SHD_SCR2 0x04
  169. #define BCM54XX_SHD_SCR2_WSPD_RTRY_DIS 0x100
  170. #define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT 2
  171. #define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET 2
  172. #define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK 0x7
  173. /* 00101: Spare Control Register 3 */
  174. #define BCM54XX_SHD_SCR3 0x05
  175. #define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001
  176. #define BCM54XX_SHD_SCR3_DLLAPD_DIS 0x0002
  177. #define BCM54XX_SHD_SCR3_TRDDAPD 0x0004
  178. /* 01010: Auto Power-Down */
  179. #define BCM54XX_SHD_APD 0x0a
  180. #define BCM_APD_CLR_MASK 0xFE9F /* clear bits 5, 6 & 8 */
  181. #define BCM54XX_SHD_APD_EN 0x0020
  182. #define BCM_NO_ANEG_APD_EN 0x0060 /* bits 5 & 6 */
  183. #define BCM_APD_SINGLELP_EN 0x0100 /* Bit 8 */
  184. #define BCM5482_SHD_LEDS1 0x0d /* 01101: LED Selector 1 */
  185. /* LED3 / ~LINKSPD[2] selector */
  186. #define BCM5482_SHD_LEDS1_LED3(src) ((src & 0xf) << 4)
  187. /* LED1 / ~LINKSPD[1] selector */
  188. #define BCM5482_SHD_LEDS1_LED1(src) ((src & 0xf) << 0)
  189. #define BCM54XX_SHD_RGMII_MODE 0x0b /* 01011: RGMII Mode Selector */
  190. #define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */
  191. #define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */
  192. #define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */
  193. /* 10011: SerDes 100-FX Control Register */
  194. #define BCM54616S_SHD_100FX_CTRL 0x13
  195. #define BCM54616S_100FX_MODE BIT(0) /* 100-FX SerDes Enable */
  196. /* 11111: Mode Control Register */
  197. #define BCM54XX_SHD_MODE 0x1f
  198. #define BCM54XX_SHD_INTF_SEL_MASK GENMASK(2, 1) /* INTERF_SEL[1:0] */
  199. #define BCM54XX_SHD_INTF_SEL_RGMII 0x02
  200. #define BCM54XX_SHD_INTF_SEL_SGMII 0x04
  201. #define BCM54XX_SHD_INTF_SEL_GBIC 0x06
  202. #define BCM54XX_SHD_MODE_1000BX BIT(0) /* Enable 1000-X registers */
  203. /*
  204. * EXPANSION SHADOW ACCESS REGISTERS. (PHY REG 0x15, 0x16, and 0x17)
  205. */
  206. #define MII_BCM54XX_EXP_AADJ1CH0 0x001f
  207. #define MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN 0x0200
  208. #define MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF 0x0100
  209. #define MII_BCM54XX_EXP_AADJ1CH3 0x601f
  210. #define MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ 0x0002
  211. #define MII_BCM54XX_EXP_EXP08 0x0F08
  212. #define MII_BCM54XX_EXP_EXP08_RJCT_2MHZ 0x0001
  213. #define MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE 0x0200
  214. #define MII_BCM54XX_EXP_EXP75 0x0f75
  215. #define MII_BCM54XX_EXP_EXP75_VDACCTRL 0x003c
  216. #define MII_BCM54XX_EXP_EXP75_CM_OSC 0x0001
  217. #define MII_BCM54XX_EXP_EXP96 0x0f96
  218. #define MII_BCM54XX_EXP_EXP96_MYST 0x0010
  219. #define MII_BCM54XX_EXP_EXP97 0x0f97
  220. #define MII_BCM54XX_EXP_EXP97_MYST 0x0c0c
  221. /*
  222. * BCM5482: Secondary SerDes registers
  223. */
  224. #define BCM5482_SSD_1000BX_CTL 0x00 /* 1000BASE-X Control */
  225. #define BCM5482_SSD_1000BX_CTL_PWRDOWN 0x0800 /* Power-down SSD */
  226. #define BCM5482_SSD_SGMII_SLAVE 0x15 /* SGMII Slave Register */
  227. #define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */
  228. #define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */
  229. /* BCM54810 Registers */
  230. #define BCM54810_EXP_BROADREACH_LRE_MISC_CTL (MII_BCM54XX_EXP_SEL_ER + 0x90)
  231. #define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN (1 << 0)
  232. #define BCM54810_SHD_CLK_CTL 0x3
  233. #define BCM54810_SHD_CLK_CTL_GTXCLK_EN (1 << 9)
  234. #define BCM54810_SHD_SCR3_TRDDAPD 0x0100
  235. /* BCM54612E Registers */
  236. #define BCM54612E_EXP_SPARE0 (MII_BCM54XX_EXP_SEL_ETC + 0x34)
  237. #define BCM54612E_LED4_CLK125OUT_EN (1 << 1)
  238. /*****************************************************************************/
  239. /* Fast Ethernet Transceiver definitions. */
  240. /*****************************************************************************/
  241. #define MII_BRCM_FET_INTREG 0x1a /* Interrupt register */
  242. #define MII_BRCM_FET_IR_MASK 0x0100 /* Mask all interrupts */
  243. #define MII_BRCM_FET_IR_LINK_EN 0x0200 /* Link status change enable */
  244. #define MII_BRCM_FET_IR_SPEED_EN 0x0400 /* Link speed change enable */
  245. #define MII_BRCM_FET_IR_DUPLEX_EN 0x0800 /* Duplex mode change enable */
  246. #define MII_BRCM_FET_IR_ENABLE 0x4000 /* Interrupt enable */
  247. #define MII_BRCM_FET_BRCMTEST 0x1f /* Brcm test register */
  248. #define MII_BRCM_FET_BT_SRE 0x0080 /* Shadow register enable */
  249. /*** Shadow register definitions ***/
  250. #define MII_BRCM_FET_SHDW_MISCCTRL 0x10 /* Shadow misc ctrl */
  251. #define MII_BRCM_FET_SHDW_MC_FAME 0x4000 /* Force Auto MDIX enable */
  252. #define MII_BRCM_FET_SHDW_AUXMODE4 0x1a /* Auxiliary mode 4 */
  253. #define MII_BRCM_FET_SHDW_AM4_LED_MASK 0x0003
  254. #define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001
  255. #define MII_BRCM_FET_SHDW_AUXSTAT2 0x1b /* Auxiliary status 2 */
  256. #define MII_BRCM_FET_SHDW_AS2_APDE 0x0020 /* Auto power down enable */
  257. #define BRCM_CL45VEN_EEE_CONTROL 0x803d
  258. #define LPI_FEATURE_EN 0x8000
  259. #define LPI_FEATURE_EN_DIG1000X 0x4000
  260. /* Core register definitions*/
  261. #define MII_BRCM_CORE_BASE12 0x12
  262. #define MII_BRCM_CORE_BASE13 0x13
  263. #define MII_BRCM_CORE_BASE14 0x14
  264. #define MII_BRCM_CORE_BASE1E 0x1E
  265. #define MII_BRCM_CORE_EXPB0 0xB0
  266. #define MII_BRCM_CORE_EXPB1 0xB1
  267. /* Enhanced Cable Diagnostics */
  268. #define BCM54XX_RDB_ECD_CTRL 0x2a0
  269. #define BCM54XX_EXP_ECD_CTRL (MII_BCM54XX_EXP_SEL_ER + 0xc0)
  270. #define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT3 1 /* CAT3 or worse */
  271. #define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT5 0 /* CAT5 or better */
  272. #define BCM54XX_ECD_CTRL_CABLE_TYPE_MASK BIT(0) /* cable type */
  273. #define BCM54XX_ECD_CTRL_INVALID BIT(3) /* invalid result */
  274. #define BCM54XX_ECD_CTRL_UNIT_CM 0 /* centimeters */
  275. #define BCM54XX_ECD_CTRL_UNIT_M 1 /* meters */
  276. #define BCM54XX_ECD_CTRL_UNIT_MASK BIT(10) /* cable length unit */
  277. #define BCM54XX_ECD_CTRL_IN_PROGRESS BIT(11) /* test in progress */
  278. #define BCM54XX_ECD_CTRL_BREAK_LINK BIT(12) /* unconnect link
  279. * during test
  280. */
  281. #define BCM54XX_ECD_CTRL_CROSS_SHORT_DIS BIT(13) /* disable inter-pair
  282. * short check
  283. */
  284. #define BCM54XX_ECD_CTRL_RUN BIT(15) /* run immediate */
  285. #define BCM54XX_RDB_ECD_FAULT_TYPE 0x2a1
  286. #define BCM54XX_EXP_ECD_FAULT_TYPE (MII_BCM54XX_EXP_SEL_ER + 0xc1)
  287. #define BCM54XX_ECD_FAULT_TYPE_INVALID 0x0
  288. #define BCM54XX_ECD_FAULT_TYPE_OK 0x1
  289. #define BCM54XX_ECD_FAULT_TYPE_OPEN 0x2
  290. #define BCM54XX_ECD_FAULT_TYPE_SAME_SHORT 0x3 /* short same pair */
  291. #define BCM54XX_ECD_FAULT_TYPE_CROSS_SHORT 0x4 /* short different pairs */
  292. #define BCM54XX_ECD_FAULT_TYPE_BUSY 0x9
  293. #define BCM54XX_ECD_FAULT_TYPE_PAIR_D_MASK GENMASK(3, 0)
  294. #define BCM54XX_ECD_FAULT_TYPE_PAIR_C_MASK GENMASK(7, 4)
  295. #define BCM54XX_ECD_FAULT_TYPE_PAIR_B_MASK GENMASK(11, 8)
  296. #define BCM54XX_ECD_FAULT_TYPE_PAIR_A_MASK GENMASK(15, 12)
  297. #define BCM54XX_ECD_PAIR_A_LENGTH_RESULTS 0x2a2
  298. #define BCM54XX_ECD_PAIR_B_LENGTH_RESULTS 0x2a3
  299. #define BCM54XX_ECD_PAIR_C_LENGTH_RESULTS 0x2a4
  300. #define BCM54XX_ECD_PAIR_D_LENGTH_RESULTS 0x2a5
  301. #define BCM54XX_RDB_ECD_PAIR_A_LENGTH_RESULTS 0x2a2
  302. #define BCM54XX_EXP_ECD_PAIR_A_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc2)
  303. #define BCM54XX_RDB_ECD_PAIR_B_LENGTH_RESULTS 0x2a3
  304. #define BCM54XX_EXP_ECD_PAIR_B_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc3)
  305. #define BCM54XX_RDB_ECD_PAIR_C_LENGTH_RESULTS 0x2a4
  306. #define BCM54XX_EXP_ECD_PAIR_C_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc4)
  307. #define BCM54XX_RDB_ECD_PAIR_D_LENGTH_RESULTS 0x2a5
  308. #define BCM54XX_EXP_ECD_PAIR_D_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc5)
  309. #define BCM54XX_ECD_LENGTH_RESULTS_INVALID 0xffff
  310. #endif /* _LINUX_BRCMPHY_H */