bcma_driver_chipcommon.h 32 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef LINUX_BCMA_DRIVER_CC_H_
  3. #define LINUX_BCMA_DRIVER_CC_H_
  4. #include <linux/platform_device.h>
  5. #include <linux/gpio.h>
  6. /** ChipCommon core registers. **/
  7. #define BCMA_CC_ID 0x0000
  8. #define BCMA_CC_ID_ID 0x0000FFFF
  9. #define BCMA_CC_ID_ID_SHIFT 0
  10. #define BCMA_CC_ID_REV 0x000F0000
  11. #define BCMA_CC_ID_REV_SHIFT 16
  12. #define BCMA_CC_ID_PKG 0x00F00000
  13. #define BCMA_CC_ID_PKG_SHIFT 20
  14. #define BCMA_CC_ID_NRCORES 0x0F000000
  15. #define BCMA_CC_ID_NRCORES_SHIFT 24
  16. #define BCMA_CC_ID_TYPE 0xF0000000
  17. #define BCMA_CC_ID_TYPE_SHIFT 28
  18. #define BCMA_CC_CAP 0x0004 /* Capabilities */
  19. #define BCMA_CC_CAP_NRUART 0x00000003 /* # of UARTs */
  20. #define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
  21. #define BCMA_CC_CAP_UARTCLK 0x00000018 /* UART clock select */
  22. #define BCMA_CC_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */
  23. #define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
  24. #define BCMA_CC_CAP_EXTBUS 0x000000C0 /* External buses present */
  25. #define BCMA_CC_CAP_FLASHT 0x00000700 /* Flash Type */
  26. #define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
  27. #define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
  28. #define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
  29. #define BCMA_CC_FLASHT_NAND 0x00000300 /* NAND flash */
  30. #define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
  31. #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
  32. #define BCMA_PLLTYPE_NONE 0x00000000
  33. #define BCMA_PLLTYPE_1 0x00010000 /* 48Mhz base, 3 dividers */
  34. #define BCMA_PLLTYPE_2 0x00020000 /* 48Mhz, 4 dividers */
  35. #define BCMA_PLLTYPE_3 0x00030000 /* 25Mhz, 2 dividers */
  36. #define BCMA_PLLTYPE_4 0x00008000 /* 48Mhz, 4 dividers */
  37. #define BCMA_PLLTYPE_5 0x00018000 /* 25Mhz, 4 dividers */
  38. #define BCMA_PLLTYPE_6 0x00028000 /* 100/200 or 120/240 only */
  39. #define BCMA_PLLTYPE_7 0x00038000 /* 25Mhz, 4 dividers */
  40. #define BCMA_CC_CAP_PCTL 0x00040000 /* Power Control */
  41. #define BCMA_CC_CAP_OTPS 0x00380000 /* OTP size */
  42. #define BCMA_CC_CAP_OTPS_SHIFT 19
  43. #define BCMA_CC_CAP_OTPS_BASE 5
  44. #define BCMA_CC_CAP_JTAGM 0x00400000 /* JTAG master present */
  45. #define BCMA_CC_CAP_BROM 0x00800000 /* Internal boot ROM active */
  46. #define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */
  47. #define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
  48. #define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
  49. #define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */
  50. #define BCMA_CC_CAP_NFLASH 0x80000000 /* NAND flash present (rev >= 35 or BCM4706?) */
  51. #define BCMA_CC_CORECTL 0x0008
  52. #define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
  53. #define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
  54. #define BCMA_CC_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */
  55. #define BCMA_CC_BIST 0x000C
  56. #define BCMA_CC_OTPS 0x0010 /* OTP status */
  57. #define BCMA_CC_OTPS_PROGFAIL 0x80000000
  58. #define BCMA_CC_OTPS_PROTECT 0x00000007
  59. #define BCMA_CC_OTPS_HW_PROTECT 0x00000001
  60. #define BCMA_CC_OTPS_SW_PROTECT 0x00000002
  61. #define BCMA_CC_OTPS_CID_PROTECT 0x00000004
  62. #define BCMA_CC_OTPS_GU_PROG_IND 0x00000F00 /* General Use programmed indication */
  63. #define BCMA_CC_OTPS_GU_PROG_IND_SHIFT 8
  64. #define BCMA_CC_OTPS_GU_PROG_HW 0x00000100 /* HW region programmed */
  65. #define BCMA_CC_OTPC 0x0014 /* OTP control */
  66. #define BCMA_CC_OTPC_RECWAIT 0xFF000000
  67. #define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00
  68. #define BCMA_CC_OTPC_PRW_SHIFT 8
  69. #define BCMA_CC_OTPC_MAXFAIL 0x00000038
  70. #define BCMA_CC_OTPC_VSEL 0x00000006
  71. #define BCMA_CC_OTPC_SELVL 0x00000001
  72. #define BCMA_CC_OTPP 0x0018 /* OTP prog */
  73. #define BCMA_CC_OTPP_COL 0x000000FF
  74. #define BCMA_CC_OTPP_ROW 0x0000FF00
  75. #define BCMA_CC_OTPP_ROW_SHIFT 8
  76. #define BCMA_CC_OTPP_READERR 0x10000000
  77. #define BCMA_CC_OTPP_VALUE 0x20000000
  78. #define BCMA_CC_OTPP_READ 0x40000000
  79. #define BCMA_CC_OTPP_START 0x80000000
  80. #define BCMA_CC_OTPP_BUSY 0x80000000
  81. #define BCMA_CC_OTPL 0x001C /* OTP layout */
  82. #define BCMA_CC_OTPL_GURGN_OFFSET 0x00000FFF /* offset of general use region */
  83. #define BCMA_CC_IRQSTAT 0x0020
  84. #define BCMA_CC_IRQMASK 0x0024
  85. #define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */
  86. #define BCMA_CC_IRQ_EXT 0x00000002 /* ro: ext intr pin (corerev >= 3) */
  87. #define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
  88. #define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
  89. #define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
  90. #define BCMA_CC_CHIPST_4313_SPROM_PRESENT 1
  91. #define BCMA_CC_CHIPST_4313_OTP_PRESENT 2
  92. #define BCMA_CC_CHIPST_4331_SPROM_PRESENT 2
  93. #define BCMA_CC_CHIPST_4331_OTP_PRESENT 4
  94. #define BCMA_CC_CHIPST_43228_ILP_DIV_EN 0x00000001
  95. #define BCMA_CC_CHIPST_43228_OTP_PRESENT 0x00000002
  96. #define BCMA_CC_CHIPST_43228_SERDES_REFCLK_PADSEL 0x00000004
  97. #define BCMA_CC_CHIPST_43228_SDIO_MODE 0x00000008
  98. #define BCMA_CC_CHIPST_43228_SDIO_OTP_PRESENT 0x00000010
  99. #define BCMA_CC_CHIPST_43228_SDIO_RESET 0x00000020
  100. #define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
  101. #define BCMA_CC_CHIPST_4706_SFLASH_PRESENT BIT(1) /* 0: parallel, 1: serial flash is present */
  102. #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
  103. #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
  104. #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
  105. #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
  106. #define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001
  107. #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
  108. #define BCMA_CC_JCMD_START 0x80000000
  109. #define BCMA_CC_JCMD_BUSY 0x80000000
  110. #define BCMA_CC_JCMD_PAUSE 0x40000000
  111. #define BCMA_CC_JCMD0_ACC_MASK 0x0000F000
  112. #define BCMA_CC_JCMD0_ACC_IRDR 0x00000000
  113. #define BCMA_CC_JCMD0_ACC_DR 0x00001000
  114. #define BCMA_CC_JCMD0_ACC_IR 0x00002000
  115. #define BCMA_CC_JCMD0_ACC_RESET 0x00003000
  116. #define BCMA_CC_JCMD0_ACC_IRPDR 0x00004000
  117. #define BCMA_CC_JCMD0_ACC_PDR 0x00005000
  118. #define BCMA_CC_JCMD0_IRW_MASK 0x00000F00
  119. #define BCMA_CC_JCMD_ACC_MASK 0x000F0000 /* Changes for corerev 11 */
  120. #define BCMA_CC_JCMD_ACC_IRDR 0x00000000
  121. #define BCMA_CC_JCMD_ACC_DR 0x00010000
  122. #define BCMA_CC_JCMD_ACC_IR 0x00020000
  123. #define BCMA_CC_JCMD_ACC_RESET 0x00030000
  124. #define BCMA_CC_JCMD_ACC_IRPDR 0x00040000
  125. #define BCMA_CC_JCMD_ACC_PDR 0x00050000
  126. #define BCMA_CC_JCMD_IRW_MASK 0x00001F00
  127. #define BCMA_CC_JCMD_IRW_SHIFT 8
  128. #define BCMA_CC_JCMD_DRW_MASK 0x0000003F
  129. #define BCMA_CC_JIR 0x0034 /* Rev >= 10 only */
  130. #define BCMA_CC_JDR 0x0038 /* Rev >= 10 only */
  131. #define BCMA_CC_JCTL 0x003C /* Rev >= 10 only */
  132. #define BCMA_CC_JCTL_FORCE_CLK 4 /* Force clock */
  133. #define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */
  134. #define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */
  135. #define BCMA_CC_FLASHCTL 0x0040
  136. /* Start/busy bit in flashcontrol */
  137. #define BCMA_CC_FLASHCTL_OPCODE 0x000000ff
  138. #define BCMA_CC_FLASHCTL_ACTION 0x00000700
  139. #define BCMA_CC_FLASHCTL_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */
  140. #define BCMA_CC_FLASHCTL_START 0x80000000
  141. #define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START
  142. /* Flashcontrol action + opcodes for ST flashes */
  143. #define BCMA_CC_FLASHCTL_ST_WREN 0x0006 /* Write Enable */
  144. #define BCMA_CC_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */
  145. #define BCMA_CC_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */
  146. #define BCMA_CC_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */
  147. #define BCMA_CC_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */
  148. #define BCMA_CC_FLASHCTL_ST_PP 0x0302 /* Page Program */
  149. #define BCMA_CC_FLASHCTL_ST_SE 0x02d8 /* Sector Erase */
  150. #define BCMA_CC_FLASHCTL_ST_BE 0x00c7 /* Bulk Erase */
  151. #define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */
  152. #define BCMA_CC_FLASHCTL_ST_RES 0x03ab /* Read Electronic Signature */
  153. #define BCMA_CC_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
  154. #define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
  155. /* Flashcontrol action + opcodes for Atmel flashes */
  156. #define BCMA_CC_FLASHCTL_AT_READ 0x07e8
  157. #define BCMA_CC_FLASHCTL_AT_PAGE_READ 0x07d2
  158. #define BCMA_CC_FLASHCTL_AT_STATUS 0x01d7
  159. #define BCMA_CC_FLASHCTL_AT_BUF1_WRITE 0x0384
  160. #define BCMA_CC_FLASHCTL_AT_BUF2_WRITE 0x0387
  161. #define BCMA_CC_FLASHCTL_AT_BUF1_ERASE_PROGRAM 0x0283
  162. #define BCMA_CC_FLASHCTL_AT_BUF2_ERASE_PROGRAM 0x0286
  163. #define BCMA_CC_FLASHCTL_AT_BUF1_PROGRAM 0x0288
  164. #define BCMA_CC_FLASHCTL_AT_BUF2_PROGRAM 0x0289
  165. #define BCMA_CC_FLASHCTL_AT_PAGE_ERASE 0x0281
  166. #define BCMA_CC_FLASHCTL_AT_BLOCK_ERASE 0x0250
  167. #define BCMA_CC_FLASHCTL_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
  168. #define BCMA_CC_FLASHCTL_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
  169. #define BCMA_CC_FLASHCTL_AT_BUF1_LOAD 0x0253
  170. #define BCMA_CC_FLASHCTL_AT_BUF2_LOAD 0x0255
  171. #define BCMA_CC_FLASHCTL_AT_BUF1_COMPARE 0x0260
  172. #define BCMA_CC_FLASHCTL_AT_BUF2_COMPARE 0x0261
  173. #define BCMA_CC_FLASHCTL_AT_BUF1_REPROGRAM 0x0258
  174. #define BCMA_CC_FLASHCTL_AT_BUF2_REPROGRAM 0x0259
  175. #define BCMA_CC_FLASHADDR 0x0044
  176. #define BCMA_CC_FLASHDATA 0x0048
  177. /* Status register bits for ST flashes */
  178. #define BCMA_CC_FLASHDATA_ST_WIP 0x01 /* Write In Progress */
  179. #define BCMA_CC_FLASHDATA_ST_WEL 0x02 /* Write Enable Latch */
  180. #define BCMA_CC_FLASHDATA_ST_BP_MASK 0x1c /* Block Protect */
  181. #define BCMA_CC_FLASHDATA_ST_BP_SHIFT 2
  182. #define BCMA_CC_FLASHDATA_ST_SRWD 0x80 /* Status Register Write Disable */
  183. /* Status register bits for Atmel flashes */
  184. #define BCMA_CC_FLASHDATA_AT_READY 0x80
  185. #define BCMA_CC_FLASHDATA_AT_MISMATCH 0x40
  186. #define BCMA_CC_FLASHDATA_AT_ID_MASK 0x38
  187. #define BCMA_CC_FLASHDATA_AT_ID_SHIFT 3
  188. #define BCMA_CC_BCAST_ADDR 0x0050
  189. #define BCMA_CC_BCAST_DATA 0x0054
  190. #define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */
  191. #define BCMA_CC_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
  192. #define BCMA_CC_GPIOIN 0x0060
  193. #define BCMA_CC_GPIOOUT 0x0064
  194. #define BCMA_CC_GPIOOUTEN 0x0068
  195. #define BCMA_CC_GPIOCTL 0x006C
  196. #define BCMA_CC_GPIOPOL 0x0070
  197. #define BCMA_CC_GPIOIRQ 0x0074
  198. #define BCMA_CC_WATCHDOG 0x0080
  199. #define BCMA_CC_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
  200. #define BCMA_CC_GPIOTIMER_OFFTIME 0x0000FFFF
  201. #define BCMA_CC_GPIOTIMER_OFFTIME_SHIFT 0
  202. #define BCMA_CC_GPIOTIMER_ONTIME 0xFFFF0000
  203. #define BCMA_CC_GPIOTIMER_ONTIME_SHIFT 16
  204. #define BCMA_CC_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
  205. #define BCMA_CC_CLOCK_N 0x0090
  206. #define BCMA_CC_CLOCK_SB 0x0094
  207. #define BCMA_CC_CLOCK_PCI 0x0098
  208. #define BCMA_CC_CLOCK_M2 0x009C
  209. #define BCMA_CC_CLOCK_MIPS 0x00A0
  210. #define BCMA_CC_CLKDIV 0x00A4 /* Rev >= 3 only */
  211. #define BCMA_CC_CLKDIV_SFLASH 0x0F000000
  212. #define BCMA_CC_CLKDIV_SFLASH_SHIFT 24
  213. #define BCMA_CC_CLKDIV_OTP 0x000F0000
  214. #define BCMA_CC_CLKDIV_OTP_SHIFT 16
  215. #define BCMA_CC_CLKDIV_JTAG 0x00000F00
  216. #define BCMA_CC_CLKDIV_JTAG_SHIFT 8
  217. #define BCMA_CC_CLKDIV_UART 0x000000FF
  218. #define BCMA_CC_CAP_EXT 0x00AC /* Capabilities */
  219. #define BCMA_CC_CAP_EXT_SECI_PRESENT 0x00000001
  220. #define BCMA_CC_CAP_EXT_GSIO_PRESENT 0x00000002
  221. #define BCMA_CC_CAP_EXT_GCI_PRESENT 0x00000004
  222. #define BCMA_CC_CAP_EXT_SECI_PUART_PRESENT 0x00000008 /* UART present */
  223. #define BCMA_CC_CAP_EXT_AOB_PRESENT 0x00000040
  224. #define BCMA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */
  225. #define BCMA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */
  226. #define BCMA_CC_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */
  227. #define BCMA_CC_SLOWCLKCTL_SRC 0x00000007 /* slow clock source mask */
  228. #define BCMA_CC_SLOWCLKCTL_SRC_LPO 0x00000000 /* source of slow clock is LPO */
  229. #define BCMA_CC_SLOWCLKCTL_SRC_XTAL 0x00000001 /* source of slow clock is crystal */
  230. #define BCMA_CC_SLOECLKCTL_SRC_PCI 0x00000002 /* source of slow clock is PCI */
  231. #define BCMA_CC_SLOWCLKCTL_LPOFREQ 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
  232. #define BCMA_CC_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
  233. #define BCMA_CC_SLOWCLKCTL_FSLOW 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
  234. #define BCMA_CC_SLOWCLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
  235. #define BCMA_CC_SLOWCLKCTL_ENXTAL 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
  236. #define BCMA_CC_SLOWCLKCTL_XTALPU 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
  237. #define BCMA_CC_SLOWCLKCTL_CLKDIV 0xFFFF0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
  238. #define BCMA_CC_SLOWCLKCTL_CLKDIV_SHIFT 16
  239. #define BCMA_CC_SYSCLKCTL 0x00C0 /* Rev >= 3 only */
  240. #define BCMA_CC_SYSCLKCTL_IDLPEN 0x00000001 /* ILPen: Enable Idle Low Power */
  241. #define BCMA_CC_SYSCLKCTL_ALPEN 0x00000002 /* ALPen: Enable Active Low Power */
  242. #define BCMA_CC_SYSCLKCTL_PLLEN 0x00000004 /* ForcePLLOn */
  243. #define BCMA_CC_SYSCLKCTL_FORCEALP 0x00000008 /* Force ALP (or HT if ALPen is not set */
  244. #define BCMA_CC_SYSCLKCTL_FORCEHT 0x00000010 /* Force HT */
  245. #define BCMA_CC_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */
  246. #define BCMA_CC_SYSCLKCTL_CLKDIV_SHIFT 16
  247. #define BCMA_CC_CLKSTSTR 0x00C4 /* Rev >= 3 only */
  248. #define BCMA_CC_EROM 0x00FC
  249. #define BCMA_CC_PCMCIA_CFG 0x0100
  250. #define BCMA_CC_PCMCIA_MEMWAIT 0x0104
  251. #define BCMA_CC_PCMCIA_ATTRWAIT 0x0108
  252. #define BCMA_CC_PCMCIA_IOWAIT 0x010C
  253. #define BCMA_CC_IDE_CFG 0x0110
  254. #define BCMA_CC_IDE_MEMWAIT 0x0114
  255. #define BCMA_CC_IDE_ATTRWAIT 0x0118
  256. #define BCMA_CC_IDE_IOWAIT 0x011C
  257. #define BCMA_CC_PROG_CFG 0x0120
  258. #define BCMA_CC_PROG_WAITCNT 0x0124
  259. #define BCMA_CC_FLASH_CFG 0x0128
  260. #define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
  261. #define BCMA_CC_FLASH_WAITCNT 0x012C
  262. #define BCMA_CC_SROM_CONTROL 0x0190
  263. #define BCMA_CC_SROM_CONTROL_START 0x80000000
  264. #define BCMA_CC_SROM_CONTROL_BUSY 0x80000000
  265. #define BCMA_CC_SROM_CONTROL_OPCODE 0x60000000
  266. #define BCMA_CC_SROM_CONTROL_OP_READ 0x00000000
  267. #define BCMA_CC_SROM_CONTROL_OP_WRITE 0x20000000
  268. #define BCMA_CC_SROM_CONTROL_OP_WRDIS 0x40000000
  269. #define BCMA_CC_SROM_CONTROL_OP_WREN 0x60000000
  270. #define BCMA_CC_SROM_CONTROL_OTPSEL 0x00000010
  271. #define BCMA_CC_SROM_CONTROL_LOCK 0x00000008
  272. #define BCMA_CC_SROM_CONTROL_SIZE_MASK 0x00000006
  273. #define BCMA_CC_SROM_CONTROL_SIZE_1K 0x00000000
  274. #define BCMA_CC_SROM_CONTROL_SIZE_4K 0x00000002
  275. #define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
  276. #define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
  277. #define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
  278. /* Block 0x140 - 0x190 registers are chipset specific */
  279. #define BCMA_CC_4706_FLASHSCFG 0x18C /* Flash struct configuration */
  280. #define BCMA_CC_4706_FLASHSCFG_MASK 0x000000ff
  281. #define BCMA_CC_4706_FLASHSCFG_SF1 0x00000001 /* 2nd serial flash present */
  282. #define BCMA_CC_4706_FLASHSCFG_PF1 0x00000002 /* 2nd parallel flash present */
  283. #define BCMA_CC_4706_FLASHSCFG_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */
  284. #define BCMA_CC_4706_FLASHSCFG_NF1 0x00000008 /* 2nd NAND flash present */
  285. #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK 0x000000f0
  286. #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */
  287. #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */
  288. #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */
  289. #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */
  290. #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */
  291. #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */
  292. #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */
  293. /* NAND flash registers for BCM4706 (corerev = 31) */
  294. #define BCMA_CC_NFLASH_CTL 0x01A0
  295. #define BCMA_CC_NFLASH_CTL_ERR 0x08000000
  296. #define BCMA_CC_NFLASH_CONF 0x01A4
  297. #define BCMA_CC_NFLASH_COL_ADDR 0x01A8
  298. #define BCMA_CC_NFLASH_ROW_ADDR 0x01AC
  299. #define BCMA_CC_NFLASH_DATA 0x01B0
  300. #define BCMA_CC_NFLASH_WAITCNT0 0x01B4
  301. /* 0x1E0 is defined as shared BCMA_CLKCTLST */
  302. #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
  303. #define BCMA_CC_UART0_DATA 0x0300
  304. #define BCMA_CC_UART0_IMR 0x0304
  305. #define BCMA_CC_UART0_FCR 0x0308
  306. #define BCMA_CC_UART0_LCR 0x030C
  307. #define BCMA_CC_UART0_MCR 0x0310
  308. #define BCMA_CC_UART0_LSR 0x0314
  309. #define BCMA_CC_UART0_MSR 0x0318
  310. #define BCMA_CC_UART0_SCRATCH 0x031C
  311. #define BCMA_CC_UART1_DATA 0x0400
  312. #define BCMA_CC_UART1_IMR 0x0404
  313. #define BCMA_CC_UART1_FCR 0x0408
  314. #define BCMA_CC_UART1_LCR 0x040C
  315. #define BCMA_CC_UART1_MCR 0x0410
  316. #define BCMA_CC_UART1_LSR 0x0414
  317. #define BCMA_CC_UART1_MSR 0x0418
  318. #define BCMA_CC_UART1_SCRATCH 0x041C
  319. /* PMU registers (rev >= 20) */
  320. #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
  321. #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
  322. #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
  323. #define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */
  324. #define BCMA_CC_PMU_CTL_RES_SHIFT 13
  325. #define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */
  326. #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
  327. #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
  328. #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
  329. #define BCMA_CC_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
  330. #define BCMA_CC_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */
  331. #define BCMA_CC_PMU_CTL_XTALFREQ_SHIFT 2
  332. #define BCMA_CC_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */
  333. #define BCMA_CC_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */
  334. #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
  335. #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
  336. #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
  337. #define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100
  338. #define BCMA_CC_PMU_STAT_WDRESET 0x00000080
  339. #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
  340. #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
  341. #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
  342. #define BCMA_CC_PMU_STAT_HAVEHT 0x00000004 /* HT available */
  343. #define BCMA_CC_PMU_STAT_RESINIT 0x00000003 /* Res init */
  344. #define BCMA_CC_PMU_RES_STAT 0x060C /* PMU res status */
  345. #define BCMA_CC_PMU_RES_PEND 0x0610 /* PMU res pending */
  346. #define BCMA_CC_PMU_TIMER 0x0614 /* PMU timer */
  347. #define BCMA_CC_PMU_MINRES_MSK 0x0618 /* PMU min res mask */
  348. #define BCMA_CC_PMU_MAXRES_MSK 0x061C /* PMU max res mask */
  349. #define BCMA_CC_PMU_RES_TABSEL 0x0620 /* PMU res table sel */
  350. #define BCMA_CC_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */
  351. #define BCMA_CC_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */
  352. #define BCMA_CC_PMU_RES_TIMER 0x062C /* PMU res timer */
  353. #define BCMA_CC_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */
  354. #define BCMA_CC_PMU_WATCHDOG 0x0634 /* PMU watchdog */
  355. #define BCMA_CC_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
  356. #define BCMA_CC_PMU_RES_REQT 0x0644 /* PMU res req timer */
  357. #define BCMA_CC_PMU_RES_REQM 0x0648 /* PMU res req mask */
  358. #define BCMA_CC_PMU_CHIPCTL_ADDR 0x0650
  359. #define BCMA_CC_PMU_CHIPCTL_DATA 0x0654
  360. #define BCMA_CC_PMU_REGCTL_ADDR 0x0658
  361. #define BCMA_CC_PMU_REGCTL_DATA 0x065C
  362. #define BCMA_CC_PMU_PLLCTL_ADDR 0x0660
  363. #define BCMA_CC_PMU_PLLCTL_DATA 0x0664
  364. #define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
  365. #define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
  366. #define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
  367. #define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000
  368. #define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31
  369. #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
  370. /* NAND flash MLC controller registers (corerev >= 38) */
  371. #define BCMA_CC_NAND_REVISION 0x0C00
  372. #define BCMA_CC_NAND_CMD_START 0x0C04
  373. #define BCMA_CC_NAND_CMD_ADDR_X 0x0C08
  374. #define BCMA_CC_NAND_CMD_ADDR 0x0C0C
  375. #define BCMA_CC_NAND_CMD_END_ADDR 0x0C10
  376. #define BCMA_CC_NAND_CS_NAND_SELECT 0x0C14
  377. #define BCMA_CC_NAND_CS_NAND_XOR 0x0C18
  378. #define BCMA_CC_NAND_SPARE_RD0 0x0C20
  379. #define BCMA_CC_NAND_SPARE_RD4 0x0C24
  380. #define BCMA_CC_NAND_SPARE_RD8 0x0C28
  381. #define BCMA_CC_NAND_SPARE_RD12 0x0C2C
  382. #define BCMA_CC_NAND_SPARE_WR0 0x0C30
  383. #define BCMA_CC_NAND_SPARE_WR4 0x0C34
  384. #define BCMA_CC_NAND_SPARE_WR8 0x0C38
  385. #define BCMA_CC_NAND_SPARE_WR12 0x0C3C
  386. #define BCMA_CC_NAND_ACC_CONTROL 0x0C40
  387. #define BCMA_CC_NAND_CONFIG 0x0C48
  388. #define BCMA_CC_NAND_TIMING_1 0x0C50
  389. #define BCMA_CC_NAND_TIMING_2 0x0C54
  390. #define BCMA_CC_NAND_SEMAPHORE 0x0C58
  391. #define BCMA_CC_NAND_DEVID 0x0C60
  392. #define BCMA_CC_NAND_DEVID_X 0x0C64
  393. #define BCMA_CC_NAND_BLOCK_LOCK_STATUS 0x0C68
  394. #define BCMA_CC_NAND_INTFC_STATUS 0x0C6C
  395. #define BCMA_CC_NAND_ECC_CORR_ADDR_X 0x0C70
  396. #define BCMA_CC_NAND_ECC_CORR_ADDR 0x0C74
  397. #define BCMA_CC_NAND_ECC_UNC_ADDR_X 0x0C78
  398. #define BCMA_CC_NAND_ECC_UNC_ADDR 0x0C7C
  399. #define BCMA_CC_NAND_READ_ERROR_COUNT 0x0C80
  400. #define BCMA_CC_NAND_CORR_STAT_THRESHOLD 0x0C84
  401. #define BCMA_CC_NAND_READ_ADDR_X 0x0C90
  402. #define BCMA_CC_NAND_READ_ADDR 0x0C94
  403. #define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X 0x0C98
  404. #define BCMA_CC_NAND_PAGE_PROGRAM_ADDR 0x0C9C
  405. #define BCMA_CC_NAND_COPY_BACK_ADDR_X 0x0CA0
  406. #define BCMA_CC_NAND_COPY_BACK_ADDR 0x0CA4
  407. #define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X 0x0CA8
  408. #define BCMA_CC_NAND_BLOCK_ERASE_ADDR 0x0CAC
  409. #define BCMA_CC_NAND_INV_READ_ADDR_X 0x0CB0
  410. #define BCMA_CC_NAND_INV_READ_ADDR 0x0CB4
  411. #define BCMA_CC_NAND_BLK_WR_PROTECT 0x0CC0
  412. #define BCMA_CC_NAND_ACC_CONTROL_CS1 0x0CD0
  413. #define BCMA_CC_NAND_CONFIG_CS1 0x0CD4
  414. #define BCMA_CC_NAND_TIMING_1_CS1 0x0CD8
  415. #define BCMA_CC_NAND_TIMING_2_CS1 0x0CDC
  416. #define BCMA_CC_NAND_SPARE_RD16 0x0D30
  417. #define BCMA_CC_NAND_SPARE_RD20 0x0D34
  418. #define BCMA_CC_NAND_SPARE_RD24 0x0D38
  419. #define BCMA_CC_NAND_SPARE_RD28 0x0D3C
  420. #define BCMA_CC_NAND_CACHE_ADDR 0x0D40
  421. #define BCMA_CC_NAND_CACHE_DATA 0x0D44
  422. #define BCMA_CC_NAND_CTRL_CONFIG 0x0D48
  423. #define BCMA_CC_NAND_CTRL_STATUS 0x0D4C
  424. /* Divider allocation in 4716/47162/5356 */
  425. #define BCMA_CC_PMU5_MAINPLL_CPU 1
  426. #define BCMA_CC_PMU5_MAINPLL_MEM 2
  427. #define BCMA_CC_PMU5_MAINPLL_SSB 3
  428. /* PLL usage in 4716/47162 */
  429. #define BCMA_CC_PMU4716_MAINPLL_PLL0 12
  430. /* PLL usage in 5356/5357 */
  431. #define BCMA_CC_PMU5356_MAINPLL_PLL0 0
  432. #define BCMA_CC_PMU5357_MAINPLL_PLL0 0
  433. /* 4706 PMU */
  434. #define BCMA_CC_PMU4706_MAINPLL_PLL0 0
  435. #define BCMA_CC_PMU6_4706_PROCPLL_OFF 4 /* The CPU PLL */
  436. #define BCMA_CC_PMU6_4706_PROC_P2DIV_MASK 0x000f0000
  437. #define BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT 16
  438. #define BCMA_CC_PMU6_4706_PROC_P1DIV_MASK 0x0000f000
  439. #define BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT 12
  440. #define BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK 0x00000ff8
  441. #define BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT 3
  442. #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
  443. #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
  444. /* PMU rev 15 */
  445. #define BCMA_CC_PMU15_PLL_PLLCTL0 0
  446. #define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
  447. #define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT 0
  448. #define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
  449. #define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT 2
  450. #define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
  451. #define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT 22
  452. #define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
  453. #define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT 24
  454. #define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
  455. #define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT 27
  456. #define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
  457. #define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT 30
  458. #define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
  459. #define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT 31
  460. /* ALP clock on pre-PMU chips */
  461. #define BCMA_CC_PMU_ALP_CLOCK 20000000
  462. /* HT clock for systems with PMU-enabled chipcommon */
  463. #define BCMA_CC_PMU_HT_CLOCK 80000000
  464. /* PMU rev 5 (& 6) */
  465. #define BCMA_CC_PPL_P1P2_OFF 0
  466. #define BCMA_CC_PPL_P1_MASK 0x0f000000
  467. #define BCMA_CC_PPL_P1_SHIFT 24
  468. #define BCMA_CC_PPL_P2_MASK 0x00f00000
  469. #define BCMA_CC_PPL_P2_SHIFT 20
  470. #define BCMA_CC_PPL_M14_OFF 1
  471. #define BCMA_CC_PPL_MDIV_MASK 0x000000ff
  472. #define BCMA_CC_PPL_MDIV_WIDTH 8
  473. #define BCMA_CC_PPL_NM5_OFF 2
  474. #define BCMA_CC_PPL_NDIV_MASK 0xfff00000
  475. #define BCMA_CC_PPL_NDIV_SHIFT 20
  476. #define BCMA_CC_PPL_FMAB_OFF 3
  477. #define BCMA_CC_PPL_MRAT_MASK 0xf0000000
  478. #define BCMA_CC_PPL_MRAT_SHIFT 28
  479. #define BCMA_CC_PPL_ABRAT_MASK 0x08000000
  480. #define BCMA_CC_PPL_ABRAT_SHIFT 27
  481. #define BCMA_CC_PPL_FDIV_MASK 0x07ffffff
  482. #define BCMA_CC_PPL_PLLCTL_OFF 4
  483. #define BCMA_CC_PPL_PCHI_OFF 5
  484. #define BCMA_CC_PPL_PCHI_MASK 0x0000003f
  485. #define BCMA_CC_PMU_PLL_CTL0 0
  486. #define BCMA_CC_PMU_PLL_CTL1 1
  487. #define BCMA_CC_PMU_PLL_CTL2 2
  488. #define BCMA_CC_PMU_PLL_CTL3 3
  489. #define BCMA_CC_PMU_PLL_CTL4 4
  490. #define BCMA_CC_PMU_PLL_CTL5 5
  491. #define BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
  492. #define BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT 20
  493. #define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
  494. #define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
  495. #define BCMA_CCB_MII_MNG_CTL 0x0000
  496. #define BCMA_CCB_MII_MNG_CMD_DATA 0x0004
  497. /* BCM4331 ChipControl numbers. */
  498. #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
  499. #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
  500. #define BCMA_CHIPCTL_4331_EXT_LNA BIT(2) /* 0 disable */
  501. #define BCMA_CHIPCTL_4331_SPROM_GPIO13_15 BIT(3) /* sprom/gpio13-15 mux */
  502. #define BCMA_CHIPCTL_4331_EXTPA_EN BIT(4) /* 0 ext pa disable, 1 ext pa enabled */
  503. #define BCMA_CHIPCTL_4331_GPIOCLK_ON_SPROMCS BIT(5) /* set drive out GPIO_CLK on sprom_cs pin */
  504. #define BCMA_CHIPCTL_4331_PCIE_MDIO_ON_SPROMCS BIT(6) /* use sprom_cs pin as PCIE mdio interface */
  505. #define BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5 BIT(7) /* aband extpa will be at gpio2/5 and sprom_dout */
  506. #define BCMA_CHIPCTL_4331_OVR_PIPEAUXCLKEN BIT(8) /* override core control on pipe_AuxClkEnable */
  507. #define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */
  508. #define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */
  509. #define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */
  510. #define BCMA_CHIPCTL_4331_EXTPA_EN2 BIT(12) /* 0 ext pa disable, 1 ext pa enabled */
  511. #define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */
  512. #define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */
  513. /* 43224 chip-specific ChipControl register bits */
  514. #define BCMA_CCTRL_43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */
  515. #define BCMA_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */
  516. #define BCMA_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */
  517. /* 4313 Chip specific ChipControl register bits */
  518. #define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
  519. /* BCM5357 ChipControl register bits */
  520. #define BCMA_CHIPCTL_5357_EXTPA BIT(14)
  521. #define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15)
  522. #define BCMA_CHIPCTL_5357_NFLASH BIT(16)
  523. #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
  524. #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
  525. #define BCMA_RES_4314_LPLDO_PU BIT(0)
  526. #define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1)
  527. #define BCMA_RES_4314_PMU_BG_PU BIT(2)
  528. #define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3)
  529. #define BCMA_RES_4314_CBUCK_PFM_PU BIT(4)
  530. #define BCMA_RES_4314_CLDO_PU BIT(5)
  531. #define BCMA_RES_4314_LPLDO2_LVM BIT(6)
  532. #define BCMA_RES_4314_WL_PMU_PU BIT(7)
  533. #define BCMA_RES_4314_LNLDO_PU BIT(8)
  534. #define BCMA_RES_4314_LDO3P3_PU BIT(9)
  535. #define BCMA_RES_4314_OTP_PU BIT(10)
  536. #define BCMA_RES_4314_XTAL_PU BIT(11)
  537. #define BCMA_RES_4314_WL_PWRSW_PU BIT(12)
  538. #define BCMA_RES_4314_LQ_AVAIL BIT(13)
  539. #define BCMA_RES_4314_LOGIC_RET BIT(14)
  540. #define BCMA_RES_4314_MEM_SLEEP BIT(15)
  541. #define BCMA_RES_4314_MACPHY_RET BIT(16)
  542. #define BCMA_RES_4314_WL_CORE_READY BIT(17)
  543. #define BCMA_RES_4314_ILP_REQ BIT(18)
  544. #define BCMA_RES_4314_ALP_AVAIL BIT(19)
  545. #define BCMA_RES_4314_MISC_PWRSW_PU BIT(20)
  546. #define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21)
  547. #define BCMA_RES_4314_RX_PWRSW_PU BIT(22)
  548. #define BCMA_RES_4314_RADIO_PU BIT(23)
  549. #define BCMA_RES_4314_VCO_LDO_PU BIT(24)
  550. #define BCMA_RES_4314_AFE_LDO_PU BIT(25)
  551. #define BCMA_RES_4314_RX_LDO_PU BIT(26)
  552. #define BCMA_RES_4314_TX_LDO_PU BIT(27)
  553. #define BCMA_RES_4314_HT_AVAIL BIT(28)
  554. #define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29)
  555. /* Data for the PMU, if available.
  556. * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
  557. */
  558. struct bcma_chipcommon_pmu {
  559. struct bcma_device *core; /* Can be separated core or just ChipCommon one */
  560. u8 rev; /* PMU revision */
  561. u32 crystalfreq; /* The active crystal frequency (in kHz) */
  562. };
  563. #ifdef CONFIG_BCMA_PFLASH
  564. struct bcma_pflash {
  565. bool present;
  566. };
  567. #endif
  568. #ifdef CONFIG_BCMA_SFLASH
  569. struct mtd_info;
  570. struct bcma_sflash {
  571. bool present;
  572. u32 blocksize;
  573. u16 numblocks;
  574. u32 size;
  575. };
  576. #endif
  577. #ifdef CONFIG_BCMA_NFLASH
  578. struct bcma_nflash {
  579. bool present;
  580. bool boot; /* This is the flash the SoC boots from */
  581. };
  582. #endif
  583. #ifdef CONFIG_BCMA_DRIVER_MIPS
  584. struct bcma_serial_port {
  585. void *regs;
  586. unsigned long clockspeed;
  587. unsigned int irq;
  588. unsigned int baud_base;
  589. unsigned int reg_shift;
  590. };
  591. #endif /* CONFIG_BCMA_DRIVER_MIPS */
  592. struct bcma_drv_cc {
  593. struct bcma_device *core;
  594. u32 status;
  595. u32 capabilities;
  596. u32 capabilities_ext;
  597. u8 setup_done:1;
  598. u8 early_setup_done:1;
  599. /* Fast Powerup Delay constant */
  600. u16 fast_pwrup_delay;
  601. struct bcma_chipcommon_pmu pmu;
  602. #ifdef CONFIG_BCMA_PFLASH
  603. struct bcma_pflash pflash;
  604. #endif
  605. #ifdef CONFIG_BCMA_SFLASH
  606. struct bcma_sflash sflash;
  607. #endif
  608. #ifdef CONFIG_BCMA_NFLASH
  609. struct bcma_nflash nflash;
  610. #endif
  611. #ifdef CONFIG_BCMA_DRIVER_MIPS
  612. int nr_serial_ports;
  613. struct bcma_serial_port serial_ports[4];
  614. #endif /* CONFIG_BCMA_DRIVER_MIPS */
  615. u32 ticks_per_ms;
  616. struct platform_device *watchdog;
  617. /* Lock for GPIO register access. */
  618. spinlock_t gpio_lock;
  619. #ifdef CONFIG_BCMA_DRIVER_GPIO
  620. struct gpio_chip gpio;
  621. #endif
  622. };
  623. struct bcma_drv_cc_b {
  624. struct bcma_device *core;
  625. u8 setup_done:1;
  626. void __iomem *mii;
  627. };
  628. /* Register access */
  629. #define bcma_cc_read32(cc, offset) \
  630. bcma_read32((cc)->core, offset)
  631. #define bcma_cc_write32(cc, offset, val) \
  632. bcma_write32((cc)->core, offset, val)
  633. #define bcma_cc_mask32(cc, offset, mask) \
  634. bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) & (mask))
  635. #define bcma_cc_set32(cc, offset, set) \
  636. bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) | (set))
  637. #define bcma_cc_maskset32(cc, offset, mask, set) \
  638. bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
  639. /* PMU registers access */
  640. #define bcma_pmu_read32(cc, offset) \
  641. bcma_read32((cc)->pmu.core, offset)
  642. #define bcma_pmu_write32(cc, offset, val) \
  643. bcma_write32((cc)->pmu.core, offset, val)
  644. #define bcma_pmu_mask32(cc, offset, mask) \
  645. bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) & (mask))
  646. #define bcma_pmu_set32(cc, offset, set) \
  647. bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) | (set))
  648. #define bcma_pmu_maskset32(cc, offset, mask, set) \
  649. bcma_pmu_write32(cc, offset, (bcma_pmu_read32(cc, offset) & (mask)) | (set))
  650. extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
  651. extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
  652. void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
  653. u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
  654. /* Chipcommon GPIO pin access. */
  655. u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask);
  656. u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value);
  657. u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value);
  658. u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
  659. u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
  660. u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
  661. u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value);
  662. u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value);
  663. /* PMU support */
  664. extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
  665. u32 value);
  666. extern void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset,
  667. u32 mask, u32 set);
  668. extern void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
  669. u32 offset, u32 mask, u32 set);
  670. extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc,
  671. u32 offset, u32 mask, u32 set);
  672. extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
  673. extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc);
  674. void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value);
  675. #endif /* LINUX_BCMA_DRIVER_CC_H_ */