amd-iommu.h 6.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
  4. * Author: Joerg Roedel <joerg.roedel@amd.com>
  5. * Leo Duran <leo.duran@amd.com>
  6. */
  7. #ifndef _ASM_X86_AMD_IOMMU_H
  8. #define _ASM_X86_AMD_IOMMU_H
  9. #include <linux/types.h>
  10. /*
  11. * This is mainly used to communicate information back-and-forth
  12. * between SVM and IOMMU for setting up and tearing down posted
  13. * interrupt
  14. */
  15. struct amd_iommu_pi_data {
  16. u32 ga_tag;
  17. u32 prev_ga_tag;
  18. u64 base;
  19. bool is_guest_mode;
  20. struct vcpu_data *vcpu_data;
  21. void *ir_data;
  22. };
  23. #ifdef CONFIG_AMD_IOMMU
  24. struct task_struct;
  25. struct pci_dev;
  26. extern int amd_iommu_detect(void);
  27. extern int amd_iommu_init_hardware(void);
  28. /**
  29. * amd_iommu_enable_device_erratum() - Enable erratum workaround for device
  30. * in the IOMMUv2 driver
  31. * @pdev: The PCI device the workaround is necessary for
  32. * @erratum: The erratum workaround to enable
  33. *
  34. * The function needs to be called before amd_iommu_init_device().
  35. * Possible values for the erratum number are for now:
  36. * - AMD_PRI_DEV_ERRATUM_ENABLE_RESET - Reset PRI capability when PRI
  37. * is enabled
  38. * - AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE - Limit number of outstanding PRI
  39. * requests to one
  40. */
  41. #define AMD_PRI_DEV_ERRATUM_ENABLE_RESET 0
  42. #define AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE 1
  43. extern void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum);
  44. /**
  45. * amd_iommu_init_device() - Init device for use with IOMMUv2 driver
  46. * @pdev: The PCI device to initialize
  47. * @pasids: Number of PASIDs to support for this device
  48. *
  49. * This function does all setup for the device pdev so that it can be
  50. * used with IOMMUv2.
  51. * Returns 0 on success or negative value on error.
  52. */
  53. extern int amd_iommu_init_device(struct pci_dev *pdev, int pasids);
  54. /**
  55. * amd_iommu_free_device() - Free all IOMMUv2 related device resources
  56. * and disable IOMMUv2 usage for this device
  57. * @pdev: The PCI device to disable IOMMUv2 usage for'
  58. */
  59. extern void amd_iommu_free_device(struct pci_dev *pdev);
  60. /**
  61. * amd_iommu_bind_pasid() - Bind a given task to a PASID on a device
  62. * @pdev: The PCI device to bind the task to
  63. * @pasid: The PASID on the device the task should be bound to
  64. * @task: the task to bind
  65. *
  66. * The function returns 0 on success or a negative value on error.
  67. */
  68. extern int amd_iommu_bind_pasid(struct pci_dev *pdev, u32 pasid,
  69. struct task_struct *task);
  70. /**
  71. * amd_iommu_unbind_pasid() - Unbind a PASID from its task on
  72. * a device
  73. * @pdev: The device of the PASID
  74. * @pasid: The PASID to unbind
  75. *
  76. * When this function returns the device is no longer using the PASID
  77. * and the PASID is no longer bound to its task.
  78. */
  79. extern void amd_iommu_unbind_pasid(struct pci_dev *pdev, u32 pasid);
  80. /**
  81. * amd_iommu_set_invalid_ppr_cb() - Register a call-back for failed
  82. * PRI requests
  83. * @pdev: The PCI device the call-back should be registered for
  84. * @cb: The call-back function
  85. *
  86. * The IOMMUv2 driver invokes this call-back when it is unable to
  87. * successfully handle a PRI request. The device driver can then decide
  88. * which PRI response the device should see. Possible return values for
  89. * the call-back are:
  90. *
  91. * - AMD_IOMMU_INV_PRI_RSP_SUCCESS - Send SUCCESS back to the device
  92. * - AMD_IOMMU_INV_PRI_RSP_INVALID - Send INVALID back to the device
  93. * - AMD_IOMMU_INV_PRI_RSP_FAIL - Send Failure back to the device,
  94. * the device is required to disable
  95. * PRI when it receives this response
  96. *
  97. * The function returns 0 on success or negative value on error.
  98. */
  99. #define AMD_IOMMU_INV_PRI_RSP_SUCCESS 0
  100. #define AMD_IOMMU_INV_PRI_RSP_INVALID 1
  101. #define AMD_IOMMU_INV_PRI_RSP_FAIL 2
  102. typedef int (*amd_iommu_invalid_ppr_cb)(struct pci_dev *pdev,
  103. u32 pasid,
  104. unsigned long address,
  105. u16);
  106. extern int amd_iommu_set_invalid_ppr_cb(struct pci_dev *pdev,
  107. amd_iommu_invalid_ppr_cb cb);
  108. #define PPR_FAULT_EXEC (1 << 1)
  109. #define PPR_FAULT_READ (1 << 2)
  110. #define PPR_FAULT_WRITE (1 << 5)
  111. #define PPR_FAULT_USER (1 << 6)
  112. #define PPR_FAULT_RSVD (1 << 7)
  113. #define PPR_FAULT_GN (1 << 8)
  114. /**
  115. * amd_iommu_device_info() - Get information about IOMMUv2 support of a
  116. * PCI device
  117. * @pdev: PCI device to query information from
  118. * @info: A pointer to an amd_iommu_device_info structure which will contain
  119. * the information about the PCI device
  120. *
  121. * Returns 0 on success, negative value on error
  122. */
  123. #define AMD_IOMMU_DEVICE_FLAG_ATS_SUP 0x1 /* ATS feature supported */
  124. #define AMD_IOMMU_DEVICE_FLAG_PRI_SUP 0x2 /* PRI feature supported */
  125. #define AMD_IOMMU_DEVICE_FLAG_PASID_SUP 0x4 /* PASID context supported */
  126. #define AMD_IOMMU_DEVICE_FLAG_EXEC_SUP 0x8 /* Device may request execution
  127. on memory pages */
  128. #define AMD_IOMMU_DEVICE_FLAG_PRIV_SUP 0x10 /* Device may request
  129. super-user privileges */
  130. struct amd_iommu_device_info {
  131. int max_pasids;
  132. u32 flags;
  133. };
  134. extern int amd_iommu_device_info(struct pci_dev *pdev,
  135. struct amd_iommu_device_info *info);
  136. /**
  137. * amd_iommu_set_invalidate_ctx_cb() - Register a call-back for invalidating
  138. * a pasid context. This call-back is
  139. * invoked when the IOMMUv2 driver needs to
  140. * invalidate a PASID context, for example
  141. * because the task that is bound to that
  142. * context is about to exit.
  143. *
  144. * @pdev: The PCI device the call-back should be registered for
  145. * @cb: The call-back function
  146. */
  147. typedef void (*amd_iommu_invalidate_ctx)(struct pci_dev *pdev, u32 pasid);
  148. extern int amd_iommu_set_invalidate_ctx_cb(struct pci_dev *pdev,
  149. amd_iommu_invalidate_ctx cb);
  150. #else /* CONFIG_AMD_IOMMU */
  151. static inline int amd_iommu_detect(void) { return -ENODEV; }
  152. #endif /* CONFIG_AMD_IOMMU */
  153. #if defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP)
  154. /* IOMMU AVIC Function */
  155. extern int amd_iommu_register_ga_log_notifier(int (*notifier)(u32));
  156. extern int
  157. amd_iommu_update_ga(int cpu, bool is_run, void *data);
  158. extern int amd_iommu_activate_guest_mode(void *data);
  159. extern int amd_iommu_deactivate_guest_mode(void *data);
  160. #else /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */
  161. static inline int
  162. amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
  163. {
  164. return 0;
  165. }
  166. static inline int
  167. amd_iommu_update_ga(int cpu, bool is_run, void *data)
  168. {
  169. return 0;
  170. }
  171. static inline int amd_iommu_activate_guest_mode(void *data)
  172. {
  173. return 0;
  174. }
  175. static inline int amd_iommu_deactivate_guest_mode(void *data)
  176. {
  177. return 0;
  178. }
  179. #endif /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */
  180. #endif /* _ASM_X86_AMD_IOMMU_H */