pl093.h 2.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /* linux/amba/pl093.h
  3. *
  4. * Copyright (c) 2008 Simtec Electronics
  5. * http://armlinux.simtec.co.uk/
  6. * Ben Dooks <ben@simtec.co.uk>
  7. *
  8. * AMBA PL093 SSMC (synchronous static memory controller)
  9. * See DDI0236.pdf (r0p4) for more details
  10. */
  11. #define SMB_BANK(x) ((x) * 0x20) /* each bank control set is 0x20 apart */
  12. /* Offsets for SMBxxxxRy registers */
  13. #define SMBIDCYR (0x00)
  14. #define SMBWSTRDR (0x04)
  15. #define SMBWSTWRR (0x08)
  16. #define SMBWSTOENR (0x0C)
  17. #define SMBWSTWENR (0x10)
  18. #define SMBCR (0x14)
  19. #define SMBSR (0x18)
  20. #define SMBWSTBRDR (0x1C)
  21. /* Masks for SMB registers */
  22. #define IDCY_MASK (0xf)
  23. #define WSTRD_MASK (0xf)
  24. #define WSTWR_MASK (0xf)
  25. #define WSTOEN_MASK (0xf)
  26. #define WSTWEN_MASK (0xf)
  27. /* Notes from datasheet:
  28. * WSTOEN <= WSTRD
  29. * WSTWEN <= WSTWR
  30. *
  31. * WSTOEN is not used with nWAIT
  32. */
  33. /* SMBCR bit definitions */
  34. #define SMBCR_BIWRITEEN (1 << 21)
  35. #define SMBCR_ADDRVALIDWRITEEN (1 << 20)
  36. #define SMBCR_SYNCWRITE (1 << 17)
  37. #define SMBCR_BMWRITE (1 << 16)
  38. #define SMBCR_WRAPREAD (1 << 14)
  39. #define SMBCR_BIREADEN (1 << 13)
  40. #define SMBCR_ADDRVALIDREADEN (1 << 12)
  41. #define SMBCR_SYNCREAD (1 << 9)
  42. #define SMBCR_BMREAD (1 << 8)
  43. #define SMBCR_SMBLSPOL (1 << 6)
  44. #define SMBCR_WP (1 << 3)
  45. #define SMBCR_WAITEN (1 << 2)
  46. #define SMBCR_WAITPOL (1 << 1)
  47. #define SMBCR_RBLE (1 << 0)
  48. #define SMBCR_BURSTLENWRITE_MASK (3 << 18)
  49. #define SMBCR_BURSTLENWRITE_4 (0 << 18)
  50. #define SMBCR_BURSTLENWRITE_8 (1 << 18)
  51. #define SMBCR_BURSTLENWRITE_RESERVED (2 << 18)
  52. #define SMBCR_BURSTLENWRITE_CONTINUOUS (3 << 18)
  53. #define SMBCR_BURSTLENREAD_MASK (3 << 10)
  54. #define SMBCR_BURSTLENREAD_4 (0 << 10)
  55. #define SMBCR_BURSTLENREAD_8 (1 << 10)
  56. #define SMBCR_BURSTLENREAD_16 (2 << 10)
  57. #define SMBCR_BURSTLENREAD_CONTINUOUS (3 << 10)
  58. #define SMBCR_MW_MASK (3 << 4)
  59. #define SMBCR_MW_8BIT (0 << 4)
  60. #define SMBCR_MW_16BIT (1 << 4)
  61. #define SMBCR_MW_M32BIT (2 << 4)
  62. /* SSMC status registers */
  63. #define SSMCCSR (0x200)
  64. #define SSMCCR (0x204)
  65. #define SSMCITCR (0x208)
  66. #define SSMCITIP (0x20C)
  67. #define SSMCITIOP (0x210)